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Subject: Re: SSE related security hole
To: ak@suse.de (Andi Kleen)
Date: Thu, 18 Apr 2002 12:53:12 +0100 (BST)
Cc: alan@lxorguk.ukuu.org.uk (Alan Cox), andrea@suse.de (Andrea Arcangeli),
        dledford@redhat.com (Doug Ledford), jh@suse.cz,
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        pavel@atrey.karlin.mff.cuni.cz
In-Reply-To: <20020418131431.B22558@wotan.suse.de> from "Andi Kleen" at Apr 18, 2002 01:14:31 PM
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> > Intel folks are actually saying even back in Pentium MMX days that it isnt
> > guaranteed that the FP/MMX state are not seperate registers
> 
> In this case it would be possible to only do the explicit clear
> when the CPU does support sse1. For mmx only it shouldn't be needed.
> For sse2 also not.

Do you have a documentation cite for that claim ?
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