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Message-ID: <535171.19301.qm@web37601.mail.mud.yahoo.com>
Date: Thu, 12 Aug 2010 00:27:24 -0700 (PDT)
From: Alex Dubov <oakad@yahoo.com>
Subject: JMicron chipset update
To: Maxim Levitsky <maximlevitsky@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>
In-Reply-To: <1281515524.21459.14.camel@maxim-laptop>
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Apparently, the values I was using to configure a jmicron memstick
interface only work with some chipset revisions. So they've sent me the
following message.

If you've got a working jmicron adapter handy, you may want to try these
changes.

-----------------
We found that there is a definition problem in your code about
JMicron MS Controller.
    Our new product would get problem with this part.
    Following is the bit definition in our code.

    // --- Clock Control Register - Offset 0x48 --- //
    // D[31:4] Reserved
    // D[3]    Force MMIO Control.  0: Control by PCI CNFG, 1: Control
by MMIO.
    // D[2:0]  Clock MUX Select
    #define MSHC_CLKMUX_CONTROL_BY_MMIO   0x00000008
    #define MSHC_CLKMUX_CLK_40MHZ                  0x00000001
    #define MSHC_CLKMUX_CLK_50MHZ                  0x00000002
    #define MSHC_CLKMUX_CLK_62_5MHZ              0x00000004
    #define MSHC_CLKMUX_CLK_60MHZ                  0x00000010  // Must
set PCICnfg Offset BCh D[0] to 1
    #define MSHC_CLKMUX_CLK_OFF                      0x00000000
    #define MSHC_CLKMUX_CLK_MASK                   0x00000017

    Driver have to set this register to 0x08 to clear default clock
setting.
    And then set its value with specfic clock setting (EX:  40MHz ->
0x09, 50MHz -> 0x0A) to change clock.
    (For MS Pro-HG, we suggest to use 50MHz with 8-bit parallel mode.)
   
    Besides, driver have to set the register to 40MHz setting before
identify MS card for safe.


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