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Date: Mon, 30 Aug 2010 15:59:45 +0200
From: Andreas Herrmann <herrmann.der.user@googlemail.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@elte.hu>, Thomas Gleixner <tglx@linutronix.de>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86, k8-gart: Decouple handling of garts and
 northbridges
Message-ID: <20100830135945.GA4749@loge.amd.com>
References: <20100827075945.GA5348@loge.amd.com>
 <4C77F164.8000100@zytor.com>
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On Fri, Aug 27, 2010 at 10:09:56AM -0700, H. Peter Anvin wrote:
> On 08/27/2010 12:59 AM, Andreas Herrmann wrote:
> > From: Andreas Herrmann <andreas.herrmann3@amd.com>
> > 
> > So far we only provide num_k8_northbridges. This is required in
> > different areas (e.g. L3 cache index disable, GART). But not all AMD
> > CPUs provide a GART. Thus it is useful to split off the GART handling
> > from the generic caching of AMD northbridge misc devices.
> > 
> > Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> > ---
> >  arch/x86/include/asm/k8.h             |   13 +++++---
> >  arch/x86/kernel/cpu/intel_cacheinfo.c |    4 +-
> >  arch/x86/kernel/k8.c                  |   52 +++++++++++++++++++--------------
> >  arch/x86/kernel/pci-gart_64.c         |   27 +++++++++++------
> >  drivers/char/agp/amd64-agp.c          |   33 ++++++++++++++------
> >  drivers/edac/amd64_edac.c             |    2 +-
> >  6 files changed, 82 insertions(+), 49 deletions(-)
> > 
> > 
> > Please apply.
> > 
> 
> From just looking at it: isn't this patch going to break compiling with
> CONFIG_K8_NB=n?

Good catch.

Compiled for me after deselecting CONFIG_CPU_SUP_AMD but deselecting
PCI breaks compilation of the L3 cache index disable code. But that
stuff requires PCI support.

Will send updated patch(es) to fix this.


Thanks,

Andreas

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