Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755392Ab0KBBzv (ORCPT ); Mon, 1 Nov 2010 21:55:51 -0400 Received: from smtp-out.google.com ([216.239.44.51]:2392 "EHLO smtp-out.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754919Ab0KBBzu convert rfc822-to-8bit (ORCPT ); Mon, 1 Nov 2010 21:55:50 -0400 DomainKey-Signature: a=rsa-sha1; c=nofws; d=google.com; s=beta; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=H5wzRoDewgexd60SY3UPeVlVwYBrOb2ABpAKqbN5T8uC/AtLMlWgRFmb0YyzovLnv6 R2Yc5E2TV6p4buKdm4HQ== MIME-Version: 1.0 In-Reply-To: <1288620663.2712.84.camel@localhost> References: <1288620663.2712.84.camel@localhost> Date: Tue, 2 Nov 2010 02:55:46 +0100 Message-ID: Subject: Re: [PATCH] wrong PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE_MISSES for AMD From: Stephane Eranian To: =?UTF-8?Q?Robert_Sch=C3=B6ne?= Cc: Vince Weaver , Peter Zijlstra , Robert Richter , Ingo Molnar , x86 , linux-kernel Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-System-Of-Record: true Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1862 Lines: 48 Hi, On Mon, Nov 1, 2010 at 3:11 PM, Robert Schöne wrote: > > The current arch/x86/kernel/cpu/perf_event_amd.c file lists > L1-Instruction-Cache Misses and Accesses as PERF_COUNT_HW_CACHE_MISSES > resp. PERF_COUNT_HW_CACHE_REFERENCES. > I always thought PERF_COUNT_HW_CACHE_* was about data cache misses. But given that there is no clear definitions for those events, it creates confusion. If you change the meaning of HW_CACHE_MISSES, then seems to me, you need to change the mapping in the perf tool, because now it includes both data+code. > This fix uses L2C-Misses and Accesses instead. (Real LLC-events would be > better, but there are some restrictions for Northbridge Events on AMD). > And those constraints are handled correctly by the kernel. The constraint is such that you cannot have more than 4 instances of Northbridge events active at the same time per core. If you do, then one of them will starve (if issued from different cores). > --- a/arch/x86/kernel/cpu/perf_event_amd.c > +++ b/arch/x86/kernel/cpu/perf_event_amd.c > @@ -100,8 +100,8 @@ static const u64 amd_perfmon_event_map[] = >  { >   [PERF_COUNT_HW_CPU_CYCLES]           = 0x0076, >   [PERF_COUNT_HW_INSTRUCTIONS]         = 0x00c0, > -  [PERF_COUNT_HW_CACHE_REFERENCES]     = 0x0080, > -  [PERF_COUNT_HW_CACHE_MISSES]         = 0x0081, > +  [PERF_COUNT_HW_CACHE_REFERENCES]     = 0x037D, > +  [PERF_COUNT_HW_CACHE_MISSES]         = 0x037E, >   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]  = 0x00c2, >   [PERF_COUNT_HW_BRANCH_MISSES]                = 0x00c3, >  }; > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/