Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755581Ab0KRIeu (ORCPT ); Thu, 18 Nov 2010 03:34:50 -0500 Received: from casper.infradead.org ([85.118.1.10]:45339 "EHLO casper.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755554Ab0KRIes convert rfc822-to-8bit (ORCPT ); Thu, 18 Nov 2010 03:34:48 -0500 Subject: Re: [PATCH -v4 1/2] lib, Make gen_pool memory allocator lockless From: Peter Zijlstra To: Huang Ying Cc: huang ying , Andrew Morton , Len Brown , "linux-kernel@vger.kernel.org" , Andi Kleen , "linux-acpi@vger.kernel.org" , Linus Torvalds , Thomas Gleixner , Ingo Molnar , Mauro Carvalho Chehab , Paul Mundt In-Reply-To: <1290042887.3122.5.camel@yhuang-dev> References: <1289868791-16658-1-git-send-email-ying.huang@intel.com> <1289868791-16658-2-git-send-email-ying.huang@intel.com> <20101116135038.fcaa90ca.akpm@linux-foundation.org> <1289960281.8719.1218.camel@yhuang-dev> <1289990458.2109.675.camel@laptop> <1289994796.2109.722.camel@laptop> <1290042887.3122.5.camel@yhuang-dev> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Date: Thu, 18 Nov 2010 09:34:35 +0100 Message-ID: <1290069275.2109.1290.camel@laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1586 Lines: 32 On Thu, 2010-11-18 at 09:14 +0800, Huang Ying wrote: > On Wed, 2010-11-17 at 19:53 +0800, Peter Zijlstra wrote: > > On Wed, 2010-11-17 at 19:47 +0800, huang ying wrote: > > > On Wed, Nov 17, 2010 at 6:40 PM, Peter Zijlstra wrote: > > > > On Wed, 2010-11-17 at 10:18 +0800, Huang Ying wrote: > > > >> > > > >> cmpxchg has been used in that way by ftrace and perf for a long time. So > > > >> I agree to make it a requirement on future architecture ports. > > > > > > > > Neither mandate an architecture do this though, only that when an > > > > architecture wants to support either feature and has NMIs (not all archs > > > > have NMI equivalents) it has to be safe. > > > > > > So we can make sure cmpxchg can be used in lock-less code on > > > architectures with perf, irq_work or ftrace enabled? > > > > It had better, otherwise stuff is broken. > > Take a look at superh architecture cmpxchg implementation. It seems that > cmpxchg is implemented with special instruction if CONFIG_GUSA_RB=y or > CONFIG_CPU_SH4A=y, otherwise it is implemented with local_irq_save. Is > it possible that superh has not PMU support if CONFIG_GUSA_RB=n and > CONFIG_CPU_SH4A=n, so that perf work properly but no NMI safe cmpxchg in > that situation? Dunno, you forgot to CC the author of that code.. I've really no clue about SH. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/