Message-ID: <4D18FF39.6080101@zytor.com>
Date: Mon, 27 Dec 2010 13:03:53 -0800
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Sam Ravnborg <sam@ravnborg.org>
CC: Tejun Heo <tj@kernel.org>, Shaohua Li <shaohua.li@intel.com>,
        lkml <linux-kernel@vger.kernel.org>,
        Andrew Morton <akpm@linux-foundation.org>, eric.dumazet@gmail.com,
        linux-arch@vger.kernel.org
Subject: Re: [PATCH RESEND percpu#for-next] percpu: align percpu readmostly
 subsection to cacheline
References: <20101227133719.GD488@htj.dyndns.org> <20101227204309.GA3878@merkur.ravnborg.org>
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On 12/27/2010 12:43 PM, Sam Ravnborg wrote:
> 
> It would have been better to include cache.h and then use L1_CACHE_BYTES,
> as the value differs for EV4.
> It will work with 64 as this is the bigger of the two.
> 
> It looks like we could do this for almost all archs.
> But then I am not sure if "L1_CACHE_BYTES" is the same as
> a cacheline on the different archs.
> 

For x86, L1 is definitely not the right cache line to use, in terms of
what matters for SMP sharing.  And yes, there are x86's with smaller L1
than L2/3 cache line size.

	-hpa

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