From: Robert Richter <robert.richter@amd.com>
To: Peter Zijlstra <peterz@infradead.org>
CC: Ingo Molnar <mingo@elte.hu>, Stephane Eranian <eranian@google.com>,
        LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH 0/5] perf, x86: perf, x86: Add support for AMD family 15h core counters
Date: Wed, 2 Feb 2011 17:40:55 +0100
Message-ID: <1296664860-10886-1-git-send-email-robert.richter@amd.com>
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This patch set adds support for AMD family 15h core counters. Major
changes compared to family 10h counters are:

* Now there are separate northbridge and core counters that resides in
  different MSR ranges (core: MSRC001_02[0B:00], nb:
  MSRC001_02[47:40]).

* The MSR addresses of perfctr and evntsel registers are now located
  side-by-side, we can not calculate the address with (base + index)
  anymore.

* There are 4 northbridge counters and 6 core counters.

* There are legacy aliases to old MSR counter addresses
  (MSRC001_00[03:00] -> MSRC001_02[07:00] respectively).

* There are restrictions now that not all performance monitor events
  can be counted on all counters.

We need to change MSR address handling of the x86 perf_event
implementation and also add more AMD event constraints to schedule
events.

This patch set only adds core counters.

-Robert


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