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Message-ID: <4D68B397.6040809@gmail.com>
Date: Sat, 26 Feb 2011 11:02:31 +0300
From: Cyrill Gorcunov <gorcunov@gmail.com>
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To: "Maciej W. Rozycki" <macro@linux-mips.org>
CC: Don Zickus <dzickus@redhat.com>, x86@kernel.org,
        Peter Zijlstra <peterz@infradead.org>,
        Robert Richter <robert.richter@amd.com>, ying.huang@intel.com,
        LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 5/6] x86, NMI: Allow NMI reason io port (0x61) to be processed
 on any CPU
References: <1294348732-15030-1-git-send-email-dzickus@redhat.com> <1294348732-15030-6-git-send-email-dzickus@redhat.com> <alpine.LFD.2.00.1102230227010.31425@eddie.linux-mips.org>
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On 02/23/2011 05:39 AM, Maciej W. Rozycki wrote:
...
>
>   [Catching up with old e-mail...]
>
>   In line with the comment above that you're removing -- have you (or
> anyone else) adjusted code elsewhere so that external NMIs are actually
> delivered to processors other than the BSP?  I can't see such code in this
> series nor an explanation as to why it wouldn't be needed.
>
>   For the record -- the piece of code above reflects our setup where the
> LINT1 input is enabled and configured for the NMI delivery mode on the BSP
> only and all the other processors have this line disabled in their local
> APIC units.  If system NMIs are to be handled after the removal of the
> BSP, then another processor has to be selected and configured for NMI
> reception.  Alternatively, all local units could have their LINT1 input
> enabled and arbitrate handling, although it would be quite disruptive as
> all the processors would take the interrupt if it happened.  OTOH it would
> be more fault-tolerant in the case of a CPU failure.  On a typical x86 box
> the system NMI cannot be routed to an I/O APIC input.
>
>    Maciej

   Hi Maciej, good catch! The code doesn't reconfig LVT. As just Don pointed
it might be Intel is working on something, dunno. Probably we better should
drop this patch for now (at least until LVT reconfig would not be implemented).

-- 
     Cyrill
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