Date: Mon, 28 Feb 2011 20:57:50 +0100
From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>, Jan Niehusmann <jan@gondor.com>,
        intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] intel-gtt: fix memory corruption with
 GM965 and >4GB RAM
Message-ID: <20110228195749.GA3597@viiv.ffwll.ch>
Mail-Followup-To: Chris Wilson <chris@chris-wilson.co.uk>,
	Jan Niehusmann <jan@gondor.com>, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
References: <20110223233022.GA3439@x61s.reliablesolutions.de>
 <20110225123056.GA3759@x61s.reliablesolutions.de>
 <b9dded$i2gkhr@orsmga002.jf.intel.com>
 <20110225211646.GA6837@x61s.reliablesolutions.de>
 <b9dded$i2hik6@orsmga002.jf.intel.com>
 <20110225230527.GC3601@viiv.ffwll.ch>
 <20110228064635.GE428@zhen-devel.sh.intel.com>
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In-Reply-To: <20110228064635.GE428@zhen-devel.sh.intel.com>
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On Mon, Feb 28, 2011 at 02:46:35PM +0800, Zhenyu Wang wrote:
> > Actually, on style points I prefer your patch: The hw status page is
> > allocated with drm_pci_alloc which calls dma_alloc_coherent, so setting
> > the coherent mask is sufficient. The dma mask set in the gtt is
> > essentially useless, because we call get_user_pages on everything anyway
> > (in gem - iirc agp uses it). I just think it's confusing to limit the
> > general dma mask and continue to happily map pages above 4G.
> > 
> 
> Think about IOMMU engine, we need to set dma_mask properly for
> returned dma mapping address be limited in max range that can be
> handled in GTT entry. 

If I understand it correctly, this is just about broadwater/crestline,
i.e. the original i965 series. Only the later eaglelake/cantiga (gm45 in
our codebase) was shipped with an iommu attached. So no problem there.
Anyway, my comment was just style nitpick, essentially to keep in line
with the existing  work-around for broken overlay reg files on gen2.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
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