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From: Roland Dreier <roland@purestorage.com>
Date: Wed, 9 Mar 2011 18:05:26 -0800
Message-ID: <AANLkTinrzY56cwB6OX6xcAb5ZWJcZC5cr-knLkCDPy6p@mail.gmail.com>
Subject: Re: [PATCH] Add support for multiple MSI on x86
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
        Micha Nelissen <micha@neli.hopto.org>,
        Jesse Barnes <jbarnes@virtuousgeek.org>,
        Ingo Molnar <mingo@redhat.com>, x86@kernel.org,
        "Venkatesh Pallipadi (Venki)" <venki@google.com>,
        linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
        Matthew Wilcox <matthew@wil.cx>
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> Yes, but there are MSI devices in the field...

But do any of them benefit from having multiple interrupt vectors available?

If I recall correct, willy was motivated by AHCI performance to try this out,
and in the end things didn't go any faster using multiple MSI.

The big win with multiple interrupt vectors is when you have independent
queues that you can point different CPUs at, and give each CPU its own
interrupt.  And that type of hardware is pretty certain to support MSI-X.

 - R.
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