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Date: Sun, 14 Jul 2002 16:58:11 -0400 (EDT)
From: Mark Hahn <hahn@physics.mcmaster.ca>
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To: BALBIR SINGH <balbir.singh@wipro.com>
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Subject: Re: Pentium IV cache line size
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> I think the patch is correct and should be applied.

P4 SMP alignment should be 128B, and that seems to be the main
use of this constant.  I'd *love* to see the spurious "L1" removed - 
in fact, there's already SMP_CACHE_BYTES, which should be used instead.
maybe just CACHE_SHIFT/BYTES, since alignment is used for uni, too.

perhaps a janitor/trivial patch for 2.5?


> >From Pentium IV, System Programming Guide, Section 9.1, Page 9-2,
> Table 9-1. Order # 245472

dueling references!  mine are from the p4 and xeon opt guide.  page 7-9:
Key Practices of Thread Synchronization:
...
	- Place each synchronization variable alone, 
	separated by 128 byte or in a separate cache line.

see also table 1.1.  I'm not sure it matters whether you consider lines 128B
or 64B; the fact that cacheline reads always happen at 128B is probably
the dominant concern.  table 1.1 page 7-18 ("placement of shared
synchonization variable") repeats this.

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