Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754630Ab1D1HYc (ORCPT ); Thu, 28 Apr 2011 03:24:32 -0400 Received: from mail-yi0-f46.google.com ([209.85.218.46]:34927 "EHLO mail-yi0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754586Ab1D1HYb (ORCPT ); Thu, 28 Apr 2011 03:24:31 -0400 DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; b=Zc4Qj1tLUbP38oqZKwKDPQtpeeLcGab5+rVcxwcJ1HmOPdIMEspr9S7mOjNGrRtW9H geY/ua436vBwjH/d0gvnBAeQq4lR73jjJ0TbnADeVNTKxG42JhlzEfOouyKb76Nv08DN acHLsULwYKFJw60CeCC8anRZ9qPa+PWssJtao= MIME-Version: 1.0 In-Reply-To: <1303940737.2513.190.camel@pasglop> References: <201104212129.17013.arnd@arndb.de> <1303940737.2513.190.camel@pasglop> Date: Thu, 28 Apr 2011 16:24:30 +0900 X-Google-Sender-Auth: VB2Q7FAAwJ1FL-ZOcs4D_hHBjDo Message-ID: Subject: Re: [Linaro-mm-sig] [RFC] ARM DMA mapping TODO, v1 From: KyongHo Cho To: Benjamin Herrenschmidt Cc: Catalin Marinas , linaro-mm-sig@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Arnd Bergmann , linux-kernel@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1359 Lines: 33 On Thu, Apr 28, 2011 at 6:45 AM, Benjamin Herrenschmidt wrote: > > Don't you have a risk where speculative loads or prefetches might bring > back some stuff into the cache via the cachable mapping ? Is that an > issue ? As long as it's non-dirty and the cachable mapping isn't > otherwise used, I suppose it might be a non-issue, tho I've seen in > powerpc land cases of processors that can checkstop if a subsequent non > cachable access "hits" the stuff that was loaded in the cache. > > Cheers, > Ben. > As far as I know, ARM processors does not have the capability to detect non-cacheable access hits the stuff in the cache. IMHO, speculative prefetch becomes a problem when a coherent buffer (that is not-cacheable in ARM) is modified by a DMA transaction while old data is already loaded in the cache via another cacheable mapping onto the buffer even though it is never touched by CPU. We can avoid this problem if the kernel removes 'executable' property from the cacheable mapping. But it is not able to modify page table entries in the direct mapping area. Regards, KyongHo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/