Date: Mon, 9 May 2011 11:32:42 +0100
From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Will Deacon <Will.Deacon@arm.com>
Subject: Re: [PATCH v5 02/19] ARM: LPAE: add ISBs around MMU enabling code
Message-ID: <20110509103242.GQ27807@n2100.arm.linux.org.uk>
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On Mon, May 09, 2011 at 11:22:19AM +0100, Catalin Marinas wrote:
> Alternatively an exception return would do as well (like movs pc, lr)
> but I think we still add some code for setting up the SPSR.

That gives us a way out of both of these without introducing any CPU
specific code.  We can setup the SPSR before this block of code, and
call it with two movs pc, reg instructions which will provide the
necessary synchronization.

That sounds to me like an all-round better solution here.
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