Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752410Ab1EIPZz (ORCPT ); Mon, 9 May 2011 11:25:55 -0400 Received: from mho-04-ewr.mailhop.org ([204.13.248.74]:28435 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752097Ab1EIPZy (ORCPT ); Mon, 9 May 2011 11:25:54 -0400 X-Mail-Handler: MailHop Outbound by DynDNS X-Originating-IP: 98.234.237.12 X-Report-Abuse-To: abuse@dyndns.com (see http://www.dyndns.com/services/mailhop/outbound_abuse.html for abuse reporting information) X-MHO-User: U2FsdGVkX19Q6k6P4oWdxMsbVv4vNSc+ Date: Mon, 9 May 2011 08:25:47 -0700 From: Tony Lindgren To: Mike Rapoport Cc: Colin Cross , Stephen Warren , Linus Walleij , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Grant Likely , Lee Jones , Martin Persson , Linus Walleij , "linux-tegra@vger.kernel.org" , Erik Gilling Subject: Re: [PATCH 1/4] drivers: create a pinmux subsystem Message-ID: <20110509152547.GD11410@atomide.com> References: <1304363786-30376-1-git-send-email-linus.walleij@stericsson.com> <74CDBE0F657A3D45AFBB94109FB122FF0497F1B201@HQMAIL01.nvidia.com> <20110504092219.GW2092@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1612 Lines: 32 * Mike Rapoport [110507 12:03]: > On Wed, May 4, 2011 at 12:22 PM, Tony Lindgren wrote: > > * Colin Cross [110502 14:26]: > >> On Mon, May 2, 2011 at 1:52 PM, Stephen Warren wrote: > >> > >> * Drive strength is also controlled through groups of pins, but > >> different groups than pinmux.  Most of the drive strength groups are > >> collections of pad mux groups, but there are a few pins that are in > >> the same pad mux group but a different drive strength group. > >> * Setting a pin as a GPIO overrides its group's mux setting, except > >> for the group's tristate.  You must untristate the entire group to use > >> a single pin as a GPIO. > >> * Each group has a "safe mode", but which mux id to select to enter > >> the safe mode is completely random. > > > > Just posted something in this thread regarding using standard data and > > standard read and write functions, then allow setting platform specific > > custom flags as needed. Care to see if that works for you too? > > Tegra does not allow pin muxing on the pin by pin basis. And, > registers that define mux config differ from those that define flags > (pull, driver strength, safe mode etc). Hmm well the separate config register could be added easily. But the grouping of pins might be tricky then :) Tony -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/