Date: Fri, 13 May 2011 17:19:23 +0200
From: Hans Rosenfeld <hans.rosenfeld@amd.com>
To: Chuck Ebbert <cebbert@redhat.com>
CC: "Ostrovsky, Boris" <Boris.Ostrovsky@amd.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Petkov, Borislav" <Borislav.Petkov@amd.com>
Subject: Re: [PATCH] cpu, AMD: Fix another bug in the new errata checking code
Message-ID: <20110513151921.GA878@escobedo.osrc.amd.com>
References: <20110512195938.1728ab52@katamari>
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 <4DCD2C3F.9070905@amd.com>
 <20110513105928.6216ddc8@katamari>
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On Fri, May 13, 2011 at 10:59:28AM -0400, Chuck Ebbert wrote:
> On Fri, 13 May 2011 09:03:59 -0400
> Boris Ostrovsky <boris.ostrovsky@amd.com> wrote:
> 
> > On 05/13/2011 06:21 AM, Hans Rosenfeld wrote:
> > > On Thu, May 12, 2011 at 07:59:38PM -0400, Chuck Ebbert wrote:
> > > The revision guide states that family 0x10 model 6 stepping 2 has E400.
> > > So I would expect that OSVW length is>= 2 and that OSVW status has bit
> > > 1 set, or that OSVW length is<  2. This indicates that the workaround is
> > > necessary, without any need to check the family-model-stepping ranges.
> > >
> > > It would also be correct if the BIOS disabled C1E and cleared the
> > > corresponding OSVW status bit. Anything else would probably be a very
> > > nasty BIOS bug.
> > >
> 
> > > Could you send me the contents of MSRs 0xc0010140, 0xc0010141 and
> > > 0xc0010055?
> > 
> > Knowing whether any C state above C1 is declared could be useful too.
> > 
> rdmsr 0xc0010140 gives 2

This means that E400 is known ...

> rdmsr 0xc0010141 gives 0

... and no workaround is necessary ...

> rdmsr 0xc0010055 gives 0

... because C1E is not enabled.

> And ARAT is definitely set where it wasn't before these updates.

I don't see how that could possibly make a difference if C1E is not even
enabled. This is all very strange.


Hans


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