Date: Wed, 25 May 2011 09:58:03 -0700
From: Andi Kleen <ak@linux.intel.com>
To: Henrique de Moraes Holschuh <hmh@hmh.eng.br>
Cc: Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
        x86@kernel.org, linux-kernel@vger.kernel.org,
        Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH 1/3] x86, intel: Output microcode revision
Message-ID: <20110525165803.GB14958@tassilo.jf.intel.com>
References: <1306278210-18285-1-git-send-email-andi@firstfloor.org>
 <20110525070604.GE429@elte.hu>
 <20110525160656.GB25225@khazad-dum.debian.net>
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> > This can happen if for example the BIOS somehow does not apply the right 
> > microcode to all CPUs. It can also happen if physically different microcode 
> > version CPUs are mixed. In theory people can mix steppings as well.
> 
> In PRACTICE people WILL mix steppings as well.

Yes exactly. I used to have a system with one P3 supporting FXSAVE
and other not :-) I had to fix the kernel back then to support this.
The system worked perfectly fine after the kernel was fixed.

So the check proposed is a bad idea. It would trigger
on real boxes which don't have any obvious problems.

-Andi
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