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Date: Mon, 29 Jul 2002 10:56:26 +0200
From: Lionel Bouton <Lionel.Bouton@inet6.fr>
To: Daniela Engert <dani@ngrt.de>
Cc: linux-kernel <linux-kernel@vger.kernel.org>,
       "L.C. Chang" <lcchang@sis.com.tw>
Subject: Re: SiS 5513 ATA133 support patch for 2.4.19-rc3-ac3
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	"L.C. Chang" <lcchang@sis.com.tw>
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On lun, jui 29, 2002 at 09:11:34 +0200, Daniela Engert wrote:
> On Mon, 29 Jul 2002 01:37:54 +0200, Lionel Bouton wrote:
> 
> 
> Lionel,
> 
> as you already figured out, looking at the northbridge IDs is simply
> not sufficient to find out which capabilities and register layout the
> IDE controller in the southbridge (no matter if integrated or external)
> has.
> 
> Some comments:
> 
> 1) the 745 has an integrated southbridge and an ATA/100 capable IDE
> controller
> 

I believed so too, but Lei-Chun patch changed it to ATA133.
Lei-Chun, could you tell us what we can expect from 745 chips ?

> 2) the 646 (and most likely the 645 and others as well) may be paired
> with a 961 (ATA/100) or 961B (ATA133) MutIOL southbridge with different
> register programming values.
> 
> Thus simply ripping out some northbridge IDs wouldn't prevent
> corruption problems.
> 

I don't see why (unless you refer to the 962/963 problem I did mention).
If we remove the IDs, the chips will be detected as SiS5513 (ATA_16). If
I'm correct, in this mode (only allowing PIO modes and SW/MW DMA modes)
all chips are OK.
I didn't dig in all specs to check each config register change, but all I
saw was OK and I *never* received any data corruption report for a chip that
was configured as original SiS5513 (though I have many reports of bad
performance due to PIO modes being used in such cases).

LB.
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