From: Eric Anholt <eric@anholt.net>
To: Ben Widawsky <ben@bwidawsk.net>,
        Daniel J Blueman <daniel.blueman@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
        Dave Airlie <airlied@redhat.com>
Subject: Re: [Intel-gfx] [PATCH 3.0-rc3] i915: Fix gen6 (SNB) GPU stalling
In-Reply-To: <20110615151654.GA31881@snipes.kumite>
References: <1308070307-2630-1-git-send-email-daniel.blueman@gmail.com> <20110615044359.GA27884@snipes.kumite> <BANLkTin1fqKMzutfOyLNegOGOuSQu-4jpA@mail.gmail.com> <20110615151654.GA31881@snipes.kumite>
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Date: Thu, 16 Jun 2011 11:36:21 -0700
Message-ID: <87wrgl8vyy.fsf@eliezer.anholt.net>
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On Wed, 15 Jun 2011 08:16:54 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> On Wed, Jun 15, 2011 at 01:04:51PM +0800, Daniel J Blueman wrote:
> > The render HWSTAM is tweaked in preinstall, but we need to tweak the
> > blitter HWSTAM (new to gen6).
> >=20
> > To me, it makes sense to reset the blitter HWSTAM register to what the
> > driver expects, in case anything before the i915 module loads and
> > adjusts it for a particular purpose (including debug); the render
> > HWSTAM is set this way too. I could add a comment to both perhaps?
>=20
> Well on that note, the docs clearly state only 1 bit can be unmasked at
> a time. Not sure if that applies to masking as well, but if it does,
> that would be not good.

This is because HWSTAM controls writes of the current ISR to the status
page, not IIR.  If you wanted to hear about more than one bit of
interrupts in that field, you'd potentially lose one of them because ISR
is "things interrupting at this very moment" not "things that have
interrupted since you last checked".  This is one of those few cases
where the hardware docs are telling you how to build software in order
to not fail, rather than telling you information about the hardware.

Given that we never look at that ISR field, then, it shouldn't matter
that we have more than one set for the render engine.

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