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From: David Woodhouse <dwmw2@infradead.org>
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To: Linus Torvalds <torvalds@transmeta.com>
Cc: davidm@hpl.hp.com, Alan Cox <alan@lxorguk.ukuu.org.uk>,
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Subject: Re: adjust prefetch in free_one_pgd() 
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torvalds@transmeta.com said:
>  I don't think that non-cache-coherency wrt DMA necessarily means that
> that is true, though. If you flush all CPU caches to memory before
> starting the DMA, and you invalidate the DMA'd memory range _after_
> the DMA finished, a "prefetch" on such an architecture is not a
> problem at all. 

OK -- assuming you actually do flush before the DMA and invalidate 
afterwards, that works. That's what I was missing; thanks :)

That's for a prefetch operation which doesn't mark the cache line 
dirty/owned. If you have random addresses used with 'write prefetch' 
operations, that's still going to be a problem.

--
dwmw2


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