Message-ID: <4FA94239.2010503@linux.intel.com>
Date: Tue, 08 May 2012 08:56:41 -0700
From: Andi Kleen <ak@linux.intel.com>
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To: "H. Peter Anvin" <hpa@zytor.com>
CC: Alex Shi <alex.shi@intel.com>, mgorman@suse.de, npiggin@gmail.com,
        tglx@linutronix.de, mingo@redhat.com, arnd@arndb.de,
        rostedt@goodmis.org, fweisbec@gmail.com, jeremy@goop.org,
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        luto@mit.edu, avi@redhat.com, len.brown@intel.com, dhowells@redhat.com,
        fenghua.yu@intel.com, borislav.petkov@amd.com, yinghai@kernel.org,
        cpw@sgi.com, steiner@sgi.com, akpm@linux-foundation.org,
        penberg@kernel.org, hughd@google.com, rientjes@google.com,
        kosaki.motohiro@jp.fujitsu.com, n-horiguchi@ah.jp.nec.com,
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Subject: Re: [PATCH v3 4/7] x86/tlb: add tlb flush all factor for specific
 CPUs
References: <1336485790-30902-1-git-send-email-alex.shi@intel.com> <1336485790-30902-5-git-send-email-alex.shi@intel.com> <4FA938AE.9070209@zytor.com>
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> This seems a bit concerning from a forward compatibility point of view.
>   It would make more sense to assume that future processors would behave
> more like the most recent (Sandy Bridge in your case) unless there is
> evidence to the contrary.
This would not work on new Atoms, which inter mix model numbers.

In the past I did a hack in other software to check the cache sizes to 
distinguish the two
for unknown models It's not pretty however.

-Andi


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