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Subject: Re: [PATCH] [2.5] asm-generic/atomic.h and changes to arm, parisc,
	mips, m68k, sh, cris to use it
From: Luca Barbieri <ldb@ldb.ods.org>
To: David Woodhouse <dwmw2@infradead.org>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>, Roman Zippel <zippel@linux-m68k.org>,
       Linux-Kernel ML <linux-kernel@vger.kernel.org>
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On Mon, 2002-08-12 at 13:16, David Woodhouse wrote:
> 
> alan@lxorguk.ukuu.org.uk said:
> >  Possibly not - volatile doesnt guarantee the compiler won't do
> > 	x = 1
> > 	add *p into x
> > 	store x into *p
> 
> Er, AIUI 'volatile' guarantees that '*p++' will do precisely that. It's a 
> load, an add and a store, and the rules about volatile mean that the load 
> and the store _must_ be separate.

I noticed that while testing how rmk's code behaved differently than
mine (and corrected in the v2 patch).
Before that, I just assumed that since the CPU must anyway issue a
separate load and store, the compiler would use the faster instruction
(that's why there is a LOCK prefix in the i386 instruction set).


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