Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760064Ab2EVSBE (ORCPT ); Tue, 22 May 2012 14:01:04 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:36311 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759922Ab2EVR76 (ORCPT ); Tue, 22 May 2012 13:59:58 -0400 From: David Daney To: devicetree-discuss@lists.ozlabs.org, Grant Likely , Rob Herring , "David S. Miller" , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Andy Fleming , David Daney Subject: [PATCH 5/5] netdev/phy: Add driver for Cortina cs4321 quad 10G PHY. Date: Tue, 22 May 2012 10:59:52 -0700 Message-Id: <1337709592-23347-6-git-send-email-ddaney.cavm@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1337709592-23347-1-git-send-email-ddaney.cavm@gmail.com> References: <1337709592-23347-1-git-send-email-ddaney.cavm@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 121920 Lines: 5625 From: David Daney These phys do *not* implement the standard IEEE 802.3 clause 45 registers. PHY to driver matching is done with OF compatible properties. Signed-off-by: David Daney --- .../devicetree/bindings/net/cortina-cs4321.txt | 27 + drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/cs4321-ucode.h | 4378 ++++++++++++++++++++ drivers/net/phy/cs4321.c | 1147 +++++ 5 files changed, 5559 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/cortina-cs4321.txt create mode 100644 drivers/net/phy/cs4321-ucode.h create mode 100644 drivers/net/phy/cs4321.c diff --git a/Documentation/devicetree/bindings/net/cortina-cs4321.txt b/Documentation/devicetree/bindings/net/cortina-cs4321.txt new file mode 100644 index 0000000..a1b6f48 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cortina-cs4321.txt @@ -0,0 +1,27 @@ +Cortina CS4321 dual RXAIU/quad XAUI 10G Ethernet PHYs. Each PHY +within the package is mostly independent and has the following +properties. These phys do *not* implement the standard IEEE 802.3 +clause 45 registers. + +Required Properties: + +- compatible : "cortina,cs4321" or "cortina,cs4318". +- reg : The address on the system management bus (MDIO/I2C/SPI address) +- cortina,host-mode : Either "rxaui" or "xaui", the protocol used to + communicate with the Ethernet MAC. + +Optional Properties: + +- interrupts : One set of cells (per the interrupt-parent) for the + interrupt line. +- interrupt-parent : Standard interrupt-parent property for the interrupt. + +Example: + + phy0: ethernet-phy@4 { + reg = <0x04>; + compatible = "cortina,cs4318"; + interrupt-parent = <&gpio>; + interrupts = <11 8>; /* Pin 11, active low */ + cortina,host-mode = "rxaui"; + }; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 9e36c8f..1d977f9 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -72,6 +72,12 @@ config BCM87XX_PHY help Currently supports the BCM8706 and BCM8727 10G Ethernet PHYs. +config CS4318_PHY + tristate "Driver for Cortina cs4318 quad-10G Ethernet PHY" + help + Currently supports only the Cortina cs4318 PHY. This may be + configured as either a quad-RXAUI or dual-XAUI device. + config ICPLUS_PHY tristate "Drivers for ICPlus PHYs" ---help--- diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 6d2dc6c..c99f64c 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_VITESSE_PHY) += vitesse.o obj-$(CONFIG_BROADCOM_PHY) += broadcom.o obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o +obj-$(CONFIG_CS4318_PHY) += cs4321.o obj-$(CONFIG_ICPLUS_PHY) += icplus.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o diff --git a/drivers/net/phy/cs4321-ucode.h b/drivers/net/phy/cs4321-ucode.h new file mode 100644 index 0000000..98f05ac --- /dev/null +++ b/drivers/net/phy/cs4321-ucode.h @@ -0,0 +1,4378 @@ +/* + * Copyright (C) 2011 by Cortina Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* + * The following arrays contain the microcode data to download to the + * device. + */ +static u16 cs4321_microcode_prolog[] = { + /* Addr, Data */ + 0x001c, 0x0001, + 0x0020, 0x8004, + 0x0240, 0x0008, + 0x024f, 0x0000 +}; + +/* + * Each slice is written: + * 0x024f, slice_number + * for each element in slice: + * 0x0201, first_value + * 0x0202, second_value + * 0x0200, element index + 0x9000 + */ +static u16 cs4321_microcode_slices[8][512 * 2] = {{ + 0x009a, 0xb616, + 0x0060, 0x01e6, + 0x0088, 0xbf02, + 0x0000, 0x0000, + 0x0083, 0xc184, + 0x0003, 0xc084, + 0x0083, 0x4f4b, + 0x0003, 0x4190, + 0x0003, 0x4f83, + 0x0083, 0x408e, + 0x0083, 0xe0db, + 0x0083, 0xc0ec, + 0x0003, 0xc0eb, + 0x0003, 0xc0ee, + 0x0083, 0xc0ea, + 0x0003, 0xc696, + 0x0004, 0xed04, + 0x0083, 0xc0bf, + 0x001a, 0x3501, + 0x0060, 0x01e6, + 0x0083, 0xc086, + 0x001a, 0xb701, + 0x0060, 0x01e6, + 0x00ba, 0x0020, + 0x009b, 0x03bf, + 0x0020, 0x001f, + 0x0083, 0xc0bf, + 0x001a, 0x3703, + 0x0060, 0x01e6, + 0x0003, 0xc2bf, + 0x0060, 0x01e6, + 0x008a, 0xde02, + 0x0080, 0x0023, + 0x008e, 0x8502, + 0x0080, 0x0015, + 0x0018, 0x9300, + 0x0003, 0x0393, + 0x001b, 0x4f80, + 0x0083, 0x0380, + 0x0083, 0xd497, + 0x0083, 0xd498, + 0x0003, 0xd499, + 0x0083, 0xc0b9, + 0x0083, 0xc7ff, + 0x0003, 0xc082, + 0x0024, 0x8508, + 0x001b, 0x57ba, + 0x0097, 0x5703, + 0x00a0, 0x0035, + 0x000f, 0x8585, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0x49b8, + 0x0083, 0xc052, + 0x0098, 0x5200, + 0x0083, 0x0352, + 0x0099, 0xb853, + 0x0003, 0x03b8, + 0x0083, 0xd497, + 0x0083, 0xd498, + 0x0003, 0xd499, + 0x00a4, 0x8505, + 0x001b, 0x57ba, + 0x0097, 0x5703, + 0x0020, 0x0043, + 0x008f, 0x8587, + 0x0003, 0xc082, + 0x0003, 0xd689, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xc182, + 0x009a, 0x0104, + 0x0083, 0x03b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0093, 0x0000, + 0x001f, 0x8761, + 0x0003, 0x03f6, + 0x001a, 0x0160, + 0x001e, 0x03f6, + 0x0003, 0x03f6, + 0x0017, 0xd103, + 0x0041, 0x0056, + 0x0083, 0xd1fb, + 0x0080, 0x005d, + 0x001a, 0x0094, + 0x0017, 0xf603, + 0x0041, 0x005c, + 0x001a, 0x0094, + 0x0083, 0x03fb, + 0x0080, 0x005d, + 0x0083, 0xf6fb, + 0x0003, 0xc0e4, + 0x0018, 0xe400, + 0x0003, 0x03e4, + 0x0003, 0xd299, + 0x0083, 0xd298, + 0x0083, 0xd297, + 0x0083, 0xcbf9, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xc1b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xcff9, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xc2b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd5b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xcef9, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x001f, 0xc20f, + 0x009e, 0xd303, + 0x0083, 0x0397, + 0x0003, 0xd398, + 0x0083, 0xd399, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x009f, 0xe40f, + 0x0017, 0xd703, + 0x00c1, 0x005e, + 0x0083, 0xd297, + 0x0083, 0xd298, + 0x0003, 0xd299, + 0x008b, 0x8515, + 0x0083, 0x5089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x000b, 0x8511, + 0x0083, 0x5089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x008b, 0x850d, + 0x0083, 0x5089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0004, 0xb609, + 0x008b, 0x8508, + 0x001a, 0x001c, + 0x0097, 0x03b6, + 0x0041, 0x00a6, + 0x0097, 0xb64b, + 0x0041, 0x00a6, + 0x0083, 0xb64b, + 0x0083, 0xb84c, + 0x001a, 0x000b, + 0x0097, 0x5203, + 0x00a1, 0x0037, + 0x0083, 0x4cb8, + 0x0083, 0xd497, + 0x0083, 0xd498, + 0x0003, 0xd499, + 0x00a4, 0x8505, + 0x001b, 0x57ba, + 0x0097, 0x5703, + 0x00a0, 0x00b2, + 0x008f, 0x8584, + 0x0003, 0xc082, + 0x0003, 0xd689, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xc182, + 0x001f, 0xc20f, + 0x009e, 0xd303, + 0x0083, 0x0397, + 0x0003, 0xd398, + 0x0083, 0xd399, + 0x0083, 0xd297, + 0x0083, 0xd298, + 0x0003, 0xd299, + 0x001b, 0x57ba, + 0x0083, 0x03b9, + 0x009f, 0xd20f, + 0x0091, 0x0380, + 0x0083, 0x0380, + 0x001a, 0xb701, + 0x0060, 0x01e6, + 0x00ba, 0x0020, + 0x009b, 0x03bf, + 0x0020, 0x00ce, + 0x0083, 0xc0bf, + 0x001a, 0x3703, + 0x0060, 0x01e6, + 0x0003, 0xc2bf, + 0x0060, 0x01e6, + 0x009b, 0x57a3, + 0x0060, 0x01dc, + 0x0083, 0x03ef, + 0x009b, 0x57a0, + 0x0060, 0x01dc, + 0x0083, 0x03dc, + 0x0018, 0xee00, + 0x0003, 0x03ee, + 0x0017, 0x59ee, + 0x0041, 0x011f, + 0x0003, 0xc0ee, + 0x0084, 0xed0f, + 0x009a, 0x8086, + 0x0083, 0x03bf, + 0x009a, 0x3408, + 0x0060, 0x01e6, + 0x001a, 0xb40b, + 0x0060, 0x01e6, + 0x0097, 0xbf60, + 0x0020, 0x00e5, + 0x0083, 0xbf60, + 0x0003, 0xc1bf, + 0x0080, 0x00e6, + 0x0083, 0xc0bf, + 0x001a, 0x3501, + 0x0060, 0x01e6, + 0x0093, 0x0000, + 0x001f, 0x8761, + 0x0003, 0x03f6, + 0x001a, 0x0160, + 0x001e, 0x03f6, + 0x0003, 0x03f6, + 0x0017, 0xd103, + 0x00c1, 0x00f2, + 0x0083, 0xd1fb, + 0x0000, 0x00f9, + 0x001a, 0x0094, + 0x0017, 0xf603, + 0x00c1, 0x00f8, + 0x001a, 0x0094, + 0x0083, 0x03fb, + 0x0000, 0x00f9, + 0x0083, 0xf6fb, + 0x009b, 0xa155, + 0x0003, 0x03e2, + 0x009a, 0x0055, + 0x0017, 0xe203, + 0x00c1, 0x0103, + 0x0084, 0xb90b, + 0x001f, 0xc10f, + 0x009e, 0xb903, + 0x0083, 0x03b9, + 0x0080, 0x0109, + 0x0097, 0x54e2, + 0x00c1, 0x0109, + 0x0017, 0xb957, + 0x0020, 0x0109, + 0x0098, 0xb900, + 0x0083, 0x03b9, + 0x009e, 0x55c4, + 0x0097, 0xb903, + 0x00c1, 0x0114, + 0x0004, 0xff13, + 0x009f, 0xff0f, + 0x009e, 0x03c1, + 0x0003, 0x03ff, + 0x001f, 0xb90f, + 0x0019, 0x03c8, + 0x0083, 0x03b9, + 0x0000, 0x011f, + 0x0099, 0xcc55, + 0x0097, 0x03b9, + 0x0041, 0x011f, + 0x009f, 0xff0f, + 0x0097, 0x03c7, + 0x0041, 0x011f, + 0x0018, 0xff00, + 0x0003, 0x03ff, + 0x001f, 0xb90f, + 0x009e, 0x03c8, + 0x0083, 0x03b9, + 0x0085, 0xeb07, + 0x0003, 0xc145, + 0x0098, 0xea00, + 0x0083, 0x03ea, + 0x0097, 0x48ea, + 0x0041, 0x0134, + 0x0083, 0xc1eb, + 0x008f, 0xdc0a, + 0x001b, 0xa055, + 0x0017, 0xc903, + 0x00c1, 0x012d, + 0x0083, 0xc045, + 0x0083, 0xc242, + 0x0000, 0x0134, + 0x0003, 0xc245, + 0x0003, 0xc042, + 0x0000, 0x0134, + 0x001b, 0xa055, + 0x0097, 0xc103, + 0x00c1, 0x012d, + 0x0000, 0x012a, + 0x001b, 0xa355, + 0x0017, 0xcc03, + 0x00c1, 0x013c, + 0x001f, 0xc80f, + 0x009e, 0xd303, + 0x0003, 0x0344, + 0x0003, 0xc843, + 0x0000, 0x0145, + 0x008f, 0xef06, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xd344, + 0x0083, 0xc043, + 0x0000, 0x0145, + 0x0017, 0xc503, + 0x00c1, 0x013f, + 0x0000, 0x0137, + 0x009b, 0xa155, + 0x0003, 0x03e2, + 0x001a, 0x0040, + 0x0017, 0xe203, + 0x0041, 0x0152, + 0x0083, 0xc296, + 0x009f, 0xd20f, + 0x0019, 0xc103, + 0x0083, 0x0398, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xd298, + 0x0003, 0xc696, + 0x009b, 0xa755, + 0x0017, 0x5a03, + 0x00c1, 0x015c, + 0x009a, 0x000a, + 0x009e, 0xd303, + 0x0083, 0x0346, + 0x009a, 0x000a, + 0x0003, 0x0347, + 0x0000, 0x0164, + 0x000f, 0xa704, + 0x0003, 0xd346, + 0x0003, 0xc047, + 0x0000, 0x0164, + 0x009b, 0xa755, + 0x0097, 0xc203, + 0x0041, 0x015d, + 0x0080, 0x0156, + 0x009f, 0xd20f, + 0x0011, 0x0344, + 0x0083, 0x0398, + 0x009f, 0xd20f, + 0x0091, 0x0345, + 0x0083, 0x0397, + 0x009f, 0xd20f, + 0x0091, 0x0346, + 0x0003, 0x0399, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd299, + 0x0083, 0xd298, + 0x0083, 0xd297, + 0x0088, 0xde22, + 0x001a, 0x000d, + 0x009e, 0x8303, + 0x0083, 0x0383, + 0x0003, 0xcc4b, + 0x009c, 0x58e5, + 0x0003, 0x034d, + 0x009e, 0x834b, + 0x0083, 0x0383, + 0x001c, 0x4bc1, + 0x0003, 0x034b, + 0x0017, 0x4b4d, + 0x0020, 0x0184, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0000, 0x017a, + 0x0083, 0x5089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0091, 0x834b, + 0x0083, 0x0383, + 0x009d, 0x4bc1, + 0x0003, 0x034b, + 0x0017, 0x4bc9, + 0x00a0, 0x0191, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0080, 0x0187, + 0x001a, 0x001f, + 0x0091, 0x8303, + 0x0083, 0x0383, + 0x0000, 0x0198, + 0x0083, 0x5089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0080, 0x019a, + 0x0000, 0x0006, + 0x0091, 0x40ca, + 0x0011, 0x5c03, + 0x0003, 0x038e, + 0x001e, 0x41c5, + 0x001e, 0x0348, + 0x0003, 0x0390, + 0x001f, 0xc80f, + 0x0091, 0x0351, + 0x0083, 0x0391, + 0x0083, 0x0392, + 0x009f, 0xd20f, + 0x0091, 0x0343, + 0x0083, 0x0398, + 0x009f, 0xd20f, + 0x0011, 0x0342, + 0x0083, 0x0397, + 0x009f, 0xd20f, + 0x0011, 0x0347, + 0x0003, 0x0399, + 0x0083, 0xcbf9, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xc1b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xd297, + 0x0083, 0xd298, + 0x0003, 0xd299, + 0x0083, 0x408e, + 0x0003, 0x4190, + 0x009f, 0xc50f, + 0x0099, 0x03c9, + 0x0091, 0x0351, + 0x0083, 0x0391, + 0x0083, 0x0392, + 0x0003, 0xcff9, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xc2b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd5b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xcef9, + 0x0098, 0xec00, + 0x0083, 0x03ec, + 0x009a, 0x0050, + 0x0097, 0x03ec, + 0x00c1, 0x01d8, + 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0x0018, 0xee00, + 0x0003, 0x03ee, + 0x0017, 0x59ee, + 0x00c1, 0x003b, + 0x0003, 0xc0ee, + 0x001f, 0xdf0f, + 0x0017, 0x03fa, + 0x0041, 0x0039, + 0x001f, 0xc10f, + 0x001e, 0xfa03, + 0x0003, 0x03fa, + 0x0060, 0x0158, + 0x0060, 0x0131, + 0x0085, 0xeb07, + 0x0003, 0xc145, + 0x0098, 0xea00, + 0x0083, 0x03ea, + 0x0097, 0x48ea, + 0x0041, 0x0050, + 0x0083, 0xc1eb, + 0x008f, 0xdc0a, + 0x001b, 0xa055, + 0x0017, 0xc903, + 0x00c1, 0x0049, + 0x0083, 0xc045, + 0x0083, 0xc242, + 0x0000, 0x0050, + 0x0003, 0xc245, + 0x0003, 0xc042, + 0x0000, 0x0050, + 0x001b, 0xa055, + 0x0097, 0xc103, + 0x00c1, 0x0049, + 0x0080, 0x0046, + 0x001b, 0xa355, + 0x0017, 0xcc03, + 0x00c1, 0x0058, + 0x001f, 0xc80f, + 0x009e, 0xd303, + 0x0003, 0x0344, + 0x0003, 0xc843, + 0x0080, 0x0061, + 0x008f, 0xef06, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xd344, + 0x0083, 0xc043, + 0x0080, 0x0061, + 0x0017, 0xc503, + 0x00c1, 0x005b, + 0x0000, 0x0053, + 0x009b, 0xa155, + 0x0003, 0x03f0, + 0x001a, 0x0040, + 0x0017, 0xf003, + 0x00c1, 0x006e, + 0x0083, 0xc296, + 0x009f, 0xd20f, + 0x0019, 0xc103, + 0x0083, 0x0398, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xd298, + 0x0003, 0xc696, + 0x009b, 0xa755, + 0x0017, 0x5a03, + 0x0041, 0x0078, + 0x009a, 0x000a, + 0x009e, 0xd303, + 0x0083, 0x0346, + 0x009a, 0x000a, + 0x0003, 0x0347, + 0x0080, 0x0080, + 0x000f, 0xa704, + 0x0003, 0xd346, + 0x0003, 0xc047, + 0x0080, 0x0080, + 0x009b, 0xa755, + 0x0097, 0xc203, + 0x00c1, 0x0079, + 0x0000, 0x0072, + 0x009f, 0xd20f, + 0x0011, 0x0344, + 0x0083, 0x0398, + 0x009f, 0xd20f, + 0x0091, 0x0345, + 0x0083, 0x0397, + 0x009f, 0xd20f, + 0x0091, 0x0346, + 0x0003, 0x0399, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd299, + 0x0083, 0xd298, + 0x0083, 0xd297, + 0x0088, 0xde30, + 0x001a, 0x000d, + 0x009e, 0x8303, + 0x0083, 0x0383, + 0x0003, 0xcc4b, + 0x001c, 0x58c5, + 0x0003, 0x034d, + 0x009e, 0x834b, + 0x0083, 0x0383, + 0x001c, 0x4bc1, + 0x0003, 0x034b, + 0x0017, 0x4b4d, + 0x00a0, 0x00a0, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0000, 0x0096, + 0x0060, 0x0119, + 0x00a8, 0xe371, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe36e, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe36b, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe368, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x00a8, 0xe365, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe362, + 0x0091, 0x834b, + 0x0083, 0x0383, + 0x009d, 0x4bc1, + 0x0003, 0x034b, + 0x0017, 0x4bc9, + 0x00a0, 0x00bb, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0000, 0x00b1, + 0x001a, 0x001f, + 0x0091, 0x8303, + 0x0083, 0x0383, + 0x0080, 0x00d0, + 0x0060, 0x0119, + 0x0028, 0xe352, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe34f, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe34c, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe349, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe346, + 0x0083, 0x6389, + 0x0060, 0x0119, + 0x0028, 0xe343, + 0x0091, 0x40ca, + 0x0011, 0x5c03, + 0x0003, 0x038e, + 0x001e, 0x41c5, + 0x001e, 0x0348, + 0x0003, 0x0390, + 0x001f, 0xc80f, + 0x0091, 0x0351, + 0x0083, 0x0391, + 0x0083, 0x0392, + 0x009f, 0xd20f, + 0x0091, 0x0343, + 0x0083, 0x0398, + 0x009f, 0xd20f, + 0x0011, 0x0342, + 0x0083, 0x0397, + 0x009f, 0xd20f, + 0x0011, 0x0347, + 0x0003, 0x0399, + 0x0083, 0xcbf9, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xc1b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xd297, + 0x0083, 0xd298, + 0x0003, 0xd299, + 0x0083, 0x408e, + 0x0003, 0x4190, + 0x009f, 0xc50f, + 0x0099, 0x03c9, + 0x0091, 0x0351, + 0x0083, 0x0391, + 0x0083, 0x0392, + 0x0003, 0xcff9, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xc2b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd089, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0xd5b5, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xcef9, + 0x0098, 0xec00, + 0x0083, 0x03ec, + 0x009a, 0x0050, + 0x0097, 0x03ec, + 0x0041, 0x010e, + 0x0003, 0x5886, + 0x0003, 0xc0db, + 0x008b, 0x8504, + 0x0000, 0x0028, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0083, 0xc694, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x003a, 0x0041, + 0x0083, 0x03e0, + 0x001f, 0x700f, + 0x001c, 0x03c4, + 0x0011, 0x0372, + 0x0003, 0x03e4, + 0x00a8, 0xe38d, + 0x0003, 0xc2e3, + 0x0024, 0x860b, + 0x0003, 0xc07e, + 0x0080, 0x0124, + 0x00ac, 0xda02, + 0x00e1, 0x0000, + 0x003a, 0x0009, + 0x0099, 0x037e, + 0x0082, 0x0f7e, + 0x0017, 0x7ee2, + 0x0041, 0x012c, + 0x0080, 0x0124, + 0x0003, 0xc1e3, + 0x00ba, 0x1000, + 0x0011, 0x0395, + 0x0003, 0x0395, + 0x00e1, 0x0000, + 0x009b, 0xa155, + 0x0083, 0x03e9, + 0x009a, 0x0055, + 0x0097, 0xe903, + 0x0041, 0x013b, + 0x0084, 0xb90b, + 0x001f, 0xc10f, + 0x009e, 0xb903, + 0x0083, 0x03b9, + 0x0080, 0x0141, + 0x0017, 0x54e9, + 0x00c1, 0x0141, + 0x0017, 0xb957, + 0x0020, 0x0141, + 0x0098, 0xb900, + 0x0083, 0x03b9, + 0x009e, 0x55c4, + 0x0097, 0xb903, + 0x0041, 0x014c, + 0x0004, 0xff13, + 0x009f, 0xff0f, + 0x009e, 0x03c1, + 0x0003, 0x03ff, + 0x001f, 0xb90f, + 0x0019, 0x03c8, + 0x0083, 0x03b9, + 0x0000, 0x0157, + 0x0099, 0xcc55, + 0x0097, 0x03b9, + 0x0041, 0x0157, + 0x009f, 0xff0f, + 0x0097, 0x03c7, + 0x0041, 0x0157, + 0x0018, 0xff00, + 0x0003, 0x03ff, + 0x001f, 0xb90f, + 0x009e, 0x03c8, + 0x0083, 0x03b9, + 0x00e1, 0x0000, + 0x0093, 0x0000, + 0x001f, 0x8761, + 0x0003, 0x03f6, + 0x001a, 0x0160, + 0x001e, 0x03f6, + 0x0003, 0x03f6, + 0x0017, 0xd103, + 0x0041, 0x0162, + 0x0083, 0xd1fb, + 0x0000, 0x016b, + 0x001a, 0x0094, + 0x0017, 0xf603, + 0x0041, 0x0168, + 0x001a, 0x0094, + 0x0083, 0x03fb, + 0x0000, 0x016b, + 0x0083, 0xf6fb, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x00e1, 0x0000, + 0x00ae, 0x8005, + 0x000f, 0x0303, + 0x001e, 0x035f, + 0x00e1, 0x0000, + 0x0099, 0x5f03, + 0x00e1, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0003, 0x03be, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x002f, 0xbf00, + 0x00aa, 0xbf85, + 0x00e1, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, + 0x0042, 0x0000, +}}; + +static u16 cs4321_microcode_epilog[] = { + /* Addr, Data */ + 0x0201, 0x8f10, 0x0202, 0x1210, 0x0200, 0x8000, + 0x0201, 0x8f13, 0x0202, 0x1313, 0x0200, 0x8001, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8002, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8003, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8004, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8005, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8006, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8007, + 0x0201, 0x0000, 0x0202, 0x0300, 0x0200, 0x8008, + 0x0201, 0x0000, 0x0202, 0x9101, 0x0200, 0x8009, + 0x0201, 0x8000, 0x0202, 0x0e00, 0x0200, 0x800a, + 0x0201, 0x0000, 0x0202, 0xffff, 0x0200, 0x800b, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x800c, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x800d, + 0x0201, 0x0000, 0x0202, 0x0020, 0x0200, 0x800e, + 0x0201, 0x7fff, 0x0202, 0xffff, 0x0200, 0x800f, + 0x0201, 0x8000, 0x0202, 0xc350, 0x0200, 0x8010, + 0x0201, 0x0000, 0x0202, 0x8000, 0x0200, 0x8011, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8012, + 0x0201, 0x0000, 0x0202, 0x0a0a, 0x0200, 0x8013, + 0x0201, 0x0000, 0x0202, 0x0064, 0x0200, 0x8014, + 0x0201, 0x0000, 0x0202, 0x007f, 0x0200, 0x8015, + 0x0201, 0x0000, 0x0202, 0x003a, 0x0200, 0x8016, + 0x0201, 0x0000, 0x0202, 0x00ff, 0x0200, 0x8017, + 0x0201, 0x0000, 0x0202, 0x0100, 0x0200, 0x8018, + 0x0201, 0x0000, 0x0202, 0x0032, 0x0200, 0x8019, + 0x0201, 0x0000, 0x0202, 0x0018, 0x0200, 0x801a, + 0x0201, 0x0000, 0x0202, 0x0013, 0x0200, 0x801b, + 0x0201, 0x0000, 0x0202, 0xff00, 0x0200, 0x801c, + 0x0201, 0x0000, 0x0202, 0x0028, 0x0200, 0x801d, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x801e, + 0x0201, 0x0000, 0x0202, 0x0080, 0x0200, 0x801f, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8020, + 0x0201, 0x00f9, 0x0202, 0xac04, 0x0200, 0x8021, + 0x0201, 0x0a42, 0x0202, 0x6b48, 0x0200, 0x8022, + 0x0201, 0x8000, 0x0202, 0x19bc, 0x0200, 0x8023, + 0x0201, 0x8020, 0x0202, 0x6cc8, 0x0200, 0x8024, + 0x0201, 0x8000, 0x0202, 0x14c0, 0x0200, 0x8025, + 0x0201, 0x0a76, 0x0202, 0x4c88, 0x0200, 0x8026, + 0x0201, 0x015f, 0x0202, 0xcf7a, 0x0200, 0x8027, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8028, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8029, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x802a, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x802b, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x802c, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x802d, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x802e, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x802f, + 0x0201, 0x0000, 0x0202, 0x0008, 0x0200, 0x8030, + 0x0201, 0x0000, 0x0202, 0x000f, 0x0200, 0x8031, + 0x0201, 0x0000, 0x0202, 0x0008, 0x0200, 0x8032, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8033, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8034, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8035, + 0x0201, 0xffff, 0x0202, 0xfff0, 0x0200, 0x8036, + 0x0201, 0xffff, 0x0202, 0xff0f, 0x0200, 0x8037, + 0x0201, 0x0000, 0x0202, 0x0003, 0x0200, 0x8038, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x8039, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x803a, + 0x0201, 0x0000, 0x0202, 0x0003, 0x0200, 0x803b, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x803c, + 0x0201, 0x2000, 0x0202, 0x0000, 0x0200, 0x803d, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x803e, + 0x0201, 0x0000, 0x0202, 0x0000, 0x0200, 0x803f, + + 0x024f, 0x0000, + 0x0505, 0x2003, + 0x0558, 0x2001, + 0x03d4, 0x0100, + 0x03d5, 0x00c0, + 0x03d3, 0x2919, + 0x021c, 0x8020, + 0x021d, 0x8040, + 0x021e, 0x8040, + 0x03d0, 0x0600, + 0x0605, 0x1d00, + 0x0231, 0x8f05, + 0x0003, 0x0020, + 0x0004, 0x0021, + 0x0005, 0x0020, + 0x0006, 0x0100, + 0x0007, 0x0020, + 0x062a, 0x101b, + 0x062b, 0xc010, + 0x0529, 0x0808, + 0x052a, 0x0000, + 0x0504, 0x0055, + 0x0622, 0x0001, + 0x0521, 0x0001, + 0x0300, 0x0008, + 0x0308, 0x00e2, + 0x0310, 0x00d5, + 0x0318, 0x0076, + 0x0320, 0x0000, + 0x0328, 0x00f0, + 0x0338, 0x00f3, + 0x0330, 0x00f3, + 0x0340, 0x0000, + 0x0348, 0x000a, + 0x0350, 0x0000, + 0x0358, 0x00fc, + 0x0360, 0x0000, + 0x0301, 0x0008, + 0x0309, 0x00ed, + 0x0311, 0x00c6, + 0x0319, 0x004f, + 0x0321, 0x0000, + 0x0329, 0x0000, + 0x0339, 0x00fd, + 0x0331, 0x00fd, + 0x0341, 0x0006, + 0x0349, 0x0000, + 0x0351, 0x000b, + 0x0359, 0x0002, + 0x0361, 0x0000, + 0x0302, 0x0000, + 0x030a, 0x0040, + 0x0312, 0x00d0, + 0x031a, 0x006e, + 0x0322, 0x0000, + 0x032a, 0x00dc, + 0x033a, 0x00d7, + 0x0332, 0x00d7, + 0x0342, 0x00e6, + 0x034a, 0x000c, + 0x0352, 0x00fd, + 0x035a, 0x0001, + 0x0362, 0x0000, + 0x0303, 0x0000, + 0x030b, 0x00f8, + 0x0313, 0x0000, + 0x031b, 0x0064, + 0x0323, 0x0000, + 0x032b, 0x00db, + 0x0333, 0x00e6, + 0x033b, 0x00e6, + 0x0343, 0x00f0, + 0x034b, 0x0010, + 0x0353, 0x00f8, + 0x035b, 0x00f7, + 0x0363, 0x0000, + 0x0304, 0x0000, + 0x030c, 0x0000, + 0x0314, 0x0000, + 0x031c, 0x0070, + 0x0324, 0x0000, + 0x032c, 0x0000, + 0x033c, 0x0000, + 0x0334, 0x0000, + 0x0344, 0x0000, + 0x034c, 0x0000, + 0x0354, 0x0000, + 0x035c, 0x0000, + 0x0364, 0x0000, + 0x0305, 0x0000, + 0x030d, 0x00d4, + 0x0315, 0x0000, + 0x031d, 0x0077, + 0x0325, 0x0000, + 0x032d, 0x00b7, + 0x033d, 0x00f8, + 0x0335, 0x00f8, + 0x0345, 0x0003, + 0x034d, 0x00fd, + 0x0355, 0x00fa, + 0x035d, 0x00fc, + 0x0365, 0x0000, + 0x0306, 0x00f5, + 0x030e, 0x0040, + 0x0316, 0x0000, + 0x031e, 0x00ee, + 0x0326, 0x0000, + 0x032e, 0x0000, + 0x0336, 0x0000, + 0x033e, 0x0000, + 0x0346, 0x0000, + 0x034e, 0x0000, + 0x0356, 0x0000, + 0x035e, 0x0000, + 0x0366, 0x0000, + 0x0307, 0x00f9, + 0x030f, 0x0060, + 0x0317, 0x0000, + 0x031f, 0x0000, + 0x0327, 0x0000, + 0x032f, 0x0000, + 0x0337, 0x0000, + 0x033f, 0x0000, + 0x0347, 0x0000, + 0x034f, 0x0000, + 0x0357, 0x0000, + 0x035f, 0x0000, + 0x0367, 0x0000, + 0x0203, 0xfe03, + 0x03d2, 0x0000, + 0x040e, 0x0001, + 0x022f, 0x0004, + 0x040f, 0xedcf, + 0x0382, 0x0002, + 0x0408, 0xffff, + 0x022b, 0x00b0, + 0x0205, 0x0603, + 0x0227, 0x0000, + 0x0404, 0xdfff, + 0x0409, 0xf048, + 0x0296, 0x0000, + 0x029a, 0x0002, + 0x028a, 0x000f, + 0x0270, 0x0005, + 0x0400, 0xd000, + 0x020c, 0xf090, + 0x0537, 0x0136, + 0x0536, 0x0136, + 0x0510, 0x0136, + 0x050f, 0x0136, + 0x0539, 0xa002, + 0x0539, 0x2002, + 0x0512, 0xa002, + 0x0512, 0x2002, + 0x0223, 0x0006, + 0x021f, 0x0134, + 0x0700, 0x0020, + 0x0726, 0x0100, + 0x0403, 0x0020, + 0x0500, 0x1200, + 0x0274, 0x0000, + 0x024f, 0x0000, + 0x000a, 0x1412, + 0x0009, 0x2011, + 0x0008, 0x0929, + 0x0203, 0xfe03, + 0x024f, 0x0000, + 0x001c, 0x0000, + 0x001f, 0xf574, +}; diff --git a/drivers/net/phy/cs4321.c b/drivers/net/phy/cs4321.c new file mode 100644 index 0000000..31b4b19 --- /dev/null +++ b/drivers/net/phy/cs4321.c @@ -0,0 +1,1147 @@ +/* + * Based on code from Cortina Systems, Inc. + * + * Copyright (C) 2011 by Cortina Systems, Inc. + * Copyright (C) 2011 - 2012 Cavium, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include "cs4321-ucode.h" + +#define CS4321_GLOBAL_CHIP_ID_LSB 0x0 +#define CS4321_GLOBAL_CHIP_ID_MSB 0x1 +#define CS4321_GLOBAL_INGRESS_SOFT_RESET 0xC +#define CS4321_GLOBAL_EGRESS_SOFT_RESET 0xD +#define CS4321_GLOBAL_REF_SOFT_RESET 0xE +#define CS4321_GLOBAL_MPIF_SOFT_RESET 0xF +#define CS4321_GLOBAL_MPIF_RESET_DOTREG 0x10 +#define CS4321_GLOBAL_INGRESS_FUNCEN 0x12 +#define CS4321_GLOBAL_EGRESS_FUNCEN 0x13 +#define CS4321_GLOBAL_HOST_MULTILANE_FUNCEN 0x14 +#define CS4321_GLOBAL_INGRESS_CLKEN 0x15 +#define CS4321_GLOBAL_INGRESS_CLKEN2 0x16 +#define CS4321_GLOBAL_EGRESS_CLKEN 0x17 +#define CS4321_GLOBAL_EGRESS_CLKEN2 0x18 +#define CS4321_GLOBAL_HOST_MULTILANE_CLKSEL 0x19 +#define CS4321_GLOBAL_MSEQCLKCTRL 0x20 +#define CS4321_GLOBAL_GT_10KHZ_REF_CLK_CNT1 0x2D +#define CS4321_GLOBAL_GT_10KHZ_REF_CLK_CNT0 0x2E +#define CS4321_GLOBAL_MISC_CONFIG 0x33 +#define CS4321_GPIO_GPIO3 0x10C +#define CS4321_GPIO_GPIO3_DRIVE 0x10E +#define CS4321_GPIO_GPIO10 0x136 +#define CS4321_GPIO_GPIO10_OUTPUT_CFG 0x137 +#define CS4321_GPIO_GPIO_INT 0x16B +#define CS4321_GPIO_GPIO_INTE 0x16C +#define CS4321_GPIO_GPIO_INTS 0x16D +#define CS4321_MSEQ_ENABLE_MSB 0x204 +#define CS4321_MSEQ_SERDES_PARAM_LSB 0x205 +#define CS4321_MSEQ_POWER_DOWN_LSB 0x208 +#define CS4321_MSEQ_POWER_DOWN_MSB 0x209 +#define CS4321_MSEQ_STATUS 0x20a +#define CS4321_MSEQ_LEAK_INTERVAL_FFE 0x21C +#define CS4321_MSEQ_COEF_DSP_DRIVE128 0x21F +#define CS4321_MSEQ_COEF_INIT_SEL 0x223 +#define CS4321_MSEQ_CAL_RX_EQADJ 0x22A +#define CS4321_MSEQ_CAL_RX_PHSEL 0x22C +#define CS4321_MSEQ_CAL_RX_SLICER 0x22D +#define CS4321_MSEQ_CAL_RX_DFE_EQ 0x22E +#define CS4321_MSEQ_OPTIONS 0x240 +#define CS4321_MSEQ_PC 0x243 +#define CS4321_MSEQ_BANKSELECT 0x24F +#define CS4321_MSEQ_RESET_COUNT_LSB 0x250 +#define CS4321_MSEQ_SPARE2_LSB 0x270 +#define CS4321_MSEQ_SPARE9_LSB 0x27E +#define CS4321_MSEQ_SPARE11_LSB 0x282 +#define CS4321_MSEQ_SPARE15_LSB 0x28A +#define CS4321_MSEQ_SPARE21_LSB 0x296 +#define CS4321_MSEQ_SPARE23_LSB 0x29A +#define CS4321_DSP_SDS_DSP_COEF_DFE0_SELECT 0x37B +#define CS4321_DSP_SDS_DSP_COEF_LARGE_LEAK 0x382 +#define CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x400 +#define CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_MSB 0x401 +#define CS4321_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT0_MSB 0x403 +#define CS4321_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x405 +#define CS4321_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x409 +#define CS4321_DSP_SDS_SERDES_SRX_FFE_INBUF_CTRL 0x40A +#define CS4321_DSP_SDS_SERDES_SRX_FFE_PGA_CTRL 0x40B +#define CS4321_DSP_SDS_SERDES_SRX_FFE_MISC 0x40C +#define CS4321_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x40E +#define CS4321_DSP_SDS_SERDES_SRX_DFE_MISC 0x412 +#define CS4321_DSP_SDS_SERDES_SRX_AGC_MISC 0x413 +#define CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG 0x500 +#define CS4321_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL 0x501 +#define CS4321_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x503 +#define CS4321_LINE_SDS_COMMON_SRX0_RX_CPA 0x504 +#define CS4321_LINE_SDS_COMMON_SRX0_RX_CPB 0x505 +#define CS4321_LINE_SDS_COMMON_SRX0_RX_VCO_CTRL 0x507 +#define CS4321_LINE_SDS_COMMON_SRX0_RX_SPARE 0x50C +#define CS4321_LINE_SDS_COMMON_RXVCO0_CONTROL 0x512 +#define CS4321_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x529 +#define CS4321_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x52A +#define CS4321_LINE_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING 0x52B +#define CS4321_LINE_SDS_COMMON_STXP0_TX_CONFIG 0x52C +#define CS4321_LINE_SDS_COMMON_STXP0_TX_PWRDN 0x52D +#define CS4321_LINE_SDS_COMMON_STXP0_TX_CLKOUT_CTRL 0x52F +#define CS4321_LINE_SDS_COMMON_STXP0_TX_LOOP_FILTER 0x530 +#define CS4321_LINE_SDS_COMMON_TXVCO0_CONTROL 0x539 +#define CS4321_HOST_SDS_COMMON_SRX0_RX_CONFIG 0x600 +#define CS4321_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL 0x601 +#define CS4321_HOST_SDS_COMMON_SRX0_RX_CLKOUT_CTRL 0x602 +#define CS4321_HOST_SDS_COMMON_RXVCO0_CONTROL 0x613 +#define CS4321_HOST_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING 0x62C +#define CS4321_HOST_SDS_COMMON_STXP0_TX_CONFIG 0x62D +#define CS4321_HOST_SDS_COMMON_STXP0_TX_PWRDN 0x62E +#define CS4321_HOST_SDS_COMMON_STXP0_TX_CLKDIV_CTRL 0x62F +#define CS4321_HOST_SDS_COMMON_STXP0_TX_CLKOUT_CTRL 0x630 +#define CS4321_HOST_SDS_COMMON_TXVCO0_CONTROL 0x63A +#define CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CONFIG 0x700 +#define CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CLKDIV_CTRL 0x701 +#define CS4321_HOST_ML_SDS_COMMON_RXVCO0_CONTROL 0x70F +#define CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CONFIG 0x725 +#define CS4321_HOST_ML_SDS_COMMON_STXP0_TX_PWRDN 0x726 +#define CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CLKDIV_CTRL 0x727 +#define CS4321_HOST_ML_SDS_COMMON_TXVCO0_CONTROL 0x731 +#define CS4321_XGPCS_LINE_TX_TXCNTRL 0xA00 +#define CS4321_XGPCS_LINE_RX_RXCNTRL 0xA20 +#define CS4321_XGPCS_HOST_TX_TXCNTRL 0xA80 +#define CS4321_XGPCS_HOST_RX_RXCNTRL 0xAA0 +#define CS4321_GIGEPCS_LINE_CONTROL 0xC00 +#define CS4321_GIGEPCS_HOST_CONTROL 0xC80 +#define CS4321_HIF_COMMON_TXCONTROL3 0xD0B +#define CS4321_XGRS_LINE_TX_TXCNTRL 0xE00 +#define CS4321_XGRS_LINE_RX_RXCNTRL1 0xE10 +#define CS4321_XGRS_HOST_TX_TXCNTRL 0xE80 +#define CS4321_XGRS_HOST_RX_RXCNTRL1 0xE90 +#define CS4321_XGMAC_LINE_RX_CFG_COM 0xF00 +#define CS4321_XGMAC_LINE_TX_CFG_COM 0xF40 +#define CS4321_XGMAC_LINE_TX_CFG_TX 0xF41 +#define CS4321_XGMAC_LINE_TX_CFG_TX_IFG 0xF43 +#define CS4321_XGMAC_HOST_RX_CFG_COM 0xF80 +#define CS4321_XGMAC_HOST_TX_CFG_COM 0xFC0 +#define CS4321_XGMAC_HOST_TX_CFG_TX 0xFC1 +#define CS4321_XGMAC_HOST_TX_CFG_TX_IFG 0xFC3 +#define CS4321_MAC_LAT_CTRL_RESET 0x3000 +#define CS4321_MAC_LAT_CTRL_CONFIG 0x3001 +#define CS4321_RADJ_INGRESS_RX_NRA_MIN_IFG 0x3204 +#define CS4321_RADJ_INGRESS_RX_NRA_SETTLE 0x3206 +#define CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA1 0x3210 +#define CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA0 0x3211 +#define CS4321_RADJ_INGRESS_TX_ADD_FILL_CTRL 0x3212 +#define CS4321_RADJ_INGRESS_TX_PRA_MIN_IFG 0x3214 +#define CS4321_RADJ_INGRESS_TX_PRA_SETTLE 0x3216 +#define CS4321_RADJ_INGRESS_MISC_RESET 0x3220 +#define CS4321_RADJ_EGRESS_RX_NRA_MIN_IFG 0x3284 +#define CS4321_RADJ_EGRESS_RX_NRA_SETTLE 0x3286 +#define CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA1 0x3290 +#define CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA0 0x3291 +#define CS4321_RADJ_EGRESS_TX_ADD_FILL_CTRL 0x3292 +#define CS4321_RADJ_EGRESS_TX_PRA_MIN_IFG 0x3294 +#define CS4321_RADJ_EGRESS_TX_PRA_SETTLE 0x3296 +#define CS4321_RADJ_EGRESS_MISC_RESET 0x32A0 +#define CS4321_PM_CTRL 0x3400 +#define CS4321_EEPROM_LOADER_CONTROL 0x3F00 +#define CS4321_EEPROM_LOADER_STATUS 0x3F01 + + +enum cs4321_host_mode { + RXAUI, + XAUI +}; + +struct cs4321_private { + enum cs4321_host_mode mode; +}; + +struct cs4321_reg_modify { + u16 reg; + u16 mask_bits; + u16 set_bits; +}; + +struct cs4321_multi_seq { + int reg_offset; + const struct cs4321_reg_modify *seq; +}; + +static const struct cs4321_reg_modify cs4321_soft_reset_registers[] = { + /* Enable all the clocks */ + {CS4321_GLOBAL_INGRESS_CLKEN, 0, 0xffff}, + {CS4321_GLOBAL_INGRESS_CLKEN2, 0, 0xffff}, + {CS4321_GLOBAL_EGRESS_CLKEN, 0, 0xffff}, + {CS4321_GLOBAL_EGRESS_CLKEN2, 0, 0xffff}, + /* Reset MPIF registers */ + {CS4321_GLOBAL_MPIF_RESET_DOTREG, 0, 0x0}, + /* Re-assert the reset */ + {CS4321_GLOBAL_MPIF_RESET_DOTREG, 0, 0xffff}, + + /* Disable all the clocks */ + {CS4321_GLOBAL_INGRESS_CLKEN, 0, 0x0}, + {CS4321_GLOBAL_INGRESS_CLKEN2, 0, 0x0}, + {CS4321_GLOBAL_EGRESS_CLKEN, 0, 0x0}, + {CS4321_GLOBAL_EGRESS_CLKEN2, 0, 0x0}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_68xx_4_nic_init[] = { + /* Configure chip for common reference clock */ + {CS4321_LINE_SDS_COMMON_STXP0_TX_CONFIG, 0, 0x2700}, + /* Set GPIO3 to drive low to enable laser output*/ + {CS4321_GPIO_GPIO3_DRIVE, 0, 0}, + {CS4321_GPIO_GPIO3, 0, 0x11}, + /* Set GPIO10 as GPIO_INT open-drain active low */ + {CS4321_GPIO_GPIO_INTE, 0, 0}, + {CS4321_GPIO_GPIO10_OUTPUT_CFG, 0, 6}, + {CS4321_GPIO_GPIO10, 0, 0x0719}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_prefix_seq[] = { + /* MPIF DeAssert System Reset */ + {CS4321_GLOBAL_MPIF_RESET_DOTREG, ~0x0001, 0}, + /* + * Make sure to stall the microsequencer before configuring + * the path. + */ + {CS4321_GLOBAL_MSEQCLKCTRL, 0, 0x8004}, + {CS4321_MSEQ_OPTIONS, 0, 0xf}, + {CS4321_MSEQ_PC, 0, 0x0}, + /* + * Correct some of the h/w defaults that are incorrect. + * + * The default value of the bias current is incorrect and needs to + * be corrected. This is normally done by Microcode but it doesn't + * always run. + */ + {CS4321_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT0_MSB, 0, 0x20}, + /* + * By default need to power on the voltage monitor since it is required + * by the temperature monitor and this is used by the microcode. + */ + {CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x0}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_ingress_local_timing_rxaui[] = { + {CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x0000}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CPA, 0, 0x0057}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0, 0x0007}, + {CS4321_LINE_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING, 0, 0x0001}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_CLKOUT_CTRL, 0, 0x0864}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_LOOP_FILTER, 0, 0x0027}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_PWRDN, 0, 0x0000}, + {CS4321_GLOBAL_INGRESS_SOFT_RESET, ~0x1, 0x0001}, + {CS4321_GLOBAL_INGRESS_SOFT_RESET, ~0x1, 0x0000}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_egress_local_timing_rxaui[] = { + {CS4321_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL, 0, 0x40d1}, + {CS4321_HOST_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x000c}, + {CS4321_HOST_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING, 0, 0x0001}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_CLKDIV_CTRL, 0, 0x4091}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_CLKOUT_CTRL, 0, 0x1864}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_CONFIG, 0, 0x090c}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_PWRDN, 0, 0x0000}, + {CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CLKDIV_CTRL, 0, 0x401d}, + {CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x000c}, + {CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CLKDIV_CTRL, 0, 0x4019}, + {CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CONFIG, 0, 0x090c}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, ~0x1, 0x0001}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, ~0x1, 0x0000}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, ~0x2, 0x0001}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, ~0x2, 0x0000}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_line_power_down[] = { + {CS4321_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0, 0x0000}, + {CS4321_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0, 0x0000}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x2040}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_VCO_CTRL, 0, 0x01e7}, + {CS4321_MSEQ_POWER_DOWN_LSB, 0, 0x0000}, + {CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_MSB, 0, 0xffff}, + {CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0, 0xffff}, + {CS4321_DSP_SDS_SERDES_SRX_AGC_MISC, 0, 0x0705}, + {CS4321_DSP_SDS_SERDES_SRX_DFE_MISC, 0, 0x002b}, + {CS4321_DSP_SDS_SERDES_SRX_FFE_PGA_CTRL, 0, 0x0021}, + {CS4321_DSP_SDS_SERDES_SRX_FFE_MISC, 0, 0x0013}, + {CS4321_DSP_SDS_SERDES_SRX_FFE_INBUF_CTRL, 0, 0x0001}, + {CS4321_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0, 0x0001}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_ingress_rxaui_pcs_ra[] = { + /* Set fen_radj, rx_fen_xgpcs*/ + {CS4321_GLOBAL_INGRESS_FUNCEN, ~0x0081, 0x0081}, + /* Set rx_en_radj, rx_en_xgpcs*/ + {CS4321_GLOBAL_INGRESS_CLKEN, ~0x0021, 0x0021}, + /* Set tx_en_hif, tx_en_radj*/ + {CS4321_GLOBAL_INGRESS_CLKEN2, ~0x0120, 0x0120}, + + {CS4321_GLOBAL_HOST_MULTILANE_CLKSEL, 0, 0x8000}, + {CS4321_GLOBAL_HOST_MULTILANE_FUNCEN, 0, 0x0006}, + + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0xffff}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0x0000}, + /* MPIF DeAssert Ingress Reset */ + {CS4321_GLOBAL_MPIF_RESET_DOTREG, ~0x0004, 0}, + + {CS4321_XGMAC_LINE_RX_CFG_COM, 0, 0x8010}, + {CS4321_XGPCS_LINE_RX_RXCNTRL, 0, 0x5000}, + + {CS4321_RADJ_INGRESS_RX_NRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_INGRESS_RX_NRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_INGRESS_TX_ADD_FILL_CTRL, 0, 0xf001}, + {CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA0, 0, 0x0707}, + {CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA1, 0, 0x0707}, + {CS4321_RADJ_INGRESS_TX_PRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_INGRESS_TX_PRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_INGRESS_MISC_RESET, 0, 0x0000}, + + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0002}, + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_RADJ_INGRESS_MISC_RESET, 0, 0x0000}, + + {CS4321_PM_CTRL, 0, 0x0000}, + {CS4321_HIF_COMMON_TXCONTROL3, 0, 0x0010}, + + {CS4321_MSEQ_POWER_DOWN_LSB, 0, 0xe01f}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_egress_rxaui_pcs_ra[] = { + /* Set tx_fen_xgpcs, fen_radj */ + {CS4321_GLOBAL_EGRESS_FUNCEN, ~0x0180, 0x0180}, + /* Set rx_en_hif, rx_en_radj*/ + {CS4321_GLOBAL_EGRESS_CLKEN, ~0x0120, 0x0120}, + /* Set tx_en_radj, tx_en_xgpcs*/ + {CS4321_GLOBAL_EGRESS_CLKEN2, ~0x0021, 0x0021}, + + {CS4321_GLOBAL_HOST_MULTILANE_CLKSEL, 0, 0x8000}, + {CS4321_GLOBAL_HOST_MULTILANE_FUNCEN, 0, 0x0006}, + + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0xffff}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0x0000}, + /* MPIF DeAssert Egress Reset */ + {CS4321_GLOBAL_MPIF_RESET_DOTREG, ~0x0002, 0}, + + {CS4321_XGMAC_LINE_TX_CFG_COM, 0, 0xc000}, + {CS4321_XGMAC_LINE_TX_CFG_TX_IFG, 0, 0x0005}, + {CS4321_XGPCS_LINE_TX_TXCNTRL, 0, 0x0000}, + {CS4321_XGRS_LINE_TX_TXCNTRL, 0, 0xc000}, + + {CS4321_RADJ_EGRESS_RX_NRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_EGRESS_RX_NRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_EGRESS_TX_ADD_FILL_CTRL, 0, 0xf001}, + {CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA0, 0, 0x0707}, + {CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA1, 0, 0x0707}, + {CS4321_RADJ_EGRESS_TX_PRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_EGRESS_TX_PRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_EGRESS_MISC_RESET, 0, 0x0000}, + + {CS4321_PM_CTRL, 0, 0x0000}, + {CS4321_HIF_COMMON_TXCONTROL3, 0, 0x0010}, + {CS4321_MSEQ_POWER_DOWN_LSB, 0, 0xe01f}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_global_timer_156_25[] = { + {CS4321_GLOBAL_GT_10KHZ_REF_CLK_CNT0, 0, 15625}, + {CS4321_GLOBAL_GT_10KHZ_REF_CLK_CNT1, 0, 0}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_mac_latency[] = { + {CS4321_MAC_LAT_CTRL_CONFIG, 0, 0}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_ref_clk_src_xaui_rxaui[] = { + /* Set edc_stxp_lptime_sel = 1, edc_stxp_pilot_sel = 7 */ + {CS4321_GLOBAL_MISC_CONFIG, (u16)~0xe700, 0x2700}, + /* Set STXP_PILOT_SEL = 7, STXP_LPTIME_SEL = 1 */ + {CS4321_LINE_SDS_COMMON_STXP0_TX_CONFIG, (u16)~0xe700, 0x2700}, + {0} +}; + + +static const struct cs4321_reg_modify cs4321_init_polarity_inv[] = { + /* Inversion disabled*/ + /* config the slice not to invert polarity on egress */ + {CS4321_HOST_SDS_COMMON_SRX0_RX_CONFIG, ~0x0800, 0}, + /* config the slice not to invert polarity on ingress */ + {CS4321_MSEQ_ENABLE_MSB, ~0x4000, 0}, + {0} +}; + +#if 0 +static const struct cs4321_reg_modify cs4321_hsif_elec_mode_set_cx1_pre[] = { + /* Stop the micro-sequencer */ + {CS4321_GLOBAL_MSEQCLKCTRL, 0, 0x8004}, + {CS4321_MSEQ_OPTIONS, 0, 0xf}, + {CS4321_MSEQ_PC, 0, 0x0}, + + {CS4321_MSEQ_COEF_DSP_DRIVE128, 0, 0x0114}, + {CS4321_MSEQ_COEF_INIT_SEL, 0, 0x0004}, + {CS4321_MSEQ_LEAK_INTERVAL_FFE, 0, 0x8010}, + {CS4321_MSEQ_BANKSELECT, 0, 0x2}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CPA, 0, 0x55}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0, 0x3}, + {CS4321_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0, 0x1}, + {CS4321_DSP_SDS_DSP_COEF_DFE0_SELECT, 0, 0x2}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CPB, 0, 0x2003}, + {CS4321_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0, 0xF047}, + {CS4321_MSEQ_RESET_COUNT_LSB, 0, 0x0}, + /* enable power savings, ignore optical module LOS */ + {CS4321_MSEQ_SPARE2_LSB, 0, 0x5}, + + {CS4321_MSEQ_SPARE9_LSB, 0, 0x5}, + + {CS4321_MSEQ_CAL_RX_PHSEL, 0, 0x23}, + {CS4321_DSP_SDS_DSP_COEF_LARGE_LEAK, 0, 0x2}, + {CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0, 0x5000}, + {CS4321_MSEQ_POWER_DOWN_LSB, 0, 0xFFFF}, + {CS4321_MSEQ_POWER_DOWN_MSB, 0, 0x0}, + {CS4321_MSEQ_CAL_RX_SLICER, 0, 0x80}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_SPARE, 0, 0xE0E0}, + {CS4321_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0, 0xff}, + + {CS4321_MSEQ_SERDES_PARAM_LSB, 0, 0x0603}, + {CS4321_MSEQ_SPARE11_LSB, 0, 0x0603}, + + + {0} +}; + +static const struct cs4321_reg_modify cs4321_hsif_elec_mode_set_cx1_2in[] = { + {CS4321_MSEQ_SPARE15_LSB, 0, 0x0603}, + {CS4321_MSEQ_SPARE21_LSB, 0, 0xE}, + {CS4321_MSEQ_SPARE23_LSB, 0, 0x0}, + {CS4321_MSEQ_CAL_RX_DFE_EQ, 0, 0x3}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_hsif_elec_mode_set_cx1_post[] = { + /* Restart the micro-sequencer */ + {CS4321_GLOBAL_MSEQCLKCTRL, 0, 0x4}, + {CS4321_MSEQ_OPTIONS, 0, 0x7}, + {0} +}; +#endif + +static const struct cs4321_reg_modify cs4321_hsif_elec_mode_set_sr_pre[] = { + /* Stop the micro-sequencer */ + {CS4321_GLOBAL_MSEQCLKCTRL, 0, 0x8004}, + {CS4321_MSEQ_OPTIONS, 0, 0xf}, + {CS4321_MSEQ_PC, 0, 0x0}, + + /* Configure the micro-sequencer for an SR transceiver */ + {CS4321_MSEQ_COEF_DSP_DRIVE128, 0, 0x0134}, + {CS4321_MSEQ_COEF_INIT_SEL, 0, 0x0006}, + {CS4321_MSEQ_LEAK_INTERVAL_FFE, 0, 0x8010}, + {CS4321_MSEQ_BANKSELECT, 0, 0x0}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CPA, 0, 0x55}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0, 0x3}, + {CS4321_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0, 0x1}, + {CS4321_DSP_SDS_DSP_COEF_DFE0_SELECT, 0, 0x2}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CPB, 0, 0x2003}, + {CS4321_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0, 0xF048}, + + {CS4321_MSEQ_RESET_COUNT_LSB, 0, 0x0}, + /* enable power savings, ignore */ + {CS4321_MSEQ_SPARE2_LSB, 0, 0x5}, + + {CS4321_MSEQ_SPARE9_LSB, 0, 0x5}, + + {CS4321_MSEQ_CAL_RX_PHSEL, 0, 0x1e}, + {CS4321_DSP_SDS_DSP_COEF_LARGE_LEAK, 0, 0x2}, + {CS4321_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0, 0xD000}, + {CS4321_MSEQ_POWER_DOWN_LSB, 0, 0xFFFF}, + {CS4321_MSEQ_POWER_DOWN_MSB, 0, 0x0}, + {CS4321_MSEQ_CAL_RX_SLICER, 0, 0x80}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_SPARE, 0, 0xE0E0}, + {CS4321_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0, 0xff}, + + /* Setup the trace lengths for the micro-sequencer */ + {CS4321_MSEQ_SERDES_PARAM_LSB, 0, 0x0603}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_hsif_elec_mode_set_sr_2in[] = { + {CS4321_MSEQ_CAL_RX_EQADJ, 0, 0x0}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_hsif_elec_mode_set_sr_post[] = { + {CS4321_MSEQ_CAL_RX_DFE_EQ, 0, 0x0}, + /* Restart the micro-sequencer */ + {CS4321_GLOBAL_MSEQCLKCTRL, 0, 0x4}, + {CS4321_MSEQ_OPTIONS, 0, 0x7}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_resync_vcos_xaui_rxaui[] = { + {CS4321_HOST_SDS_COMMON_RXVCO0_CONTROL, (u16)~0x8000, 0x8000}, + {CS4321_HOST_SDS_COMMON_RXVCO0_CONTROL, (u16)~0x8000, 0}, + + {CS4321_HOST_SDS_COMMON_TXVCO0_CONTROL, (u16)~0x8000, 0x8000}, + {CS4321_HOST_SDS_COMMON_TXVCO0_CONTROL, (u16)~0x8000, 0}, + + {CS4321_LINE_SDS_COMMON_RXVCO0_CONTROL, (u16)~0x8000, 0x8000}, + {CS4321_LINE_SDS_COMMON_RXVCO0_CONTROL, (u16)~0x8000, 0}, + + {CS4321_LINE_SDS_COMMON_TXVCO0_CONTROL, (u16)~0x8000, 0x8000}, + {CS4321_LINE_SDS_COMMON_TXVCO0_CONTROL, (u16)~0x8000, 0}, + + {CS4321_HOST_ML_SDS_COMMON_RXVCO0_CONTROL, (u16)~0x8000, 0x8000}, + {CS4321_HOST_ML_SDS_COMMON_RXVCO0_CONTROL, (u16)~0x8000, 0}, + + {CS4321_HOST_ML_SDS_COMMON_TXVCO0_CONTROL, (u16)~0x8000, 0x8000}, + {CS4321_HOST_ML_SDS_COMMON_TXVCO0_CONTROL, (u16)~0x8000, 0}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_toggle_resets_xaui_rxaui[] = { + {CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CONFIG, ~0x0020, 0}, + {CS4321_HOST_ML_SDS_COMMON_STXP0_TX_PWRDN, ~0x0100, 0}, + + /* + * Now that the device is configured toggle the ingress and + * egress soft resets to make sure the device re-syncs + * properly. + */ + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x3}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0x3}, + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0x0000}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_xaui_egress[] = { + {CS4321_LINE_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING, 0, 0x0001}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_CLKOUT_CTRL, 0, 0x0864}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_LOOP_FILTER, 0, 0x0027}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_PWRDN, 0, 0x0000}, + + {CS4321_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL, 0, 0x45d2}, + {CS4321_HOST_SDS_COMMON_SRX0_RX_CLKOUT_CTRL, 0, 0x6a03}, + {CS4321_HOST_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x000c}, + {CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CLKDIV_CTRL, 0, 0x412d}, + {CS4321_HOST_ML_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x000c}, + + {CS4321_LINE_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING, 0, 0x0001}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_CLKOUT_CTRL, 0, 0x0864}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_LOOP_FILTER, 0, 0x0027}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_PWRDN, 0, 0x0000}, + + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0003}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0xffff}, + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0xffff}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0x0000}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_xaui_ingress[] = { + {CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x0000}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CPA, 0, 0x0057}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0, 0x0007}, + + {CS4321_HOST_SDS_COMMON_STX0_TX_CONFIG_LOCAL_TIMING, 0, 0x0001}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_CLKDIV_CTRL, 0, 0x4492}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_CLKOUT_CTRL, 0, 0x1864}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_CONFIG, 0, 0x090c}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_PWRDN, 0, 0x0000}, + {CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CLKDIV_CTRL, 0, 0x4429}, + {CS4321_HOST_ML_SDS_COMMON_STXP0_TX_CONFIG, 0, 0x090c}, + + {CS4321_LINE_SDS_COMMON_SRX0_RX_CONFIG, 0, 0x0000}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_CPA, 0, 0x0057}, + {CS4321_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0, 0x0007}, + + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0003}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0xffff}, + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0xffff}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0x0000}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_ingress_1[] = { + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0002}, + {CS4321_GLOBAL_INGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_HOST_SDS_COMMON_STXP0_TX_PWRDN, 0, 0x0000}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_2e[] = { + {CS4321_GLOBAL_HOST_MULTILANE_CLKSEL, 0, 0x8000}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_2o[] = { + {CS4321_GLOBAL_HOST_MULTILANE_CLKSEL, 0, 0x8300}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_ingress_3[] = { + /* Set the device in XAUI mode */ + {CS4321_GLOBAL_HOST_MULTILANE_FUNCEN, 0, 0x0005}, + + /* Enable the XGPCS and the Rate Adjust block */ + /* Set fen_radj, rx_fen_xgpcs */ + {CS4321_GLOBAL_INGRESS_FUNCEN, ~0x0081, 0x0081}, + + /* Setup the clock enables for the XGPCS and Rate Adjust block */ + /* Set rx_en_radj, rx_en_xgpcs */ + {CS4321_GLOBAL_INGRESS_CLKEN, ~0x0021, 0x0021}, + + /* Setup the clock enables for the HIF and the Rate Adjust block */ + /* Set tx_en_hif, tx_en_radj */ + {CS4321_GLOBAL_INGRESS_CLKEN2, ~0x0120, 0x0120}, + + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0xffff}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0, 0x0000}, + /* MPIF DeAssert Ingress Reset */ + {CS4321_GLOBAL_MPIF_RESET_DOTREG, ~0x0004, 0}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_ingress_4e[] = { + {CS4321_XGMAC_LINE_RX_CFG_COM, 0, 0x8010}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_ingress_4o[] = { + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_ingress_5[] = { + {CS4321_XGMAC_HOST_TX_CFG_TX_IFG, 0, 0x0005}, + {CS4321_XGPCS_LINE_RX_RXCNTRL, 0, 0x5000}, + {CS4321_XGRS_HOST_TX_TXCNTRL, 0, 0xc000}, + {CS4321_GIGEPCS_LINE_CONTROL, 0, 0x0000}, + {CS4321_GIGEPCS_HOST_CONTROL, 0, 0x0000}, + + {CS4321_RADJ_INGRESS_RX_NRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_INGRESS_RX_NRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_INGRESS_TX_ADD_FILL_CTRL, 0, 0xf001}, + {CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA0, 0, 0x0707}, + {CS4321_RADJ_INGRESS_TX_ADD_FILL_DATA1, 0, 0x0707}, + {CS4321_RADJ_INGRESS_TX_PRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_INGRESS_TX_PRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_INGRESS_MISC_RESET, 0, 0x0000}, + {CS4321_PM_CTRL, 0, 0x0002}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_6e[] = { + {CS4321_HIF_COMMON_TXCONTROL3, 0, 0x0010}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_6o[] = { + {CS4321_HIF_COMMON_TXCONTROL3, 0, 0x0011}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_egress_1[] = { + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0x1}, + {CS4321_GLOBAL_EGRESS_SOFT_RESET, 0, 0x0000}, + {CS4321_LINE_SDS_COMMON_STXP0_TX_PWRDN, 0, 0x0000}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_egress_3[] = { + /* Set the device in XAUI mode */ + {CS4321_GLOBAL_HOST_MULTILANE_FUNCEN, 0x0005}, + + /* Enable the XGPCS and the Rate Adjust block */ + /* Set tx_fen_xgpcs, fen_radj */ + {CS4321_GLOBAL_EGRESS_FUNCEN, ~0x0180, 0x0180}, + + /* Setup the clock enables for the HIF and the Rate Adjust block */ + /* Set rx_en_hif, rx_en_radj */ + {CS4321_GLOBAL_EGRESS_CLKEN, ~0x0120, 0x0120}, + + /* Setup the clock enables for the XGPCS and Rate Adjust block */ + /* Set tx_en_radj, tx_en_xgpcs */ + {CS4321_GLOBAL_EGRESS_CLKEN2, ~0x0021, 0x0021}, + + {CS4321_GLOBAL_REF_SOFT_RESET, 0xffff}, + {CS4321_GLOBAL_REF_SOFT_RESET, 0x0000}, + + /* MPIF DeAssert Egress Reset */ + {CS4321_GLOBAL_MPIF_RESET_DOTREG, ~0x0002, 0}, + + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_egress_4e[] = { + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_egress_4o[] = { + {CS4321_XGMAC_LINE_TX_CFG_COM, 0, 0xc000}, + {0} +}; + +static const struct cs4321_reg_modify cs4321_init_dpath_xaui_pcs_ra_egress_5[] = { + {CS4321_XGMAC_LINE_TX_CFG_TX_IFG, 0, 0x0005}, + {CS4321_XGPCS_LINE_TX_TXCNTRL, 0, 0x0000}, + {CS4321_XGRS_LINE_TX_TXCNTRL, 0, 0xc000}, + + {CS4321_RADJ_EGRESS_RX_NRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_EGRESS_RX_NRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_EGRESS_TX_ADD_FILL_CTRL, 0, 0xf001}, + {CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA0, 0, 0x0707}, + {CS4321_RADJ_EGRESS_TX_ADD_FILL_DATA1, 0, 0x0707}, + {CS4321_RADJ_EGRESS_TX_PRA_MIN_IFG, 0, 0x0004}, + {CS4321_RADJ_EGRESS_TX_PRA_SETTLE, 0, 0x0000}, + {CS4321_RADJ_EGRESS_MISC_RESET, 0, 0x0000}, + {CS4321_PM_CTRL, 0, 0x0002}, + {0} +}; + +const struct cs4321_multi_seq cs4321_init_rxaui_seq[] = { + {0, cs4321_init_prefix_seq}, + {0, cs4321_init_egress_local_timing_rxaui}, + {0, cs4321_init_ingress_local_timing_rxaui}, + {0, cs4321_init_dpath_ingress_rxaui_pcs_ra}, + {0, cs4321_init_dpath_egress_rxaui_pcs_ra}, + {0, cs4321_resync_vcos_xaui_rxaui}, + {0, cs4321_toggle_resets_xaui_rxaui}, + {0, cs4321_hsif_elec_mode_set_sr_pre}, + {0, cs4321_hsif_elec_mode_set_sr_2in}, + {0, cs4321_hsif_elec_mode_set_sr_post}, + {0, cs4321_init_global_timer_156_25}, + {0, cs4321_init_mac_latency}, + {0, cs4321_init_ref_clk_src_xaui_rxaui}, + {0, cs4321_init_polarity_inv}, + + {0, NULL} +}; + +const struct cs4321_multi_seq cs4321_init_xaui_seq[] = { + {0, cs4321_init_prefix_seq}, + /* Init egress even and odd */ + {0, cs4321_init_xaui_egress}, + {1, cs4321_init_xaui_egress}, + + /* Init ingress even and odd */ + {0, cs4321_init_xaui_ingress}, + {1, cs4321_init_xaui_ingress}, + + /* dpath ingress even and odd */ + {0, cs4321_init_dpath_xaui_pcs_ra_ingress_1}, + {0, cs4321_init_dpath_xaui_pcs_ra_2e}, + {0, cs4321_init_dpath_xaui_pcs_ra_ingress_3}, + {0, cs4321_init_dpath_xaui_pcs_ra_ingress_4e}, + {0, cs4321_init_dpath_xaui_pcs_ra_ingress_5}, + {0, cs4321_init_dpath_xaui_pcs_ra_6e}, + + + {1, cs4321_init_dpath_xaui_pcs_ra_ingress_1}, + {1, cs4321_init_dpath_xaui_pcs_ra_2o}, + {1, cs4321_init_dpath_xaui_pcs_ra_ingress_3}, + {1, cs4321_init_dpath_xaui_pcs_ra_ingress_4o}, + {1, cs4321_init_dpath_xaui_pcs_ra_ingress_5}, + {1, cs4321_init_dpath_xaui_pcs_ra_6o}, + + /* dpath egress even and odd */ + {0, cs4321_init_dpath_xaui_pcs_ra_egress_1}, + {0, cs4321_init_dpath_xaui_pcs_ra_2e}, + {0, cs4321_init_dpath_xaui_pcs_ra_egress_3}, + {0, cs4321_init_dpath_xaui_pcs_ra_egress_4e}, + {0, cs4321_init_dpath_xaui_pcs_ra_egress_5}, + {0, cs4321_init_dpath_xaui_pcs_ra_6e}, + + {1, cs4321_init_dpath_xaui_pcs_ra_egress_1}, + {1, cs4321_init_dpath_xaui_pcs_ra_2o}, + {1, cs4321_init_dpath_xaui_pcs_ra_egress_3}, + {1, cs4321_init_dpath_xaui_pcs_ra_egress_4o}, + {1, cs4321_init_dpath_xaui_pcs_ra_egress_5}, + {1, cs4321_init_dpath_xaui_pcs_ra_6o}, + + /* power down the odd slice's line side */ + {1, cs4321_init_line_power_down}, + + {0, cs4321_resync_vcos_xaui_rxaui}, + {0, cs4321_toggle_resets_xaui_rxaui}, + {0, cs4321_hsif_elec_mode_set_sr_pre}, + {0, cs4321_hsif_elec_mode_set_sr_2in}, + {0, cs4321_hsif_elec_mode_set_sr_post}, + {0, cs4321_init_global_timer_156_25}, + {0, cs4321_init_mac_latency}, + {0, cs4321_init_ref_clk_src_xaui_rxaui}, + {0, cs4321_init_polarity_inv}, + + {0, NULL} +}; + +static int cs4321_phy_read_x(struct phy_device *phydev, int off, u16 regnum) +{ + return mdiobus_read(phydev->bus, phydev->addr + off, + MII_ADDR_C45 | regnum); +} + +static int cs4321_phy_write_x(struct phy_device *phydev, int off, + u16 regnum, u16 val) +{ + return mdiobus_write(phydev->bus, phydev->addr + off, + MII_ADDR_C45 | regnum, val); +} +static int cs4321_phy_read(struct phy_device *phydev, u16 regnum) +{ + return cs4321_phy_read_x(phydev, 0, regnum); +} + +static int cs4321_phy_write(struct phy_device *phydev, u16 regnum, u16 val) +{ + return cs4321_phy_write_x(phydev, 0, regnum, val); +} + +static int cs4321_write_seq_x(struct phy_device *phydev, int off, + const struct cs4321_reg_modify *seq) +{ + int last_reg = -1; + int last_val = 0; + int ret = 0; + + while (seq->reg) { + if (seq->mask_bits) { + if (last_reg != seq->reg) { + ret = cs4321_phy_read_x(phydev, off, seq->reg); + if (ret < 0) + goto err; + last_val = ret; + } + last_val &= seq->mask_bits; + } else { + last_val = 0; + } + last_val |= seq->set_bits; + ret = cs4321_phy_write_x(phydev, off, seq->reg, last_val); + if (ret < 0) + goto err; + seq++; + } +err: + return ret; +} + +static int cs4321_write_multi_seq(struct phy_device *phydev, + const struct cs4321_multi_seq *m) +{ + int ret = 0; + + while (m->seq) { + ret = cs4321_write_seq_x(phydev, m->reg_offset, m->seq); + if (ret) + goto err; + m++; + } + +err: + return ret; +} + +static int cs4321_write_seq(struct phy_device *phydev, + const struct cs4321_reg_modify *seq) +{ + return cs4321_write_seq_x(phydev, 0, seq); +} + +static int cs4321_write_multi_reg(struct phy_device *phydev, u16 *dat, int cnt) +{ + int i; + int ret = 0; + for (i = 0; i < (cnt * 2); i += 2) { + u16 reg = dat[i]; + u16 val = dat[i + 1]; + ret = cs4321_phy_write(phydev, reg, val); + if (ret) + break; + } + return ret; +} + +static int cs4321_write_microcode_slice(struct phy_device *phydev, int s) +{ + int i; + int ret; + + ret = cs4321_phy_write(phydev, 0x024f, s); + if (ret) + return ret; + + for (i = 0; i < 512; i++) { + ret = cs4321_phy_write(phydev, + 0x0201, + cs4321_microcode_slices[s][2 * i + 0]); + if (ret) + return ret; + + ret = cs4321_phy_write(phydev, + 0x0202, + cs4321_microcode_slices[s][2 * i + 1]); + if (ret) + return ret; + ret = cs4321_phy_write(phydev, 0x0200, 0x9000 + i); + if (ret) + return ret; + } + return 0; +} + +static int cs4321_write_microcode(struct phy_device *phydev) +{ + int i; + int ret; + + ret = cs4321_write_multi_reg(phydev, + cs4321_microcode_prolog, + ARRAY_SIZE(cs4321_microcode_prolog) / 2); + if (ret) + return ret; + + for (i = 0; i < 8; i++) { + ret = cs4321_write_microcode_slice(phydev, i); + if (ret) + return ret; + } + ret = cs4321_write_multi_reg(phydev, + cs4321_microcode_epilog, + ARRAY_SIZE(cs4321_microcode_epilog) / 2); + return ret; +} + +static int cs4321_reset(struct phy_device *phydev) +{ + int ret; + int retry; + + ret = cs4321_phy_write(phydev, CS4321_GLOBAL_MPIF_SOFT_RESET, 0xdead); + if (ret) + goto err; + + msleep(100); + + /* Disable eeprom loading */ + ret = cs4321_phy_write(phydev, CS4321_EEPROM_LOADER_CONTROL, 2); + if (ret) + goto err; + + retry = 0; + do { + if (retry > 0) + mdelay(1); + ret = cs4321_phy_read(phydev, CS4321_EEPROM_LOADER_STATUS); + if (ret < 0) + goto err; + retry++; + } while ((ret & 4) == 0 && retry < 10); + + if ((ret & 4) == 0) { + ret = -ENXIO; + goto err; + } + + ret = cs4321_write_seq(phydev, cs4321_soft_reset_registers); + if (ret) + goto err; + + ret = cs4321_write_microcode(phydev); + if (ret) + goto err; + + + ret = cs4321_write_seq(phydev, cs4321_68xx_4_nic_init); + if (ret) + goto err; + +err: + return ret; +} + +int cs4321_init_rxaui(struct phy_device *phydev) +{ + return cs4321_write_multi_seq(phydev, + cs4321_init_rxaui_seq); +} + +int cs4321_init_xaui(struct phy_device *phydev) +{ + return cs4321_write_multi_seq(phydev, + cs4321_init_xaui_seq); + +} + +int cs4321_config_init(struct phy_device *phydev) +{ + int ret; + struct cs4321_private *p = phydev->priv; + const struct cs4321_multi_seq *init_seq; + + ret = cs4321_reset(phydev); + if (ret) + goto err; + + init_seq = (p->mode == XAUI) ? + cs4321_init_xaui_seq : cs4321_init_rxaui_seq; + + ret = cs4321_write_multi_seq(phydev, init_seq); + + phydev->state = PHY_NOLINK; + +err: + return ret; +} + +int cs4321_probe(struct phy_device *phydev) +{ + int ret = 0; + int id_lsb, id_msb; + enum cs4321_host_mode host_mode; + const char *prop_val; + struct cs4321_private *p; + /* + * CS4312 keeps its ID values in non-standard registers, make + * sure we are talking to what we think we are. + */ + id_lsb = cs4321_phy_read(phydev, CS4321_GLOBAL_CHIP_ID_LSB); + if (id_lsb < 0) { + ret = id_lsb; + goto err; + } + + id_msb = cs4321_phy_read(phydev, CS4321_GLOBAL_CHIP_ID_MSB); + if (id_msb < 0) { + ret = id_msb; + goto err; + } + + if (id_lsb != 0x23E5 || id_msb != 0x1002) { + ret = -ENODEV; + goto err; + } + ret = of_property_read_string(phydev->dev.of_node, + "cortina,host-mode", &prop_val); + if (ret) + goto err; + + if (strcmp(prop_val, "rxaui") == 0) + host_mode = RXAUI; + else if (strcmp(prop_val, "xaui") == 0) + host_mode = XAUI; + else { + dev_err(&phydev->dev, + "Invalid \"cortina,host-mode\" property: \"%s\"\n", + prop_val); + ret = -EINVAL; + goto err; + } + p = devm_kzalloc(&phydev->dev, sizeof(*p), GFP_KERNEL); + if (!p) { + ret = -ENOMEM; + goto err; + } + p->mode = host_mode; + phydev->priv = p; +err: + return ret; +} + +int cs4321_config_aneg(struct phy_device *phydev) +{ + return -EINVAL; +} + +int cs4321_read_status(struct phy_device *phydev) +{ + int gpio_int_status; + int ret = 0; + + gpio_int_status = cs4321_phy_read(phydev, CS4321_GPIO_GPIO_INTS); + if (gpio_int_status < 0) { + ret = gpio_int_status; + goto err; + } + if (gpio_int_status & 0x8) { + /* Up when edc_convergedS set. */ + phydev->speed = 10000; + phydev->duplex = 1; + phydev->link = 1; + } else { + phydev->link = 0; + } + +err: + return ret; +} + +static struct of_device_id cs4321_match[] = { + { + .compatible = "cortina,cs4321", + }, + { + .compatible = "cortina,cs4318", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, cs4321_match); + +static struct phy_driver cs4321_phy_driver = { + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Cortina CS4321", + .config_init = cs4321_config_init, + .probe = cs4321_probe, + .config_aneg = cs4321_config_aneg, + .read_status = cs4321_read_status, + .driver = { + .owner = THIS_MODULE, + .of_match_table = cs4321_match, + }, +}; + +static int __init cs4321_drv_init(void) +{ + int ret; + + ret = phy_driver_register(&cs4321_phy_driver); + + return ret; +} +module_init(cs4321_drv_init); + +static void __exit cs4321_drv_exit(void) +{ + phy_driver_unregister(&cs4321_phy_driver); +} +module_exit(cs4321_drv_exit); -- 1.7.2.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/