Date: Wed, 13 Jun 2012 14:34:51 -0700
From: Andi Kleen <ak@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <andi@firstfloor.org>, x86@kernel.org,
        linux-kernel@vger.kernel.org, eranian@google.com
Subject: Re: [PATCH 3/4] perf, x86: check ucode before disabling PEBS on
 SandyBridge v3
Message-ID: <20120613213451.GC32604@tassilo.jf.intel.com>
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 <1339623054.8980.64.camel@twins>
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> Stephane actually wrote:
> 
> "Ok, so to close on this, I tried the 6/6/2012 ucode update on a few
> SNB-EP systems.
> 
> I got two answers depending on the stepping:
> C1 (stepping 6) -> 0x618
> C2 (stepping 7) -> 0x70c
> 
> So we need to check x86_mask for stepping and adjust the value of
> snb_ucode_rev accordingly for model 45."

not sure i understood your point? 
What do you want me to change?

I check different numbers on the different models.

FWIW it works on a Sandy Bridge E and I believe I didn't change
the logic for non E, which Stephane tested.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only
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