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From: James Cleverdon <jamesclv@us.ibm.com>
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Organization: IBM xSeries Linux Solutions
To: Xuehua Chen <namniardniw@yahoo.com>, linux-kernel@vger.kernel.org
Subject: Re: A question about cache coherence
Date: Mon, 19 Aug 2002 14:40:23 -0700
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On Monday 19 August 2002 11:21 am, Xuehua Chen wrote:
> Met a problem in my research. I run some code on a
> Xeon
> dual-processor machine. It seems to me that there is a
>  cache coherence problem. As I am not so familiar
> to this topic, I would like to ask some experts about
> the following questions.
>
> 1. Do Xeon processors have hardware mechanisms to
> maintain cache coherence?

Someone at Intel can correct me, but I believe they use a modified MESI cache 
coherency protocol.  Note that this coherency does not guarantee indivisible 
read-modify-write operations unless atomic opcodes are used.  (xchg or lock 
<opcode>)

> 2. Does the SMP kernel handle the cache coherence
> problem

See Alan's and others' postings.  The kernel relies on the hardware to keep 
its act straight, then takes care of MMU coherency.

> 3. What should I do if both of them don't handle cache
> coherence.

See 1 and 2.  Consider using futexes or some other mutex mechanism appropriate 
to user or kernel code.

> Thanks.
>
> Frank Samuel

-- 
James Cleverdon
IBM xSeries Linux Solutions
{jamesclv(Unix, preferred), cleverdj(Notes)} at us dot ibm dot com

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