Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754102Ab2HCQis (ORCPT ); Fri, 3 Aug 2012 12:38:48 -0400 Received: from osrc3.amd.com ([217.9.48.20]:47866 "EHLO mail.x86-64.org" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1753913Ab2HCQiD (ORCPT ); Fri, 3 Aug 2012 12:38:03 -0400 From: Borislav Petkov To: "H. Peter Anvin" Cc: Alex Shi , X86-ML , LKML , Borislav Petkov Subject: [PATCH 0/4] x86, CPU: TLB flushall shift, the AMD side Date: Fri, 3 Aug 2012 18:37:45 +0200 Message-Id: <1344011869-21868-1-git-send-email-bp@amd64.org> X-Mailer: git-send-email 1.7.11.rc1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 517 Lines: 16 From: Borislav Petkov Hi all, now that the Intel TLB subset flushing patches are in mainline, here's the AMD side of the deal. Those have been tested on all our families with the mprotect microbenchmark. Any comments are appreciated. Thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/