Date: Thu, 16 Aug 2012 15:29:18 +0100
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: leroy christophe <christophe.leroy@c-s.fr>
Cc: Alan Cox <alan@linux.intel.com>, Vitaly Bordug <vitb@kernel.crashing.org>,
        Marcelo Tosatti <marcelo@kvack.org>, linux-kernel@vger.kernel.org,
        linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] Powerpc 8xx CPM_UART delay in receive
Message-ID: <20120816152918.5ed2649f@pyramind.ukuu.org.uk>
In-Reply-To: <502CF2A0.8080109@c-s.fr>
References: <201208141426.q7EEQSPc003956@localhost.localdomain>
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	<502CF2A0.8080109@c-s.fr>
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> The PowerPC CPM is working differently. It doesn't use a fifo but 
> buffers. Buffers are handed to the microprocessor only when they are 
> full or after a timeout period which is adjustable. In the driver, the 

Which is different how - remembering we empty the FIFO on an IRQ

> buffers are configured with a size of 32 bytes. And the timeout is set 
> to the size of the buffer. That is this timeout that I'm reducing to 1 
> byte in my proposed patch. I can't see what it would break for high 
> speed I/O.

How can a timeout be measured in "bytes". Can we have a bit more clarity
on how the hardware works and take it from there ?

Alan
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