Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753345Ab2JRHq6 (ORCPT ); Thu, 18 Oct 2012 03:46:58 -0400 Received: from va3ehsobe003.messaging.microsoft.com ([216.32.180.13]:29340 "EHLO va3outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752443Ab2JRHqm convert rfc822-to-8bit (ORCPT ); Thu, 18 Oct 2012 03:46:42 -0400 X-Forefront-Antispam-Report: CIP:70.37.183.190;KIP:(null);UIP:(null);IPV:NLI;H:mail.freescale.net;RD:none;EFVD:NLI X-SpamScore: 2 X-BigFish: VS2(zzc89bh1432Id799hzz1202h1d1ah1d2ah1082kzzz2dh2a8h668h839h93fhd25he5bhf0ah107ah1288h12a5h12a9h12bdh1354h137ah13b6h1441h1155h) Message-ID: <507FB495.7050104@freescale.com> Date: Thu, 18 Oct 2012 15:49:41 +0800 From: Huang Shijie User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.24) Gecko/20111108 Fedora/3.1.16-1.fc14 Thunderbird/3.1.16 MIME-Version: 1.0 To: Marek Vasut CC: Vinod Koul , , , , , , , , , , , , , , , , , , , , Huang Shijie , Fabio Estevam Subject: Re: [PATCH] dma: add new DMA control commands References: <1350538335-29026-1-git-send-email-b32955@freescale.com> <1350541111.5263.3.camel@vkoul-udesk3> <507FA595.4020507@freescale.com> <201210180914.58527.marex@denx.de> In-Reply-To: <201210180914.58527.marex@denx.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8BIT X-OriginatorOrg: freescale.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2320 Lines: 64 于 2012年10月18日 15:14, Marek Vasut 写道: > Dear Huang Shijie, > > Why such massive CC ? > >> 于 2012年10月18日 14:18, Vinod Koul 写道: >>> Why cant you do start (prepare clock etc) when you submit the descriptor >>> to dmaengine. Can be done in tx_submit callback. >>> Similarly remove the clock when dma transaction gets completed. >> I ever thought this method too. >> >> But it will become low efficient in the following case: >> >> Assuming the gpmi-nand driver has to read out 1024 pages in one >> _SINGLE_ read operation. >> The gpmi-nand will submit the descriptor to dmaengine per page. > It will? Then GPMI NAND is flat our broken ... again. yes. Please read the NAND chip spec about the comand READ PAGE(00h-30h) and the code nand_do_read_ops(). The nand chip limits us only read one page out one time. So the driver will submit the descriptor to dmaengine per page. >> So with >> your method, >> the system will repeat the enable/disable dma clock 1024 time. > Yes, it is the driver that's wrong. not the driver. >> At every >> enable/disable dma clock, >> the system has to enable the clock chain and it's parents ... >> >> But with this patch, we only need to enable/disable dma clock one time, >> just at we select the nand chip. > You are fixing a driver problem at a framework level, wrong. > > So, check how the MXS SPI driver handles descriptor chaining. Indeed, the > Sigmatel screwed the DMA stuff good. But if you analyze the SPI driver, you'll > notice a few important points that might come handy when you fix the GPMI NAND > driver properly. > > The direction to take here is: > 1) Implement DMA chaining into the GPMI NAND driver How can i implement the DMA chain if the nand chip READ-PAGE command gives us the one page limit? thanks Huang Shijie > 2) You might need to do one PIO transfer to reconfigure the IP registers between > each segment of the DMA chain (just as MXS SPI does it) > 3) You might run out of DMA descriptors when doing too long chains -- so you > might need to fix that part of the mxs DMA driver. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/