Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756013Ab2JZDYx (ORCPT ); Thu, 25 Oct 2012 23:24:53 -0400 Received: from fgwmail6.fujitsu.co.jp ([192.51.44.36]:37187 "EHLO fgwmail6.fujitsu.co.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755973Ab2JZDYs (ORCPT ); Thu, 25 Oct 2012 23:24:48 -0400 X-SecurityPolicyCheck: OK by SHieldMailChecker v1.7.4 Date: Fri, 26 Oct 2012 12:24:06 +0900 (JST) Message-Id: <20121026.122406.13396329.d.hatayama@jp.fujitsu.com> To: hpa@zytor.com, ebiederm@xmission.com Cc: len.brown@intel.com, fenghua.yu@intel.com, x86@kernel.org, kexec@lists.infradead.org, linux-kernel@vger.kernel.org, rob.herring@calxeda.com, grant.likely@secretlab.ca, tglx@linutronix.de, mingo@elte.hu, vgoyal@redhat.com Subject: Re: [PATCH v1 2/2] x86, apic: Disable BSP if boot cpu is AP From: HATAYAMA Daisuke In-Reply-To: <5085E663.6040307@zytor.com> References: <5085B0D0.9020508@zytor.com> <87mwze8abu.fsf@xmission.com> <5085E663.6040307@zytor.com> X-Mailer: Mew version 6.3 on Emacs 23.4 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Multipart/Mixed; boundary="--Next_Part(Fri_Oct_26_12_24_06_2012_043)--" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 15261 Lines: 241 ----Next_Part(Fri_Oct_26_12_24_06_2012_043)-- Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit From: "H. Peter Anvin" Subject: Re: [PATCH v1 2/2] x86, apic: Disable BSP if boot cpu is AP Date: Mon, 22 Oct 2012 17:35:47 -0700 > On 10/22/2012 02:29 PM, Eric W. Biederman wrote: >>> >>> As I said, I thought Fenghua tried that but it didn't work, >>> experimentally. >> >> Fair enough. You described the problem with clearing bit 8 in a weird >> way. >> >> If the best we can muster are fuzzy memories it may be worth >> revisiting. >> Perhaps it works on enough cpu models to be interesting. >> > > It isn't fuzzy memories... this was done as late as 1-2 months ago. I > just don't know the details. > > Fenghua, could you help fill us in? > I overlooked completely the fact that BSP flag is rewritable. I tried Eric's suggestion using attached test programs and saw it worked fine at least on the three cpus around me below: - Intel(R) Xeon(R) CPU E7- 4820 @ 2.00GHz - Intel(R) Xeon(R) CPU E7- 8870 @ 2.40GHz - Intel(R) Xeon(TM) CPU 1.80GHz - 32 bits CPU Next I found the description about this in 8.4.2, IASDM Vol.3: The MP initialization protocol imposes the following requirements and restrictions on the system: * The MP protocol is executed only after a power-up or RESET. If the MP protocol has completed and a BSP is chosen, subsequent INITs (either to a specific processor or system wide) do not cause the MP protocol to be repeated. Instead, each logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) to determine whether it should execute the BIOS boot-strap code (if it is the BSP) or enter a wait-for-SIPI state (if it is an AP). So this is no longer undocumented behaviour for recent cpus, I think. Considering these, I'll make a patch to clear BSP flag at appropreate position in kernel boot-up code. OTOH, according to the discussion, it was reported that clearing BSP flag affected some BIOSes. To deal with this, I'll prepare a kernel option to decide whether to clear BSP flag or not. Does anyone have any comments now? Or please comment after I submit a new patch. Thanks. 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