Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758812Ab2JZN0K (ORCPT ); Fri, 26 Oct 2012 09:26:10 -0400 Received: from mail-ee0-f46.google.com ([74.125.83.46]:36530 "EHLO mail-ee0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756396Ab2JZN0I (ORCPT ); Fri, 26 Oct 2012 09:26:08 -0400 Date: Fri, 26 Oct 2012 15:26:01 +0200 From: Ingo Molnar To: Rik van Riel Cc: Andi Kleen , Michel Lespinasse , Linus Torvalds , Peter Zijlstra , Andrea Arcangeli , Mel Gorman , Johannes Weiner , Thomas Gleixner , Andrew Morton , linux-kernel@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCH 05/31] x86/mm: Reduce tlb flushes from ptep_set_access_flags() Message-ID: <20121026132601.GC9886@gmail.com> References: <20121025121617.617683848@chello.nl> <20121025124832.840241082@chello.nl> <5089F5B5.1050206@redhat.com> <508A0A0D.4090001@redhat.com> <508A8D31.9000106@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <508A8D31.9000106@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2354 Lines: 60 * Rik van Riel wrote: > On 10/26/2012 08:48 AM, Andi Kleen wrote: > >Michel Lespinasse writes: > > > >>On Thu, Oct 25, 2012 at 9:23 PM, Linus Torvalds > >> wrote: > >>>On Thu, Oct 25, 2012 at 8:57 PM, Rik van Riel wrote: > >>>> > >>>>That may not even be needed. Apparently Intel chips > >>>>automatically flush an entry from the TLB when it > >>>>causes a page fault. I assume AMD chips do the same, > >>>>because flush_tlb_fix_spurious_fault evaluates to > >>>>nothing on x86. > >>> > >>>Yes. It's not architected as far as I know, though. But I agree, it's > >>>possible - even likely - we could avoid TLB flushing entirely on x86. > >> > >>Actually, it is architected on x86. This was first described in the > >>intel appnote 317080 "TLBs, Paging-Structure Caches, and Their > >>Invalidation", last paragraph of section 5.1. Nowadays, the same > >>contents are buried somewhere in Volume 3 of the architecture manual > >>(in my copy: 4.10.4.1 Operations that Invalidate TLBs and > >>Paging-Structure Caches) > > > > This unfortunately would only work for processes with no > > threads because it only works on the current logical CPU. > > That is fine. > > Potentially triggering a spurious page fault on > another CPU is bound to be better than always > doing a synchronous remote TLB flush, waiting > for who knows how many CPUs to acknowledge the > IPI... The other killer is the fundamental IPI delay - which makes it 'invisible' to regular profiling and makes it hard to analyze. So yes, even the local flush is a win, a major one - and the flush-less one is likely a win too, because INVLPG has some TLB-cache-walking costs. Rik, mind sending an updated patch that addresses Linus's concerns, or should I code it up if you are busy? We can also certainly try the second patch, but I'd do it at the end of the series, to put some tree distance between the two patches, to not concentrate regression risks too tightly in the Git space, to help out with hard to bisect problems... Thanks, Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/