Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422840Ab2JaNWV (ORCPT ); Wed, 31 Oct 2012 09:22:21 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:34590 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1422806Ab2JaNWU (ORCPT ); Wed, 31 Oct 2012 09:22:20 -0400 Message-ID: <509125FC.1090609@ti.com> Date: Wed, 31 Oct 2012 09:22:04 -0400 From: Murali Karicheri User-Agent: Mozilla/5.0 (X11; Linux i686; rv:16.0) Gecko/20121026 Thunderbird/16.0.2 MIME-Version: 1.0 To: Linus Walleij CC: , , , , , , , , , , , , , Subject: Re: [PATCH v3 04/11] clk: davinci - add pll divider clock driver References: <1351181518-11882-1-git-send-email-m-karicheri2@ti.com> <1351181518-11882-5-git-send-email-m-karicheri2@ti.com> In-Reply-To: Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 949 Lines: 26 On 10/28/2012 03:26 PM, Linus Walleij wrote: > On Thu, Oct 25, 2012 at 6:11 PM, Murali Karicheri wrote: > >> pll dividers are present in the pll controller of DaVinci and Other >> SoCs that re-uses the same hardware IP. This has a enable bit for >> bypass the divider or enable the driver. This is a sub class of the >> clk-divider clock checks the enable bit to calculare the rate and >> invoke the recalculate() function of the clk-divider if enabled. >> >> Signed-off-by: Murali Karicheri > Looking good, > Acked-by: Linus Walleij > > Yours, > Linus Walleij > Linus, Thanks. I will add your Acked-by in the next version. Murali -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/