Resend clock patches from v4 based on v5.0-rc1.
The whole series now is composed of
a fix for PLL tuner (PATCH 1),
clock common changes for both MT8183 & MT6765 (PATCH 2-3),
clock support of MT8183 (PATCH 4-8) and
resend a clock patch long time ago(PTACH 9).
changes since v4:
- refine for the fix of PLL tuner(PATCH 1).
- add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7).
changes sinve v3:
- add fix tag.
- small change of mtk_clk_mux data structure.
- use of_property_for_each_string to iterate dependent subsys clock of power domain.
- document critical clocks.
- reduce some clock register error log.
- few coding style fix.
changes sinve v2:
- refine for implementation consistency of mtk clk mux.
- separate the onoff API into enable/disable API for mtk scpsys.
- resend a patch about PLL rate changing.
changes since v1:
- refine for better code quality.
- some minor bug fix of clock part, like incorrect control address
and missing clocks.
In previous MediaTek PLL design, it assumes the pcw change control
is always on the CON1 register.
However, the pcw change bit on MT8183 was moved onto CON0 because
the the PCW length of audio PLLs are extended to 32-bit.
Add configurable pcw_chg_reg to set the pcw change control register
address or using the default control register CON1 if without
setting in pll data.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/clk-mtk.h | 1 +
drivers/clk/mediatek/clk-pll.c | 17 +++++++++++------
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 928905496c4b..37ae944548e9 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -221,6 +221,7 @@ struct mtk_pll_data {
int pcwibits;
uint32_t pcw_reg;
int pcw_shift;
+ uint32_t pcw_chg_reg;
const struct mtk_pll_div_table *div_table;
const char *parent_name;
};
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 67aaa3082d9b..65cee1d6c400 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -27,7 +27,7 @@
#define CON0_BASE_EN BIT(0)
#define CON0_PWR_ON BIT(0)
#define CON0_ISO_EN BIT(1)
-#define CON0_PCW_CHG BIT(31)
+#define PCW_CHG_MASK BIT(31)
#define AUDPLL_TUNER_EN BIT(31)
@@ -51,6 +51,7 @@ struct mtk_clk_pll {
void __iomem *tuner_addr;
void __iomem *tuner_en_addr;
void __iomem *pcw_addr;
+ void __iomem *pcw_chg_addr;
const struct mtk_pll_data *data;
};
@@ -122,7 +123,7 @@ static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
int postdiv)
{
- u32 con1, val;
+ u32 chg, val;
int pll_en;
pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
@@ -147,14 +148,14 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
val |= pcw << pll->data->pcw_shift;
writel(val, pll->pcw_addr);
- con1 = readl(pll->base_addr + REG_CON1);
+ chg = readl(pll->pcw_chg_addr);
if (pll_en)
- con1 |= CON0_PCW_CHG;
+ chg |= PCW_CHG_MASK;
- writel(con1, pll->base_addr + REG_CON1);
+ writel(chg, pll->pcw_chg_addr);
if (pll->tuner_addr)
- writel(con1 + 1, pll->tuner_addr);
+ writel(val + 1, pll->tuner_addr);
/* restore tuner_en */
__mtk_pll_tuner_enable(pll);
@@ -329,6 +330,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
pll->pwr_addr = base + data->pwr_reg;
pll->pd_addr = base + data->pd_reg;
pll->pcw_addr = base + data->pcw_reg;
+ if (data->pcw_chg_reg)
+ pll->pcw_chg_addr = base + data->pcw_chg_reg;
+ else
+ pll->pcw_chg_addr = pll->base_addr + REG_CON1;
if (data->tuner_reg)
pll->tuner_addr = base + data->tuner_reg;
if (data->tuner_en_reg)
--
2.18.0
From: Owen Chen <[email protected]>
On both MT8183 & MT6765, there add "set/clr" register for
each clkmux setting, and one update register to trigger value change.
It is designed to prevent read-modify-write racing issue.
The sw design need to add a new API to handle this hw change with
a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
Signed-off-by: Owen Chen <[email protected]>
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mux.c | 223 +++++++++++++++++++++++++++++++++
drivers/clk/mediatek/clk-mux.h | 89 +++++++++++++
3 files changed, 314 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mediatek/clk-mux.c
create mode 100644 drivers/clk/mediatek/clk-mux.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index ee4410ff43ab..20cf9eea4171 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
+
obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
new file mode 100644
index 000000000000..877a883fa616
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mux.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <[email protected]>
+ */
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+
+static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
+{
+ return container_of(hw, struct mtk_clk_mux, hw);
+}
+
+static int mtk_clk_mux_enable(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = BIT(mux->data->gate_shift);
+
+ return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
+ mask, ~mask);
+}
+
+static void mtk_clk_mux_disable(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = BIT(mux->data->gate_shift);
+
+ regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
+}
+
+static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+
+ return regmap_write(mux->regmap, mux->data->clr_ofs,
+ BIT(mux->data->gate_shift));
+}
+
+static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+
+ regmap_write(mux->regmap, mux->data->set_ofs,
+ BIT(mux->data->gate_shift));
+}
+
+static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 val;
+
+ regmap_read(mux->regmap, mux->data->mux_ofs, &val);
+
+ return (val & BIT(mux->data->gate_shift)) == 0;
+}
+
+static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = GENMASK(mux->data->mux_width - 1, 0);
+ u32 val;
+
+ regmap_read(mux->regmap, mux->data->mux_ofs, &val);
+ val = (val >> mux->data->mux_shift) & mask;
+
+ return val;
+}
+
+static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = GENMASK(mux->data->mux_width - 1, 0);
+ unsigned long flags;
+
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+
+ regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
+ index << mux->data->mux_shift);
+
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+
+ return 0;
+}
+
+static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
+{
+ struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
+ u32 mask = GENMASK(mux->data->mux_width - 1, 0);
+ u32 val, orig;
+ unsigned long flags;
+
+ if (mux->lock)
+ spin_lock_irqsave(mux->lock, flags);
+ else
+ __acquire(mux->lock);
+
+ regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
+ val = (orig & ~(mask << mux->data->mux_shift))
+ | (index << mux->data->mux_shift);
+
+ if (val != orig) {
+ regmap_write(mux->regmap, mux->data->clr_ofs,
+ mask << mux->data->mux_shift);
+ regmap_write(mux->regmap, mux->data->set_ofs,
+ index << mux->data->mux_shift);
+
+ if (mux->data->upd_shift >= 0)
+ regmap_write(mux->regmap, mux->data->upd_ofs,
+ BIT(mux->data->upd_shift));
+ }
+
+ if (mux->lock)
+ spin_unlock_irqrestore(mux->lock, flags);
+ else
+ __release(mux->lock);
+
+ return 0;
+}
+
+const struct clk_ops mtk_mux_ops = {
+ .get_parent = mtk_clk_mux_get_parent,
+ .set_parent = mtk_clk_mux_set_parent_lock,
+};
+
+const struct clk_ops mtk_mux_clr_set_upd_ops = {
+ .get_parent = mtk_clk_mux_get_parent,
+ .set_parent = mtk_clk_mux_set_parent_setclr_lock,
+};
+
+const struct clk_ops mtk_mux_gate_ops = {
+ .enable = mtk_clk_mux_enable,
+ .disable = mtk_clk_mux_disable,
+ .is_enabled = mtk_clk_mux_is_enabled,
+ .get_parent = mtk_clk_mux_get_parent,
+ .set_parent = mtk_clk_mux_set_parent_lock,
+};
+
+const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
+ .enable = mtk_clk_mux_enable_setclr,
+ .disable = mtk_clk_mux_disable_setclr,
+ .is_enabled = mtk_clk_mux_is_enabled,
+ .get_parent = mtk_clk_mux_get_parent,
+ .set_parent = mtk_clk_mux_set_parent_setclr_lock,
+};
+
+struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
+ struct regmap *regmap,
+ spinlock_t *lock)
+{
+ struct mtk_clk_mux *clk_mux;
+ struct clk_init_data init;
+ struct clk *clk;
+
+ clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
+ if (!clk_mux)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = mux->name;
+ init.flags = mux->flags | CLK_SET_RATE_PARENT;
+ init.parent_names = mux->parent_names;
+ init.num_parents = mux->num_parents;
+ init.ops = mux->ops;
+
+ clk_mux->regmap = regmap;
+ clk_mux->data = mux;
+ clk_mux->lock = lock;
+ clk_mux->hw.init = &init;
+
+ clk = clk_register(NULL, &clk_mux->hw);
+ if (IS_ERR(clk)) {
+ kfree(clk_mux);
+ return clk;
+ }
+
+ return clk;
+}
+
+int mtk_clk_register_muxes(const struct mtk_mux *muxes,
+ int num, struct device_node *node,
+ spinlock_t *lock,
+ struct clk_onecell_data *clk_data)
+{
+ struct regmap *regmap;
+ struct clk *clk;
+ int i;
+
+ regmap = syscon_node_to_regmap(node);
+ if (IS_ERR(regmap)) {
+ pr_err("Cannot find regmap for %pOF: %ld\n", node,
+ PTR_ERR(regmap));
+ return PTR_ERR(regmap);
+ }
+
+ for (i = 0; i < num; i++) {
+ const struct mtk_mux *mux = &muxes[i];
+
+ if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
+ clk = mtk_clk_register_mux(mux, regmap, lock);
+
+ if (IS_ERR(clk)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ mux->name, PTR_ERR(clk));
+ continue;
+ }
+
+ clk_data->clks[mux->id] = clk;
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
new file mode 100644
index 000000000000..f5625f4d9e6c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mux.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <[email protected]>
+ */
+
+#ifndef __DRV_CLK_MTK_MUX_H
+#define __DRV_CLK_MTK_MUX_H
+
+#include <linux/clk-provider.h>
+
+struct mtk_clk_mux {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ const struct mtk_mux *data;
+ spinlock_t *lock;
+};
+
+struct mtk_mux {
+ int id;
+ const char *name;
+ const char * const *parent_names;
+ unsigned int flags;
+
+ u32 mux_ofs;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 upd_ofs;
+
+ u8 mux_shift;
+ u8 mux_width;
+ u8 gate_shift;
+ s8 upd_shift;
+
+ const struct clk_ops *ops;
+
+ signed char num_parents;
+};
+
+extern const struct clk_ops mtk_mux_ops;
+extern const struct clk_ops mtk_mux_clr_set_upd_ops;
+extern const struct clk_ops mtk_mux_gate_ops;
+extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
+
+#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd, _flags, _ops) { \
+ .id = _id, \
+ .name = _name, \
+ .mux_ofs = _mux_ofs, \
+ .set_ofs = _mux_set_ofs, \
+ .clr_ofs = _mux_clr_ofs, \
+ .upd_ofs = _upd_ofs, \
+ .mux_shift = _shift, \
+ .mux_width = _width, \
+ .gate_shift = _gate, \
+ .upd_shift = _upd, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = _flags, \
+ .ops = &_ops, \
+ }
+
+#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd, _flags) \
+ GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd, _flags, \
+ mtk_mux_gate_clr_set_upd_ops)
+
+#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
+ _gate, _upd_ofs, _upd) \
+ MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
+ _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
+ _width, _gate, _upd_ofs, _upd, \
+ CLK_SET_RATE_PARENT)
+
+struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
+ struct regmap *regmap,
+ spinlock_t *lock);
+
+int mtk_clk_register_muxes(const struct mtk_mux *muxes,
+ int num, struct device_node *node,
+ spinlock_t *lock,
+ struct clk_onecell_data *clk_data);
+
+#endif /* __DRV_CLK_MTK_MUX_H */
--
2.18.0
From: Owen Chen <[email protected]>
PLLs with tuner_en bit, such as APLL1, need to disable
tuner_en before apply new frequency settings, or the new frequency
settings (pcw) will not be applied.
The tuner_en bit will be disabled during changing PLL rate
and be restored after new settings applied.
Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
Cc: <[email protected]>
Signed-off-by: Owen Chen <[email protected]>
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++----------
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index f54e4015b0b1..18842d660317 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
return ((unsigned long)vco + postdiv - 1) / postdiv;
}
+static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
+{
+ u32 r;
+
+ if (pll->tuner_en_addr) {
+ r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
+ writel(r, pll->tuner_en_addr);
+ } else if (pll->tuner_addr) {
+ r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
+ writel(r, pll->tuner_addr);
+ }
+}
+
+static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
+{
+ u32 r;
+
+ if (pll->tuner_en_addr) {
+ r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
+ writel(r, pll->tuner_en_addr);
+ } else if (pll->tuner_addr) {
+ r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
+ writel(r, pll->tuner_addr);
+ }
+}
+
static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
int postdiv)
{
@@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
+ /* disable tuner */
+ __mtk_pll_tuner_disable(pll);
+
/* set postdiv */
val = readl(pll->pd_addr);
val &= ~(POSTDIV_MASK << pll->data->pd_shift);
@@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
if (pll->tuner_addr)
writel(con1 + 1, pll->tuner_addr);
+ /* restore tuner_en */
+ __mtk_pll_tuner_enable(pll);
+
if (pll_en)
udelay(20);
}
@@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
r |= pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
- if (pll->tuner_en_addr) {
- r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
- writel(r, pll->tuner_en_addr);
- } else if (pll->tuner_addr) {
- r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
- writel(r, pll->tuner_addr);
- }
+ __mtk_pll_tuner_enable(pll);
udelay(20);
@@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
writel(r, pll->base_addr + REG_CON0);
}
- if (pll->tuner_en_addr) {
- r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
- writel(r, pll->tuner_en_addr);
- } else if (pll->tuner_addr) {
- r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
- writel(r, pll->tuner_addr);
- }
+ __mtk_pll_tuner_disable(pll);
r = readl(pll->base_addr + REG_CON0);
r &= ~CON0_BASE_EN;
--
2.18.0
Resend clock patches from v4 based on v5.0-rc1.
The whole series now is composed of
a fix for PLL tuner (PATCH 1),
clock common changes for both MT8183 & MT6765 (PATCH 2-3),
clock support of MT8183 (PATCH 4-8) and
resend a clock patch long time ago(PTACH 9).
changes since v4:
- refine for the fix of PLL tuner(PATCH 1).
- add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7).
changes sinve v3:
- add fix tag.
- small change of mtk_clk_mux data structure.
- use of_property_for_each_string to iterate dependent subsys clock of power domain.
- document critical clocks.
- reduce some clock register error log.
- few coding style fix.
changes sinve v2:
- refine for implementation consistency of mtk clk mux.
- separate the onoff API into enable/disable API for mtk scpsys.
- resend a patch about PLL rate changing.
changes since v1:
- refine for better code quality.
- some minor bug fix of clock part, like incorrect control address
and missing clocks.
James Liao (1):
clk: mediatek: Allow changing PLL rate when it is off
Owen Chen (3):
clk: mediatek: Disable tuner_en before change PLL rate
clk: mediatek: Add new clkmux register API
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
Weiyi Lu (5):
dt-bindings: ARM: Mediatek: Document bindings for MT8183
clk: mediatek: Add dt-bindings for MT8183 clocks
clk: mediatek: Add flags support for mtk_gate data
clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
clk: mediatek: Add MT8183 clock support
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,camsys.txt | 22 +
.../bindings/arm/mediatek/mediatek,imgsys.txt | 1 +
.../arm/mediatek/mediatek,infracfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,ipu.txt | 43 +
.../bindings/arm/mediatek/mediatek,mcucfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
.../arm/mediatek/mediatek,topckgen.txt | 1 +
.../arm/mediatek/mediatek,vdecsys.txt | 1 +
.../arm/mediatek/mediatek,vencsys.txt | 1 +
drivers/clk/mediatek/Kconfig | 75 +
drivers/clk/mediatek/Makefile | 15 +-
drivers/clk/mediatek/clk-gate.c | 5 +-
drivers/clk/mediatek/clk-gate.h | 17 +-
drivers/clk/mediatek/clk-mt8183-audio.c | 105 ++
drivers/clk/mediatek/clk-mt8183-cam.c | 63 +
drivers/clk/mediatek/clk-mt8183-img.c | 63 +
drivers/clk/mediatek/clk-mt8183-ipu0.c | 56 +
drivers/clk/mediatek/clk-mt8183-ipu1.c | 56 +
drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 54 +
drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 123 ++
drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 54 +
drivers/clk/mediatek/clk-mt8183-mm.c | 111 ++
drivers/clk/mediatek/clk-mt8183-vdec.c | 67 +
drivers/clk/mediatek/clk-mt8183-venc.c | 59 +
drivers/clk/mediatek/clk-mt8183.c | 1284 +++++++++++++++++
drivers/clk/mediatek/clk-mtk.c | 3 +-
drivers/clk/mediatek/clk-mtk.h | 4 +
drivers/clk/mediatek/clk-mux.c | 223 +++
drivers/clk/mediatek/clk-mux.h | 89 ++
drivers/clk/mediatek/clk-pll.c | 87 +-
include/dt-bindings/clock/mt8183-clk.h | 422 ++++++
34 files changed, 3073 insertions(+), 37 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt
create mode 100644 drivers/clk/mediatek/clk-mt8183-audio.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-cam.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-img.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu0.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu1.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_adl.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_conn.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-mfgcfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-venc.c
create mode 100644 drivers/clk/mediatek/clk-mt8183.c
create mode 100644 drivers/clk/mediatek/clk-mux.c
create mode 100644 drivers/clk/mediatek/clk-mux.h
create mode 100644 include/dt-bindings/clock/mt8183-clk.h
--
2.18.0
This patch adds the binding documentation for apmixedsys, audiosys,
camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys,
vencsys and ipu for Mediatek MT8183.
Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
---
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,camsys.txt | 22 ++++++++++
.../bindings/arm/mediatek/mediatek,imgsys.txt | 1 +
.../arm/mediatek/mediatek,infracfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,ipu.txt | 43 +++++++++++++++++++
.../bindings/arm/mediatek/mediatek,mcucfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
.../arm/mediatek/mediatek,topckgen.txt | 1 +
.../arm/mediatek/mediatek,vdecsys.txt | 1 +
.../arm/mediatek/mediatek,vencsys.txt | 1 +
12 files changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index de4075413d91..9adf28d0141b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
+ - "mediatek,mt8183-apmixedsys", "syscon"
- #clock-cells: Must be 1
The apmixedsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index d1606b2c3e63..f3cef1a6d95c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
+ - "mediatek,mt8183-audiosys", "syscon"
- #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
new file mode 100644
index 000000000000..d8930f64aa98
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
@@ -0,0 +1,22 @@
+MediaTek CAMSYS controller
+============================
+
+The MediaTek camsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+ - "mediatek,mt8183-camsys", "syscon"
+- #clock-cells: Must be 1
+
+The camsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+camsys: camsys@1a000000 {
+ compatible = "mediatek,mt8183-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index 3f99672163e3..e3bc4a1e7a6e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6797-imgsys", "syscon"
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
+ - "mediatek,mt8183-imgsys", "syscon"
- #clock-cells: Must be 1
The imgsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index 417bd83d1378..0b324d216724 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
+ - "mediatek,mt8183-infracfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt
new file mode 100644
index 000000000000..aabc8c5c8ed2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipu.txt
@@ -0,0 +1,43 @@
+Mediatek IPU controller
+============================
+
+The Mediatek ipu controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+ - "mediatek,mt8183-ipu_conn", "syscon"
+ - "mediatek,mt8183-ipu_adl", "syscon"
+ - "mediatek,mt8183-ipu_core0", "syscon"
+ - "mediatek,mt8183-ipu_core1", "syscon"
+- #clock-cells: Must be 1
+
+The ipu controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+ipu_conn: syscon@19000000 {
+ compatible = "mediatek,mt8183-ipu_conn", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+};
+
+ipu_adl: syscon@19010000 {
+ compatible = "mediatek,mt8183-ipu_adl", "syscon";
+ reg = <0 0x19010000 0 0x1000>;
+ #clock-cells = <1>;
+};
+
+ipu_core0: syscon@19180000 {
+ compatible = "mediatek,mt8183-ipu_core0", "syscon";
+ reg = <0 0x19180000 0 0x1000>;
+ #clock-cells = <1>;
+};
+
+ipu_core1: syscon@19280000 {
+ compatible = "mediatek,mt8183-ipu_core1", "syscon";
+ reg = <0 0x19280000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
index b8fb03f3613e..2b882b7ca72e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2712-mcucfg", "syscon"
+ - "mediatek,mt8183-mcucfg", "syscon"
- #clock-cells: Must be 1
The mcucfg controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
index 859e67b416d5..72787e7dd227 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2712-mfgcfg", "syscon"
+ - "mediatek,mt8183-mfgcfg", "syscon"
- #clock-cells: Must be 1
The mfgcfg controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 15d977afad31..545eab717c96 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
+ - "mediatek,mt8183-mmsys", "syscon"
- #clock-cells: Must be 1
The mmsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index d160c2b4b6fe..46a1cfeb8b1d 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7629-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen"
+ - "mediatek,mt8183-topckgen", "syscon"
- #clock-cells: Must be 1
The topckgen controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index 3212afc753c8..57176bb8dbb5 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6797-vdecsys", "syscon"
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
+ - "mediatek,mt8183-vdecsys", "syscon"
- #clock-cells: Must be 1
The vdecsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
index 851545357e94..c9faa6269087 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2712-vencsys", "syscon"
- "mediatek,mt6797-vencsys", "syscon"
- "mediatek,mt8173-vencsys", "syscon"
+ - "mediatek,mt8183-vencsys", "syscon"
- #clock-cells: Must be 1
The vencsys controller uses the common clk binding from
--
2.18.0
From: Owen Chen <[email protected]>
1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
add a variable to indicate this change and
backward-compatible.
2. fmin: The pll freqency lower-bound is vary from 1GMhz to
1.5Ghz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen <[email protected]>
Signed-off-by: Weiyi Lu <[email protected]>
Acked-by: Sean Wang <[email protected]>
---
drivers/clk/mediatek/clk-mtk.h | 2 ++
drivers/clk/mediatek/clk-pll.c | 15 +++++++++++----
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f83c2bbb677e..11b5517903d0 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -214,8 +214,10 @@ struct mtk_pll_data {
unsigned int flags;
const struct clk_ops *ops;
u32 rst_bar_mask;
+ unsigned long fmin;
unsigned long fmax;
int pcwbits;
+ int pcwibits;
uint32_t pcw_reg;
int pcw_shift;
const struct mtk_pll_div_table *div_table;
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 18842d660317..67aaa3082d9b 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -32,6 +32,8 @@
#define AUDPLL_TUNER_EN BIT(31)
#define POSTDIV_MASK 0x7
+
+/* default 7 bits integer, can be overridden with pcwibits. */
#define INTEGER_BITS 7
/*
@@ -68,12 +70,15 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
u32 pcw, int postdiv)
{
int pcwbits = pll->data->pcwbits;
- int pcwfbits;
+ int pcwfbits = 0;
+ int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
- pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
+ ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
+ if (pcwbits > ibits)
+ pcwfbits = pcwbits - ibits;
vco = (u64)fin * pcw;
@@ -170,9 +175,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
u32 freq, u32 fin)
{
- unsigned long fmin = 1000 * MHZ;
+ unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
const struct mtk_pll_div_table *div_table = pll->data->div_table;
u64 _pcw;
+ int ibits;
u32 val;
if (freq > pll->data->fmax)
@@ -196,7 +202,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
}
/* _pcw = freq * postdiv / fin * 2^pcwfbits */
- _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
+ ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
do_div(_pcw, fin);
*pcw = (u32)_pcw;
--
2.18.0
Add MT8183 clock dt-bindings, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
include/dt-bindings/clock/mt8183-clk.h | 422 +++++++++++++++++++++++++
1 file changed, 422 insertions(+)
create mode 100644 include/dt-bindings/clock/mt8183-clk.h
diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
new file mode 100644
index 000000000000..0046506eb24c
--- /dev/null
+++ b/include/dt-bindings/clock/mt8183-clk.h
@@ -0,0 +1,422 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Weiyi Lu <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8183_H
+#define _DT_BINDINGS_CLK_MT8183_H
+
+/* APMIXED */
+#define CLK_APMIXED_ARMPLL_LL 0
+#define CLK_APMIXED_ARMPLL_L 1
+#define CLK_APMIXED_CCIPLL 2
+#define CLK_APMIXED_MAINPLL 3
+#define CLK_APMIXED_UNIV2PLL 4
+#define CLK_APMIXED_MSDCPLL 5
+#define CLK_APMIXED_MMPLL 6
+#define CLK_APMIXED_MFGPLL 7
+#define CLK_APMIXED_TVDPLL 8
+#define CLK_APMIXED_APLL1 9
+#define CLK_APMIXED_APLL2 10
+#define CLK_APMIXED_SSUSB_26M 11
+#define CLK_APMIXED_APPLL_26M 12
+#define CLK_APMIXED_MIPIC0_26M 13
+#define CLK_APMIXED_MDPLLGP_26M 14
+#define CLK_APMIXED_MMSYS_26M 15
+#define CLK_APMIXED_UFS_26M 16
+#define CLK_APMIXED_MIPIC1_26M 17
+#define CLK_APMIXED_MEMPLL_26M 18
+#define CLK_APMIXED_CLKSQ_LVPLL_26M 19
+#define CLK_APMIXED_MIPID0_26M 20
+#define CLK_APMIXED_MIPID1_26M 21
+#define CLK_APMIXED_NR_CLK 22
+
+/* TOPCKGEN */
+#define CLK_TOP_MUX_AXI 0
+#define CLK_TOP_MUX_MM 1
+#define CLK_TOP_MUX_CAM 2
+#define CLK_TOP_MUX_MFG 3
+#define CLK_TOP_MUX_CAMTG 4
+#define CLK_TOP_MUX_UART 5
+#define CLK_TOP_MUX_SPI 6
+#define CLK_TOP_MUX_MSDC50_0_HCLK 7
+#define CLK_TOP_MUX_MSDC50_0 8
+#define CLK_TOP_MUX_MSDC30_1 9
+#define CLK_TOP_MUX_MSDC30_2 10
+#define CLK_TOP_MUX_AUDIO 11
+#define CLK_TOP_MUX_AUD_INTBUS 12
+#define CLK_TOP_MUX_FPWRAP_ULPOSC 13
+#define CLK_TOP_MUX_SCP 14
+#define CLK_TOP_MUX_ATB 15
+#define CLK_TOP_MUX_SSPM 16
+#define CLK_TOP_MUX_DPI0 17
+#define CLK_TOP_MUX_SCAM 18
+#define CLK_TOP_MUX_AUD_1 19
+#define CLK_TOP_MUX_AUD_2 20
+#define CLK_TOP_MUX_DISP_PWM 21
+#define CLK_TOP_MUX_SSUSB_TOP_XHCI 22
+#define CLK_TOP_MUX_USB_TOP 23
+#define CLK_TOP_MUX_SPM 24
+#define CLK_TOP_MUX_I2C 25
+#define CLK_TOP_MUX_F52M_MFG 26
+#define CLK_TOP_MUX_SENINF 27
+#define CLK_TOP_MUX_DXCC 28
+#define CLK_TOP_MUX_CAMTG2 29
+#define CLK_TOP_MUX_AUD_ENG1 30
+#define CLK_TOP_MUX_AUD_ENG2 31
+#define CLK_TOP_MUX_FAES_UFSFDE 32
+#define CLK_TOP_MUX_FUFS 33
+#define CLK_TOP_MUX_IMG 34
+#define CLK_TOP_MUX_DSP 35
+#define CLK_TOP_MUX_DSP1 36
+#define CLK_TOP_MUX_DSP2 37
+#define CLK_TOP_MUX_IPU_IF 38
+#define CLK_TOP_MUX_CAMTG3 39
+#define CLK_TOP_MUX_CAMTG4 40
+#define CLK_TOP_MUX_PMICSPI 41
+#define CLK_TOP_SYSPLL_CK 42
+#define CLK_TOP_SYSPLL_D2 43
+#define CLK_TOP_SYSPLL_D3 44
+#define CLK_TOP_SYSPLL_D5 45
+#define CLK_TOP_SYSPLL_D7 46
+#define CLK_TOP_SYSPLL_D2_D2 47
+#define CLK_TOP_SYSPLL_D2_D4 48
+#define CLK_TOP_SYSPLL_D2_D8 49
+#define CLK_TOP_SYSPLL_D2_D16 50
+#define CLK_TOP_SYSPLL_D3_D2 51
+#define CLK_TOP_SYSPLL_D3_D4 52
+#define CLK_TOP_SYSPLL_D3_D8 53
+#define CLK_TOP_SYSPLL_D5_D2 54
+#define CLK_TOP_SYSPLL_D5_D4 55
+#define CLK_TOP_SYSPLL_D7_D2 56
+#define CLK_TOP_SYSPLL_D7_D4 57
+#define CLK_TOP_UNIVPLL_CK 58
+#define CLK_TOP_UNIVPLL_D2 59
+#define CLK_TOP_UNIVPLL_D3 60
+#define CLK_TOP_UNIVPLL_D5 61
+#define CLK_TOP_UNIVPLL_D7 62
+#define CLK_TOP_UNIVPLL_D2_D2 63
+#define CLK_TOP_UNIVPLL_D2_D4 64
+#define CLK_TOP_UNIVPLL_D2_D8 65
+#define CLK_TOP_UNIVPLL_D3_D2 66
+#define CLK_TOP_UNIVPLL_D3_D4 67
+#define CLK_TOP_UNIVPLL_D3_D8 68
+#define CLK_TOP_UNIVPLL_D5_D2 69
+#define CLK_TOP_UNIVPLL_D5_D4 70
+#define CLK_TOP_UNIVPLL_D5_D8 71
+#define CLK_TOP_APLL1_CK 72
+#define CLK_TOP_APLL1_D2 73
+#define CLK_TOP_APLL1_D4 74
+#define CLK_TOP_APLL1_D8 75
+#define CLK_TOP_APLL2_CK 76
+#define CLK_TOP_APLL2_D2 77
+#define CLK_TOP_APLL2_D4 78
+#define CLK_TOP_APLL2_D8 79
+#define CLK_TOP_TVDPLL_CK 80
+#define CLK_TOP_TVDPLL_D2 81
+#define CLK_TOP_TVDPLL_D4 82
+#define CLK_TOP_TVDPLL_D8 83
+#define CLK_TOP_TVDPLL_D16 84
+#define CLK_TOP_MSDCPLL_CK 85
+#define CLK_TOP_MSDCPLL_D2 86
+#define CLK_TOP_MSDCPLL_D4 87
+#define CLK_TOP_MSDCPLL_D8 88
+#define CLK_TOP_MSDCPLL_D16 89
+#define CLK_TOP_AD_OSC_CK 90
+#define CLK_TOP_OSC_D2 91
+#define CLK_TOP_OSC_D4 92
+#define CLK_TOP_OSC_D8 93
+#define CLK_TOP_OSC_D16 94
+#define CLK_TOP_F26M_CK_D2 95
+#define CLK_TOP_MFGPLL_CK 96
+#define CLK_TOP_UNIVP_192M_CK 97
+#define CLK_TOP_UNIVP_192M_D2 98
+#define CLK_TOP_UNIVP_192M_D4 99
+#define CLK_TOP_UNIVP_192M_D8 100
+#define CLK_TOP_UNIVP_192M_D16 101
+#define CLK_TOP_UNIVP_192M_D32 102
+#define CLK_TOP_MMPLL_CK 103
+#define CLK_TOP_MMPLL_D4 104
+#define CLK_TOP_MMPLL_D4_D2 105
+#define CLK_TOP_MMPLL_D4_D4 106
+#define CLK_TOP_MMPLL_D5 107
+#define CLK_TOP_MMPLL_D5_D2 108
+#define CLK_TOP_MMPLL_D5_D4 109
+#define CLK_TOP_MMPLL_D6 110
+#define CLK_TOP_MMPLL_D7 111
+#define CLK_TOP_CLK26M 112
+#define CLK_TOP_CLK13M 113
+#define CLK_TOP_ULPOSC 114
+#define CLK_TOP_UNIVP_192M 115
+#define CLK_TOP_MUX_APLL_I2S0 116
+#define CLK_TOP_MUX_APLL_I2S1 117
+#define CLK_TOP_MUX_APLL_I2S2 118
+#define CLK_TOP_MUX_APLL_I2S3 119
+#define CLK_TOP_MUX_APLL_I2S4 120
+#define CLK_TOP_MUX_APLL_I2S5 121
+#define CLK_TOP_APLL12_DIV0 122
+#define CLK_TOP_APLL12_DIV1 123
+#define CLK_TOP_APLL12_DIV2 124
+#define CLK_TOP_APLL12_DIV3 125
+#define CLK_TOP_APLL12_DIV4 126
+#define CLK_TOP_APLL12_DIVB 127
+#define CLK_TOP_UNIVPLL 128
+#define CLK_TOP_ARMPLL_DIV_PLL1 129
+#define CLK_TOP_ARMPLL_DIV_PLL2 130
+#define CLK_TOP_UNIVPLL_D3_D16 131
+#define CLK_TOP_NR_CLK 132
+
+/* CAMSYS */
+#define CLK_CAM_LARB6 0
+#define CLK_CAM_DFP_VAD 1
+#define CLK_CAM_CAM 2
+#define CLK_CAM_CAMTG 3
+#define CLK_CAM_SENINF 4
+#define CLK_CAM_CAMSV0 5
+#define CLK_CAM_CAMSV1 6
+#define CLK_CAM_CAMSV2 7
+#define CLK_CAM_CCU 8
+#define CLK_CAM_LARB3 9
+#define CLK_CAM_NR_CLK 10
+
+/* INFRACFG_AO */
+#define CLK_INFRA_PMIC_TMR 0
+#define CLK_INFRA_PMIC_AP 1
+#define CLK_INFRA_PMIC_MD 2
+#define CLK_INFRA_PMIC_CONN 3
+#define CLK_INFRA_SCPSYS 4
+#define CLK_INFRA_SEJ 5
+#define CLK_INFRA_APXGPT 6
+#define CLK_INFRA_ICUSB 7
+#define CLK_INFRA_GCE 8
+#define CLK_INFRA_THERM 9
+#define CLK_INFRA_I2C0 10
+#define CLK_INFRA_I2C1 11
+#define CLK_INFRA_I2C2 12
+#define CLK_INFRA_I2C3 13
+#define CLK_INFRA_PWM_HCLK 14
+#define CLK_INFRA_PWM1 15
+#define CLK_INFRA_PWM2 16
+#define CLK_INFRA_PWM3 17
+#define CLK_INFRA_PWM4 18
+#define CLK_INFRA_PWM 19
+#define CLK_INFRA_UART0 20
+#define CLK_INFRA_UART1 21
+#define CLK_INFRA_UART2 22
+#define CLK_INFRA_UART3 23
+#define CLK_INFRA_GCE_26M 24
+#define CLK_INFRA_CQ_DMA_FPC 25
+#define CLK_INFRA_BTIF 26
+#define CLK_INFRA_SPI0 27
+#define CLK_INFRA_MSDC0 28
+#define CLK_INFRA_MSDC1 29
+#define CLK_INFRA_MSDC2 30
+#define CLK_INFRA_MSDC0_SCK 31
+#define CLK_INFRA_DVFSRC 32
+#define CLK_INFRA_GCPU 33
+#define CLK_INFRA_TRNG 34
+#define CLK_INFRA_AUXADC 35
+#define CLK_INFRA_CPUM 36
+#define CLK_INFRA_CCIF1_AP 37
+#define CLK_INFRA_CCIF1_MD 38
+#define CLK_INFRA_AUXADC_MD 39
+#define CLK_INFRA_MSDC1_SCK 40
+#define CLK_INFRA_MSDC2_SCK 41
+#define CLK_INFRA_AP_DMA 42
+#define CLK_INFRA_XIU 43
+#define CLK_INFRA_DEVICE_APC 44
+#define CLK_INFRA_CCIF_AP 45
+#define CLK_INFRA_DEBUGSYS 46
+#define CLK_INFRA_AUDIO 47
+#define CLK_INFRA_CCIF_MD 48
+#define CLK_INFRA_DXCC_SEC_CORE 49
+#define CLK_INFRA_DXCC_AO 50
+#define CLK_INFRA_DRAMC_F26M 51
+#define CLK_INFRA_IRTX 52
+#define CLK_INFRA_DISP_PWM 53
+#define CLK_INFRA_CLDMA_BCLK 54
+#define CLK_INFRA_AUDIO_26M_BCLK 55
+#define CLK_INFRA_SPI1 56
+#define CLK_INFRA_I2C4 57
+#define CLK_INFRA_MODEM_TEMP_SHARE 58
+#define CLK_INFRA_SPI2 59
+#define CLK_INFRA_SPI3 60
+#define CLK_INFRA_UNIPRO_SCK 61
+#define CLK_INFRA_UNIPRO_TICK 62
+#define CLK_INFRA_UFS_MP_SAP_BCLK 63
+#define CLK_INFRA_MD32_BCLK 64
+#define CLK_INFRA_SSPM 65
+#define CLK_INFRA_UNIPRO_MBIST 66
+#define CLK_INFRA_SSPM_BUS_HCLK 67
+#define CLK_INFRA_I2C5 68
+#define CLK_INFRA_I2C5_ARBITER 69
+#define CLK_INFRA_I2C5_IMM 70
+#define CLK_INFRA_I2C1_ARBITER 71
+#define CLK_INFRA_I2C1_IMM 72
+#define CLK_INFRA_I2C2_ARBITER 73
+#define CLK_INFRA_I2C2_IMM 74
+#define CLK_INFRA_SPI4 75
+#define CLK_INFRA_SPI5 76
+#define CLK_INFRA_CQ_DMA 77
+#define CLK_INFRA_UFS 78
+#define CLK_INFRA_AES_UFSFDE 79
+#define CLK_INFRA_UFS_TICK 80
+#define CLK_INFRA_MSDC0_SELF 81
+#define CLK_INFRA_MSDC1_SELF 82
+#define CLK_INFRA_MSDC2_SELF 83
+#define CLK_INFRA_SSPM_26M_SELF 84
+#define CLK_INFRA_SSPM_32K_SELF 85
+#define CLK_INFRA_UFS_AXI 86
+#define CLK_INFRA_I2C6 87
+#define CLK_INFRA_AP_MSDC0 88
+#define CLK_INFRA_MD_MSDC0 89
+#define CLK_INFRA_USB 90
+#define CLK_INFRA_DEVMPU_BCLK 91
+#define CLK_INFRA_CCIF2_AP 92
+#define CLK_INFRA_CCIF2_MD 93
+#define CLK_INFRA_CCIF3_AP 94
+#define CLK_INFRA_CCIF3_MD 95
+#define CLK_INFRA_SEJ_F13M 96
+#define CLK_INFRA_AES_BCLK 97
+#define CLK_INFRA_I2C7 98
+#define CLK_INFRA_I2C8 99
+#define CLK_INFRA_FBIST2FPC 100
+#define CLK_INFRA_NR_CLK 101
+
+/* MFGCFG */
+#define CLK_MFG_BG3D 0
+#define CLK_MFG_NR_CLK 1
+
+/* IMG */
+#define CLK_IMG_OWE 0
+#define CLK_IMG_WPE_B 1
+#define CLK_IMG_WPE_A 2
+#define CLK_IMG_MFB 3
+#define CLK_IMG_RSC 4
+#define CLK_IMG_DPE 5
+#define CLK_IMG_FDVT 6
+#define CLK_IMG_DIP 7
+#define CLK_IMG_LARB2 8
+#define CLK_IMG_LARB5 9
+#define CLK_IMG_NR_CLK 10
+
+/* MMSYS_CONFIG */
+#define CLK_MM_SMI_COMMON 0
+#define CLK_MM_SMI_LARB0 1
+#define CLK_MM_SMI_LARB1 2
+#define CLK_MM_GALS_COMM0 3
+#define CLK_MM_GALS_COMM1 4
+#define CLK_MM_GALS_CCU2MM 5
+#define CLK_MM_GALS_IPU12MM 6
+#define CLK_MM_GALS_IMG2MM 7
+#define CLK_MM_GALS_CAM2MM 8
+#define CLK_MM_GALS_IPU2MM 9
+#define CLK_MM_MDP_DL_TXCK 10
+#define CLK_MM_IPU_DL_TXCK 11
+#define CLK_MM_MDP_RDMA0 12
+#define CLK_MM_MDP_RDMA1 13
+#define CLK_MM_MDP_RSZ0 14
+#define CLK_MM_MDP_RSZ1 15
+#define CLK_MM_MDP_TDSHP 16
+#define CLK_MM_MDP_WROT0 17
+#define CLK_MM_FAKE_ENG 18
+#define CLK_MM_DISP_OVL0 19
+#define CLK_MM_DISP_OVL0_2L 20
+#define CLK_MM_DISP_OVL1_2L 21
+#define CLK_MM_DISP_RDMA0 22
+#define CLK_MM_DISP_RDMA1 23
+#define CLK_MM_DISP_WDMA0 24
+#define CLK_MM_DISP_COLOR0 25
+#define CLK_MM_DISP_CCORR0 26
+#define CLK_MM_DISP_AAL0 27
+#define CLK_MM_DISP_GAMMA0 28
+#define CLK_MM_DISP_DITHER0 29
+#define CLK_MM_DISP_SPLIT 30
+#define CLK_MM_DSI0_MM 31
+#define CLK_MM_DSI0_IF 32
+#define CLK_MM_DPI_MM 33
+#define CLK_MM_DPI_IF 34
+#define CLK_MM_FAKE_ENG2 35
+#define CLK_MM_MDP_DL_RX 36
+#define CLK_MM_IPU_DL_RX 37
+#define CLK_MM_26M 38
+#define CLK_MM_MMSYS_R2Y 39
+#define CLK_MM_DISP_RSZ 40
+#define CLK_MM_MDP_WDMA0 41
+#define CLK_MM_MDP_AAL 42
+#define CLK_MM_MDP_CCORR 43
+#define CLK_MM_DBI_MM 44
+#define CLK_MM_DBI_IF 45
+#define CLK_MM_NR_CLK 46
+
+/* VDEC_GCON */
+#define CLK_VDEC_VDEC 0
+#define CLK_VDEC_LARB1 1
+#define CLK_VDEC_NR_CLK 2
+
+/* VENC_GCON */
+#define CLK_VENC_LARB 0
+#define CLK_VENC_VENC 1
+#define CLK_VENC_JPGENC 2
+#define CLK_VENC_NR_CLK 3
+
+/* AUDIO */
+#define CLK_AUDIO_TML 0
+#define CLK_AUDIO_DAC_PREDIS 1
+#define CLK_AUDIO_DAC 2
+#define CLK_AUDIO_ADC 3
+#define CLK_AUDIO_APLL_TUNER 4
+#define CLK_AUDIO_APLL2_TUNER 5
+#define CLK_AUDIO_24M 6
+#define CLK_AUDIO_22M 7
+#define CLK_AUDIO_AFE 8
+#define CLK_AUDIO_I2S4 9
+#define CLK_AUDIO_I2S3 10
+#define CLK_AUDIO_I2S2 11
+#define CLK_AUDIO_I2S1 12
+#define CLK_AUDIO_PDN_ADDA6_ADC 13
+#define CLK_AUDIO_TDM 14
+#define CLK_AUDIO_NR_CLK 15
+
+/* IPU_CONN */
+#define CLK_IPU_CONN_IPU 0
+#define CLK_IPU_CONN_AHB 1
+#define CLK_IPU_CONN_AXI 2
+#define CLK_IPU_CONN_ISP 3
+#define CLK_IPU_CONN_CAM_ADL 4
+#define CLK_IPU_CONN_IMG_ADL 5
+#define CLK_IPU_CONN_DAP_RX 6
+#define CLK_IPU_CONN_APB2AXI 7
+#define CLK_IPU_CONN_APB2AHB 8
+#define CLK_IPU_CONN_IPU_CAB1TO2 9
+#define CLK_IPU_CONN_IPU1_CAB1TO2 10
+#define CLK_IPU_CONN_IPU2_CAB1TO2 11
+#define CLK_IPU_CONN_CAB3TO3 12
+#define CLK_IPU_CONN_CAB2TO1 13
+#define CLK_IPU_CONN_CAB3TO1_SLICE 14
+#define CLK_IPU_CONN_NR_CLK 15
+
+/* IPU_ADL */
+#define CLK_IPU_ADL_CABGEN 0
+#define CLK_IPU_ADL_NR_CLK 1
+
+/* IPU_CORE0 */
+#define CLK_IPU_CORE0_JTAG 0
+#define CLK_IPU_CORE0_AXI 1
+#define CLK_IPU_CORE0_IPU 2
+#define CLK_IPU_CORE0_NR_CLK 3
+
+/* IPU_CORE1 */
+#define CLK_IPU_CORE1_JTAG 0
+#define CLK_IPU_CORE1_AXI 1
+#define CLK_IPU_CORE1_IPU 2
+#define CLK_IPU_CORE1_NR_CLK 3
+
+/* MCUCFG */
+#define CLK_MCU_MP0_SEL 0
+#define CLK_MCU_MP2_SEL 1
+#define CLK_MCU_BUS_SEL 2
+#define CLK_MCU_NR_CLK 3
+
+#endif /* _DT_BINDINGS_CLK_MT8183_H */
--
2.18.0
Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/Kconfig | 75 ++
drivers/clk/mediatek/Makefile | 12 +
drivers/clk/mediatek/clk-gate.h | 14 +
drivers/clk/mediatek/clk-mt8183-audio.c | 105 ++
drivers/clk/mediatek/clk-mt8183-cam.c | 63 +
drivers/clk/mediatek/clk-mt8183-img.c | 63 +
drivers/clk/mediatek/clk-mt8183-ipu0.c | 56 +
drivers/clk/mediatek/clk-mt8183-ipu1.c | 56 +
drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 54 +
drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 123 ++
drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 54 +
drivers/clk/mediatek/clk-mt8183-mm.c | 111 ++
drivers/clk/mediatek/clk-mt8183-vdec.c | 67 +
drivers/clk/mediatek/clk-mt8183-venc.c | 59 +
drivers/clk/mediatek/clk-mt8183.c | 1284 ++++++++++++++++++++
15 files changed, 2196 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8183-audio.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-cam.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-img.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu0.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu1.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_adl.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_conn.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-mfgcfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8183-venc.c
create mode 100644 drivers/clk/mediatek/clk-mt8183.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 53edade25a1d..1cc414290818 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -216,4 +216,79 @@ config COMMON_CLK_MT8173
default ARCH_MEDIATEK
---help---
This driver supports MediaTek MT8173 clocks.
+
+config COMMON_CLK_MT8183
+ bool "Clock driver for MediaTek MT8183"
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK && ARM64
+ help
+ This driver supports MediaTek MT8183 basic clocks.
+
+config COMMON_CLK_MT8183_AUDIOSYS
+ bool "Clock driver for MediaTek MT8183 audiosys"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 audiosys clocks.
+
+config COMMON_CLK_MT8183_CAMSYS
+ bool "Clock driver for MediaTek MT8183 camsys"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 camsys clocks.
+
+config COMMON_CLK_MT8183_IMGSYS
+ bool "Clock driver for MediaTek MT8183 imgsys"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 imgsys clocks.
+
+config COMMON_CLK_MT8183_IPU_CORE0
+ bool "Clock driver for MediaTek MT8183 ipu_core0"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 ipu_core0 clocks.
+
+config COMMON_CLK_MT8183_IPU_CORE1
+ bool "Clock driver for MediaTek MT8183 ipu_core1"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 ipu_core1 clocks.
+
+config COMMON_CLK_MT8183_IPU_ADL
+ bool "Clock driver for MediaTek MT8183 ipu_adl"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 ipu_adl clocks.
+
+config COMMON_CLK_MT8183_IPU_CONN
+ bool "Clock driver for MediaTek MT8183 ipu_conn"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 ipu_conn clocks.
+
+config COMMON_CLK_MT8183_MFGCFG
+ bool "Clock driver for MediaTek MT8183 mfgcfg"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 mfgcfg clocks.
+
+config COMMON_CLK_MT8183_MMSYS
+ bool "Clock driver for MediaTek MT8183 mmsys"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 mmsys clocks.
+
+config COMMON_CLK_MT8183_VDECSYS
+ bool "Clock driver for MediaTek MT8183 vdecsys"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 vdecsys clocks.
+
+config COMMON_CLK_MT8183_VENCSYS
+ bool "Clock driver for MediaTek MT8183 vencsys"
+ depends on COMMON_CLK_MT8183
+ help
+ This driver supports MediaTek MT8183 vencsys clocks.
+
endmenu
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 20cf9eea4171..3dc1b9f15ea2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -32,3 +32,15 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
+obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
+obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o
+obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) += clk-mt8183-img.o
+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE0) += clk-mt8183-ipu0.o
+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE1) += clk-mt8183-ipu1.o
+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_ADL) += clk-mt8183-ipu_adl.o
+obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CONN) += clk-mt8183-ipu_conn.o
+obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
+obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
+obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
+obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 9f766dfe1d57..ab240163f9f8 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -50,4 +50,18 @@ struct clk *mtk_clk_register_gate(
const struct clk_ops *ops,
unsigned long flags);
+#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
+ _ops, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = _regs, \
+ .shift = _shift, \
+ .ops = _ops, \
+ .flags = _flags, \
+ }
+
+#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
+ GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
+
#endif /* __DRV_CLK_GATE_H */
diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c
new file mode 100644
index 000000000000..c87450180b7b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-audio.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs audio0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audio1_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_AUDIO0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr)
+
+#define GATE_AUDIO1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate audio_clks[] = {
+ /* AUDIO0 */
+ GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
+ 2),
+ GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
+ 8),
+ GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
+ 9),
+ GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
+ 18),
+ GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
+ 19),
+ GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
+ 20),
+ GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
+ 24),
+ GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
+ 25),
+ GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
+ 26),
+ GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
+ 27),
+ /* AUDIO1 */
+ GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
+ 4),
+ GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
+ 5),
+ GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
+ 6),
+ GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
+ 7),
+ GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
+ 20),
+};
+
+static int clk_mt8183_audio_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+
+ mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ return r;
+
+ r = devm_of_platform_populate(&pdev->dev);
+ if (r)
+ of_clk_del_provider(node);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt8183_audio[] = {
+ { .compatible = "mediatek,mt8183-audiosys", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_audio_drv = {
+ .probe = clk_mt8183_audio_probe,
+ .driver = {
+ .name = "clk-mt8183-audio",
+ .of_match_table = of_match_clk_mt8183_audio,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_audio_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-cam.c b/drivers/clk/mediatek/clk-mt8183-cam.c
new file mode 100644
index 000000000000..8643802c4471
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-cam.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs cam_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_CAM(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate cam_clks[] = {
+ GATE_CAM(CLK_CAM_LARB6, "cam_larb6", "cam_sel", 0),
+ GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
+ GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "cam_sel", 2),
+ GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
+ GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
+ GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
+ GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
+ GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
+ GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
+ GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),
+};
+
+static int clk_mt8183_cam_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
+
+ mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_cam[] = {
+ { .compatible = "mediatek,mt8183-camsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_cam_drv = {
+ .probe = clk_mt8183_cam_probe,
+ .driver = {
+ .name = "clk-mt8183-cam",
+ .of_match_table = of_match_clk_mt8183_cam,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_cam_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/clk-mt8183-img.c
new file mode 100644
index 000000000000..470d676a4a10
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-img.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs img_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate img_clks[] = {
+ GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
+ GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
+ GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
+ GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
+ GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
+ GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
+ GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
+ GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
+ GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
+ GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
+};
+
+static int clk_mt8183_img_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+
+ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_img[] = {
+ { .compatible = "mediatek,mt8183-imgsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_img_drv = {
+ .probe = clk_mt8183_img_probe,
+ .driver = {
+ .name = "clk-mt8183-img",
+ .of_match_table = of_match_clk_mt8183_img,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_img_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-ipu0.c b/drivers/clk/mediatek/clk-mt8183-ipu0.c
new file mode 100644
index 000000000000..c5cb76fc9e5e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-ipu0.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs ipu_core0_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IPU_CORE0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ipu_core0_clks[] = {
+ GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
+ GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
+ GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
+};
+
+static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
+
+ mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
+ { .compatible = "mediatek,mt8183-ipu_core0", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_ipu_core0_drv = {
+ .probe = clk_mt8183_ipu_core0_probe,
+ .driver = {
+ .name = "clk-mt8183-ipu_core0",
+ .of_match_table = of_match_clk_mt8183_ipu_core0,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_ipu_core0_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-ipu1.c b/drivers/clk/mediatek/clk-mt8183-ipu1.c
new file mode 100644
index 000000000000..8fd5fe002890
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-ipu1.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs ipu_core1_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IPU_CORE1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_core1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ipu_core1_clks[] = {
+ GATE_IPU_CORE1(CLK_IPU_CORE1_JTAG, "ipu_core1_jtag", "dsp_sel", 0),
+ GATE_IPU_CORE1(CLK_IPU_CORE1_AXI, "ipu_core1_axi", "dsp_sel", 1),
+ GATE_IPU_CORE1(CLK_IPU_CORE1_IPU, "ipu_core1_ipu", "dsp_sel", 2),
+};
+
+static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK);
+
+ mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {
+ { .compatible = "mediatek,mt8183-ipu_core1", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_ipu_core1_drv = {
+ .probe = clk_mt8183_ipu_core1_probe,
+ .driver = {
+ .name = "clk-mt8183-ipu_core1",
+ .of_match_table = of_match_clk_mt8183_ipu_core1,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_ipu_core1_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c
new file mode 100644
index 000000000000..3f37d0ef1df1
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs ipu_adl_cg_regs = {
+ .set_ofs = 0x204,
+ .clr_ofs = 0x204,
+ .sta_ofs = 0x204,
+};
+
+#define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate ipu_adl_clks[] = {
+ GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
+};
+
+static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
+
+ mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
+ { .compatible = "mediatek,mt8183-ipu_adl", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_ipu_adl_drv = {
+ .probe = clk_mt8183_ipu_adl_probe,
+ .driver = {
+ .name = "clk-mt8183-ipu_adl",
+ .of_match_table = of_match_clk_mt8183_ipu_adl,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_ipu_adl_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c
new file mode 100644
index 000000000000..7e0eef79c461
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs ipu_conn_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
+ .set_ofs = 0x18,
+ .clr_ofs = 0x18,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
+ .set_ofs = 0x1c,
+ .clr_ofs = 0x1c,
+ .sta_ofs = 0x1c,
+};
+
+static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
+ .set_ofs = 0x20,
+ .clr_ofs = 0x20,
+ .sta_ofs = 0x20,
+};
+
+#define GATE_IPU_CONN(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr)
+
+#define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate ipu_conn_clks[] = {
+ GATE_IPU_CONN(CLK_IPU_CONN_IPU,
+ "ipu_conn_ipu", "dsp_sel", 0),
+ GATE_IPU_CONN(CLK_IPU_CONN_AHB,
+ "ipu_conn_ahb", "dsp_sel", 1),
+ GATE_IPU_CONN(CLK_IPU_CONN_AXI,
+ "ipu_conn_axi", "dsp_sel", 2),
+ GATE_IPU_CONN(CLK_IPU_CONN_ISP,
+ "ipu_conn_isp", "dsp_sel", 3),
+ GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
+ "ipu_conn_cam_adl", "dsp_sel", 4),
+ GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
+ "ipu_conn_img_adl", "dsp_sel", 5),
+ GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
+ "ipu_conn_dap_rx", "dsp1_sel", 0),
+ GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
+ "ipu_conn_apb2axi", "dsp1_sel", 3),
+ GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
+ "ipu_conn_apb2ahb", "dsp1_sel", 20),
+ GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
+ "ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
+ GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
+ "ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
+ GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
+ "ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
+ GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
+ "ipu_conn_cab3to3", "dsp1_sel", 0),
+ GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
+ "ipu_conn_cab2to1", "dsp1_sel", 14),
+ GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
+ "ipu_conn_cab3to1_slice", "dsp1_sel", 17),
+};
+
+static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
+
+ mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
+ { .compatible = "mediatek,mt8183-ipu_conn", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_ipu_conn_drv = {
+ .probe = clk_mt8183_ipu_conn_probe,
+ .driver = {
+ .name = "clk-mt8183-ipu_conn",
+ .of_match_table = of_match_clk_mt8183_ipu_conn,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_ipu_conn_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
new file mode 100644
index 000000000000..99a6b020833e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs mfg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mfg_clks[] = {
+ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
+};
+
+static int clk_mt8183_mfg_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
+
+ mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_mfg[] = {
+ { .compatible = "mediatek,mt8183-mfgcfg", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_mfg_drv = {
+ .probe = clk_mt8183_mfg_probe,
+ .driver = {
+ .name = "clk-mt8183-mfg",
+ .of_match_table = of_match_clk_mt8183_mfg,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_mfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/clk-mt8183-mm.c
new file mode 100644
index 000000000000..720c696b506d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-mm.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+ .set_ofs = 0x114,
+ .clr_ofs = 0x118,
+ .sta_ofs = 0x110,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_MM1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mm_clks[] = {
+ /* MM0 */
+ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
+ GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+ GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
+ GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
+ GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
+ GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
+ GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
+ GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
+ GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
+ GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
+ GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
+ GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
+ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
+ GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
+ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
+ GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
+ GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
+ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
+ GATE_MM0(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 18),
+ GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
+ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
+ GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
+ GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
+ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
+ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
+ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
+ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
+ GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
+ GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
+ GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
+ GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
+ GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
+ /* MM1 */
+ GATE_MM1(CLK_MM_DSI0_MM, "mm_dsi0_mm", "mm_sel", 0),
+ GATE_MM1(CLK_MM_DSI0_IF, "mm_dsi0_if", "mm_sel", 1),
+ GATE_MM1(CLK_MM_DPI_MM, "mm_dpi_mm", "mm_sel", 2),
+ GATE_MM1(CLK_MM_DPI_IF, "mm_dpi_if", "dpi0_sel", 3),
+ GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
+ GATE_MM1(CLK_MM_MDP_DL_RX, "mm_mdp_dl_rx", "mm_sel", 5),
+ GATE_MM1(CLK_MM_IPU_DL_RX, "mm_ipu_dl_rx", "mm_sel", 6),
+ GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
+ GATE_MM1(CLK_MM_MMSYS_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
+ GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
+ GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
+ GATE_MM1(CLK_MM_MDP_CCORR, "mm_mdp_ccorr", "mm_sel", 11),
+ GATE_MM1(CLK_MM_DBI_MM, "mm_dbi_mm", "mm_sel", 12),
+ GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13),
+};
+
+static int clk_mt8183_mm_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+
+ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_mm[] = {
+ { .compatible = "mediatek,mt8183-mmsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_mm_drv = {
+ .probe = clk_mt8183_mm_probe,
+ .driver = {
+ .name = "clk-mt8183-mm",
+ .of_match_table = of_match_clk_mt8183_mm,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_mm_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/clk-mt8183-vdec.c
new file mode 100644
index 000000000000..6250fd1e0edc
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-vdec.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate vdec_clks[] = {
+ /* VDEC0 */
+ GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
+ /* VDEC1 */
+ GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
+};
+
+static int clk_mt8183_vdec_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
+
+ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_vdec[] = {
+ { .compatible = "mediatek,mt8183-vdecsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_vdec_drv = {
+ .probe = clk_mt8183_vdec_probe,
+ .driver = {
+ .name = "clk-mt8183-vdec",
+ .of_match_table = of_match_clk_mt8183_vdec,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_vdec_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183-venc.c b/drivers/clk/mediatek/clk-mt8183-venc.c
new file mode 100644
index 000000000000..6678ef03fab2
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183-venc.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static const struct mtk_gate_regs venc_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_VENC_I(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate venc_clks[] = {
+ GATE_VENC_I(CLK_VENC_LARB, "venc_larb",
+ "mm_sel", 0),
+ GATE_VENC_I(CLK_VENC_VENC, "venc_venc",
+ "mm_sel", 4),
+ GATE_VENC_I(CLK_VENC_JPGENC, "venc_jpgenc",
+ "mm_sel", 8),
+};
+
+static int clk_mt8183_venc_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
+
+ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183_venc[] = {
+ { .compatible = "mediatek,mt8183-vencsys", },
+ {}
+};
+
+static struct platform_driver clk_mt8183_venc_drv = {
+ .probe = clk_mt8183_venc_probe,
+ .driver = {
+ .name = "clk-mt8183-venc",
+ .of_match_table = of_match_clk_mt8183_venc,
+ },
+};
+
+builtin_platform_driver(clk_mt8183_venc_drv);
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
new file mode 100644
index 000000000000..68f157b31b28
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -0,0 +1,1284 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2018 MediaTek Inc.
+// Author: Weiyi Lu <[email protected]>
+
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8183-clk.h>
+
+static DEFINE_SPINLOCK(mt8183_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
+ FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
+ FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
+ 2),
+ FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
+ 1),
+ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
+ 4),
+ FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
+ 8),
+ FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
+ 16),
+ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
+ 3),
+ FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
+ 4),
+ FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
+ 8),
+ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
+ 5),
+ FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
+ 4),
+ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
+ 7),
+ FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
+ 2),
+ FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
+ 1),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
+ 3),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
+ 5),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
+ 7),
+ FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
+ 1),
+ FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
+ 4),
+ FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
+ 8),
+ FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
+ 16),
+ FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
+ 32),
+ FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
+ 1),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
+ 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
+ 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
+ 8),
+ FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
+ 1),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
+ 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
+ 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
+ 8),
+ FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
+ 1),
+ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
+ 2),
+ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
+ 4),
+ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
+ 8),
+ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
+ 16),
+ FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
+ 4),
+ FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
+ 2),
+ FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
+ 4),
+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
+ 5),
+ FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
+ 2),
+ FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
+ 4),
+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
+ 6),
+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
+ 7),
+ FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
+ 1),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
+ 2),
+ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
+ 4),
+ FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
+ 8),
+ FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
+ 16),
+ FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
+ 1),
+ FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
+ 2),
+ FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
+ 4),
+ FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
+ 8),
+ FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
+ 16),
+ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
+ 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
+ 16),
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "syspll_d2_d4",
+ "syspll_d7",
+ "osc_d4"
+};
+
+static const char * const mm_parents[] = {
+ "clk26m",
+ "mmpll_d7",
+ "syspll_d3",
+ "univpll_d2_d2",
+ "syspll_d2_d2",
+ "syspll_d3_d2"
+};
+
+static const char * const img_parents[] = {
+ "clk26m",
+ "mmpll_d6",
+ "univpll_d3",
+ "syspll_d3",
+ "univpll_d2_d2",
+ "syspll_d2_d2",
+ "univpll_d3_d2",
+ "syspll_d3_d2"
+};
+
+static const char * const cam_parents[] = {
+ "clk26m",
+ "syspll_d2",
+ "mmpll_d6",
+ "syspll_d3",
+ "mmpll_d7",
+ "univpll_d3",
+ "univpll_d2_d2",
+ "syspll_d2_d2",
+ "syspll_d3_d2",
+ "univpll_d3_d2"
+};
+
+static const char * const dsp_parents[] = {
+ "clk26m",
+ "mmpll_d6",
+ "mmpll_d7",
+ "univpll_d3",
+ "syspll_d3",
+ "univpll_d2_d2",
+ "syspll_d2_d2",
+ "univpll_d3_d2",
+ "syspll_d3_d2"
+};
+
+static const char * const dsp1_parents[] = {
+ "clk26m",
+ "mmpll_d6",
+ "mmpll_d7",
+ "univpll_d3",
+ "syspll_d3",
+ "univpll_d2_d2",
+ "syspll_d2_d2",
+ "univpll_d3_d2",
+ "syspll_d3_d2"
+};
+
+static const char * const dsp2_parents[] = {
+ "clk26m",
+ "mmpll_d6",
+ "mmpll_d7",
+ "univpll_d3",
+ "syspll_d3",
+ "univpll_d2_d2",
+ "syspll_d2_d2",
+ "univpll_d3_d2",
+ "syspll_d3_d2"
+};
+
+static const char * const ipu_if_parents[] = {
+ "clk26m",
+ "mmpll_d6",
+ "mmpll_d7",
+ "univpll_d3",
+ "syspll_d3",
+ "univpll_d2_d2",
+ "syspll_d2_d2",
+ "univpll_d3_d2",
+ "syspll_d3_d2"
+};
+
+static const char * const mfg_parents[] = {
+ "clk26m",
+ "mfgpll_ck",
+ "univpll_d3",
+ "syspll_d3"
+};
+
+static const char * const f52m_mfg_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "univpll_d3_d4",
+ "univpll_d3_d8"
+};
+
+static const char * const camtg_parents[] = {
+ "clk26m",
+ "univ_192m_d8",
+ "univpll_d3_d8",
+ "univ_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univ_192m_d16",
+ "univ_192m_d32"
+};
+
+static const char * const camtg2_parents[] = {
+ "clk26m",
+ "univ_192m_d8",
+ "univpll_d3_d8",
+ "univ_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univ_192m_d16",
+ "univ_192m_d32"
+};
+
+static const char * const camtg3_parents[] = {
+ "clk26m",
+ "univ_192m_d8",
+ "univpll_d3_d8",
+ "univ_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univ_192m_d16",
+ "univ_192m_d32"
+};
+
+static const char * const camtg4_parents[] = {
+ "clk26m",
+ "univ_192m_d8",
+ "univpll_d3_d8",
+ "univ_192m_d4",
+ "univpll_d3_d16",
+ "csw_f26m_ck_d2",
+ "univ_192m_d16",
+ "univ_192m_d32"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll_d3_d8"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "syspll_d5_d2",
+ "syspll_d3_d4",
+ "msdcpll_d4"
+};
+
+static const char * const msdc50_hclk_parents[] = {
+ "clk26m",
+ "syspll_d2_d2",
+ "syspll_d3_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m",
+ "msdcpll_ck",
+ "msdcpll_d2",
+ "univpll_d2_d4",
+ "syspll_d3_d2",
+ "univpll_d2_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "syspll_d3_d2",
+ "syspll_d7",
+ "msdcpll_d2"
+};
+
+static const char * const msdc30_2_parents[] = {
+ "clk26m",
+ "univpll_d3_d2",
+ "syspll_d3_d2",
+ "syspll_d7",
+ "msdcpll_d2"
+};
+
+static const char * const audio_parents[] = {
+ "clk26m",
+ "syspll_d5_d4",
+ "syspll_d7_d4",
+ "syspll_d2_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "syspll_d2_d4",
+ "syspll_d7_d2"
+};
+
+static const char * const pmicspi_parents[] = {
+ "clk26m",
+ "syspll_d2_d8",
+ "osc_d8"
+};
+
+static const char * const fpwrap_ulposc_parents[] = {
+ "clk26m",
+ "osc_d16",
+ "osc_d4",
+ "osc_d8"
+};
+
+static const char * const atb_parents[] = {
+ "clk26m",
+ "syspll_d2_d2",
+ "syspll_d5"
+};
+
+static const char * const sspm_parents[] = {
+ "clk26m",
+ "univpll_d2_d4",
+ "syspll_d2_d2",
+ "univpll_d2_d2",
+ "syspll_d3"
+};
+
+static const char * const dpi0_parents[] = {
+ "clk26m",
+ "tvdpll_d2",
+ "tvdpll_d4",
+ "tvdpll_d8",
+ "tvdpll_d16",
+ "univpll_d5_d2",
+ "univpll_d3_d4",
+ "syspll_d3_d4",
+ "univpll_d3_d8"
+};
+
+static const char * const scam_parents[] = {
+ "clk26m",
+ "syspll_d5_d2"
+};
+
+static const char * const disppwm_parents[] = {
+ "clk26m",
+ "univpll_d3_d4",
+ "osc_d2",
+ "osc_d4",
+ "osc_d16"
+};
+
+static const char * const usb_top_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d3_d4",
+ "univpll_d5_d2"
+};
+
+
+static const char * const ssusb_top_xhci_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d3_d4",
+ "univpll_d5_d2"
+};
+
+static const char * const spm_parents[] = {
+ "clk26m",
+ "syspll_d2_d8"
+};
+
+static const char * const i2c_parents[] = {
+ "clk26m",
+ "syspll_d2_d8",
+ "univpll_d5_d2"
+};
+
+static const char * const scp_parents[] = {
+ "clk26m",
+ "univpll_d2_d8",
+ "syspll_d5",
+ "syspll_d2_d2",
+ "univpll_d2_d2",
+ "syspll_d3",
+ "univpll_d3"
+};
+
+static const char * const seninf_parents[] = {
+ "clk26m",
+ "univpll_d2_d2",
+ "univpll_d3_d2",
+ "univpll_d2_d4"
+};
+
+static const char * const dxcc_parents[] = {
+ "clk26m",
+ "syspll_d2_d2",
+ "syspll_d2_d4",
+ "syspll_d2_d8"
+};
+
+static const char * const aud_engen1_parents[] = {
+ "clk26m",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+ "clk26m",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8"
+};
+
+static const char * const faes_ufsfde_parents[] = {
+ "clk26m",
+ "syspll_d2",
+ "syspll_d2_d2",
+ "syspll_d3",
+ "syspll_d2_d4",
+ "univpll_d3"
+};
+
+static const char * const fufs_parents[] = {
+ "clk26m",
+ "syspll_d2_d4",
+ "syspll_d2_d8",
+ "syspll_d2_d16"
+};
+
+static const char * const aud_1_parents[] = {
+ "clk26m",
+ "apll1_ck"
+};
+
+static const char * const aud_2_parents[] = {
+ "clk26m",
+ "apll2_ck"
+};
+
+/*
+ * CRITICAL CLOCK:
+ * axi_sel is the main bus clock of whole SOC.
+ * spm_sel is the clock of the always-on co-processor.
+ */
+static const struct mtk_mux top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
+ axi_parents, 0x40,
+ 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
+ mm_parents, 0x40,
+ 0x44, 0x48, 8, 3, 15, 0x004, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
+ img_parents, 0x40,
+ 0x44, 0x48, 16, 3, 23, 0x004, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
+ cam_parents, 0x40,
+ 0x44, 0x48, 24, 4, 31, 0x004, 3),
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
+ dsp_parents, 0x50,
+ 0x54, 0x58, 0, 4, 7, 0x004, 4),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
+ dsp1_parents, 0x50,
+ 0x54, 0x58, 8, 4, 15, 0x004, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
+ dsp2_parents, 0x50,
+ 0x54, 0x58, 16, 4, 23, 0x004, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
+ ipu_if_parents, 0x50,
+ 0x54, 0x58, 24, 4, 31, 0x004, 7),
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
+ mfg_parents, 0x60,
+ 0x64, 0x68, 0, 2, 7, 0x004, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
+ f52m_mfg_parents, 0x60,
+ 0x64, 0x68, 8, 2, 15, 0x004, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
+ camtg_parents, 0x60,
+ 0x64, 0x68, 16, 3, 23, 0x004, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
+ camtg2_parents, 0x60,
+ 0x64, 0x68, 24, 3, 31, 0x004, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
+ camtg3_parents, 0x70,
+ 0x74, 0x78, 0, 3, 7, 0x004, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
+ camtg4_parents, 0x70,
+ 0x74, 0x78, 8, 3, 15, 0x004, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
+ uart_parents, 0x70,
+ 0x74, 0x78, 16, 1, 23, 0x004, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
+ spi_parents, 0x70,
+ 0x74, 0x78, 24, 2, 31, 0x004, 15),
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
+ msdc50_hclk_parents, 0x80,
+ 0x84, 0x88, 0, 2, 7, 0x004, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
+ msdc50_0_parents, 0x80,
+ 0x84, 0x88, 8, 3, 15, 0x004, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
+ msdc30_1_parents, 0x80,
+ 0x84, 0x88, 16, 3, 23, 0x004, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
+ msdc30_2_parents, 0x80,
+ 0x84, 0x88, 24, 3, 31, 0x004, 19),
+ /* CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
+ audio_parents, 0x90,
+ 0x94, 0x98, 0, 2, 7, 0x004, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
+ aud_intbus_parents, 0x90,
+ 0x94, 0x98, 8, 2, 15, 0x004, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
+ pmicspi_parents, 0x90,
+ 0x94, 0x98, 16, 2, 23, 0x004, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
+ fpwrap_ulposc_parents, 0x90,
+ 0x94, 0x98, 24, 2, 31, 0x004, 23),
+ /* CLK_CFG_6 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
+ atb_parents, 0xa0,
+ 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSPM, "sspm_sel",
+ sspm_parents, 0xa0,
+ 0xa4, 0xa8, 8, 3, 15, 0x004, 25),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
+ dpi0_parents, 0xa0,
+ 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
+ scam_parents, 0xa0,
+ 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
+ disppwm_parents, 0xb0,
+ 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
+ usb_top_parents, 0xb0,
+ 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
+ ssusb_top_xhci_parents, 0xb0,
+ 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
+ spm_parents, 0xb0,
+ 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
+ i2c_parents, 0xc0,
+ 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
+ scp_parents, 0xc0,
+ 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
+ seninf_parents, 0xc0,
+ 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
+ dxcc_parents, 0xc0,
+ 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
+ /* CLK_CFG_9 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
+ aud_engen1_parents, 0xd0,
+ 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
+ aud_engen2_parents, 0xd0,
+ 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
+ faes_ufsfde_parents, 0xd0,
+ 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
+ fufs_parents, 0xd0,
+ 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
+ /* CLK_CFG_10 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
+ aud_1_parents, 0xe0,
+ 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
+ aud_2_parents, 0xe0,
+ 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
+};
+
+static const char * const apll_i2s0_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s1_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s2_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s3_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s4_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const apll_i2s5_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static struct mtk_composite top_aud_muxes[] = {
+ MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
+ 0x320, 8, 1),
+ MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
+ 0x320, 9, 1),
+ MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
+ 0x320, 10, 1),
+ MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
+ 0x320, 11, 1),
+ MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
+ 0x320, 12, 1),
+ MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
+ 0x328, 20, 1),
+};
+
+static const char * const mcu_mp0_parents[] = {
+ "clk26m",
+ "armpll_ll",
+ "armpll_div_pll1",
+ "armpll_div_pll2"
+};
+
+static const char * const mcu_mp2_parents[] = {
+ "clk26m",
+ "armpll_l",
+ "armpll_div_pll1",
+ "armpll_div_pll2"
+};
+
+static const char * const mcu_bus_parents[] = {
+ "clk26m",
+ "ccipll",
+ "armpll_div_pll1",
+ "armpll_div_pll2"
+};
+
+static struct mtk_composite mcu_muxes[] = {
+ /* mp0_pll_divider_cfg */
+ MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
+ /* mp2_pll_divider_cfg */
+ MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
+ /* bus_pll_divider_cfg */
+ MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
+};
+
+static struct mtk_composite top_aud_divs[] = {
+ DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
+ 0x320, 2, 0x324, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
+ 0x320, 3, 0x324, 8, 8),
+ DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel",
+ 0x320, 4, 0x324, 8, 16),
+ DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel",
+ 0x320, 5, 0x324, 8, 24),
+ DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
+ 0x320, 6, 0x328, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
+ 0x320, 7, 0x328, 8, 8),
+};
+
+static const struct mtk_gate_regs top_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x104,
+ .sta_ofs = 0x104,
+};
+
+#define GATE_TOP(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP */
+ GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
+ GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+#define GATE_INFRA0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA3(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate infra_clks[] = {
+ /* INFRA0 */
+ GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
+ "axi_sel", 0),
+ GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
+ "axi_sel", 1),
+ GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
+ "axi_sel", 2),
+ GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
+ "axi_sel", 3),
+ GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
+ "scp_sel", 4),
+ GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
+ "f_f26m_ck", 5),
+ GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
+ "axi_sel", 6),
+ GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
+ "axi_sel", 8),
+ GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
+ "axi_sel", 9),
+ GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
+ "axi_sel", 10),
+ GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
+ "i2c_sel", 11),
+ GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
+ "i2c_sel", 12),
+ GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
+ "i2c_sel", 13),
+ GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
+ "i2c_sel", 14),
+ GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
+ "axi_sel", 15),
+ GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
+ "i2c_sel", 16),
+ GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
+ "i2c_sel", 17),
+ GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
+ "i2c_sel", 18),
+ GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
+ "i2c_sel", 19),
+ GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
+ "i2c_sel", 21),
+ GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+ "uart_sel", 22),
+ GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
+ "uart_sel", 23),
+ GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
+ "uart_sel", 24),
+ GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
+ "uart_sel", 25),
+ GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
+ "axi_sel", 27),
+ GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
+ "axi_sel", 28),
+ GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
+ "axi_sel", 31),
+ /* INFRA1 */
+ GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
+ "spi_sel", 1),
+ GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
+ "msdc50_hclk_sel", 2),
+ GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
+ "axi_sel", 4),
+ GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
+ "axi_sel", 5),
+ GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
+ "msdc50_0_sel", 6),
+ GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
+ "f_f26m_ck", 7),
+ GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
+ "axi_sel", 8),
+ GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
+ "axi_sel", 9),
+ GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
+ "f_f26m_ck", 10),
+ GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
+ "axi_sel", 11),
+ GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
+ "axi_sel", 12),
+ GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
+ "axi_sel", 13),
+ GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
+ "f_f26m_ck", 14),
+ GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
+ "msdc30_1_sel", 16),
+ GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
+ "msdc30_2_sel", 17),
+ GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
+ "axi_sel", 18),
+ GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
+ "axi_sel", 19),
+ GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
+ "axi_sel", 20),
+ GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
+ "axi_sel", 23),
+ GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
+ "axi_sel", 24),
+ GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio",
+ "axi_sel", 25),
+ GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
+ "axi_sel", 26),
+ GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
+ "dxcc_sel", 27),
+ GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
+ "dxcc_sel", 28),
+ GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
+ "axi_sel", 30),
+ GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+ "f_f26m_ck", 31),
+ /* INFRA2 */
+ GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
+ "f_f26m_ck", 0),
+ GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
+ "usb_top_sel", 1),
+ GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
+ "axi_sel", 2),
+ GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk",
+ "axi_sel", 3),
+ GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk",
+ "f_f26m_ck", 4),
+ GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
+ "spi_sel", 6),
+ GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
+ "i2c_sel", 7),
+ GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
+ "f_f26m_ck", 8),
+ GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
+ "spi_sel", 9),
+ GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
+ "spi_sel", 10),
+ GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
+ "ssusb_top_xhci_sel", 11),
+ GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
+ "fufs_sel", 12),
+ GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
+ "fufs_sel", 13),
+ GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
+ "axi_sel", 14),
+ GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm",
+ "sspm_sel", 15),
+ GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
+ "axi_sel", 16),
+ GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
+ "axi_sel", 17),
+ GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
+ "i2c_sel", 18),
+ GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
+ "i2c_sel", 19),
+ GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
+ "i2c_sel", 20),
+ GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
+ "i2c_sel", 21),
+ GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
+ "i2c_sel", 22),
+ GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
+ "i2c_sel", 23),
+ GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
+ "i2c_sel", 24),
+ GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
+ "spi_sel", 25),
+ GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
+ "spi_sel", 26),
+ GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
+ "axi_sel", 27),
+ GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
+ "fufs_sel", 28),
+ GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
+ "faes_ufsfde_sel", 29),
+ GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
+ "fufs_sel", 30),
+ /* INFRA3 */
+ GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
+ "msdc50_0_sel", 0),
+ GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
+ "msdc50_0_sel", 1),
+ GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
+ "msdc50_0_sel", 2),
+ GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
+ "f_f26m_ck", 3),
+ GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
+ "f_f26m_ck", 4),
+ GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
+ "axi_sel", 5),
+ GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
+ "i2c_sel", 6),
+ GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
+ "msdc50_hclk_sel", 7),
+ GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
+ "msdc50_hclk_sel", 8),
+ GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
+ "axi_sel", 16),
+ GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
+ "axi_sel", 17),
+ GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
+ "axi_sel", 18),
+ GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
+ "axi_sel", 19),
+ GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
+ "f_f26m_ck", 20),
+ GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
+ "axi_sel", 21),
+ GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
+ "i2c_sel", 22),
+ GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
+ "i2c_sel", 23),
+ GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
+ "msdc50_0_sel", 24),
+};
+
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x20,
+ .clr_ofs = 0x20,
+ .sta_ofs = 0x20,
+};
+
+#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
+ _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
+
+#define GATE_APMIXED(_id, _name, _parent, _shift) \
+ GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
+
+/*
+ * CRITICAL CLOCK:
+ * apmixed_appll26m is the toppest clock gate of all PLLs.
+ */
+static const struct mtk_gate apmixed_clks[] = {
+ /* AUDIO0 */
+ GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
+ "f_f26m_ck", 4),
+ GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
+ "f_f26m_ck", 5, CLK_IS_CRITICAL),
+ GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
+ "f_f26m_ck", 6),
+ GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
+ "f_f26m_ck", 7),
+ GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
+ "f_f26m_ck", 8),
+ GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
+ "f_f26m_ck", 9),
+ GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
+ "f_f26m_ck", 11),
+ GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
+ "f_f26m_ck", 13),
+ GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
+ "f_f26m_ck", 14),
+ GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
+ "f_f26m_ck", 16),
+ GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
+ "f_f26m_ck", 17),
+};
+
+#define MT8183_PLL_FMAX (3800UL * MHZ)
+#define MT8183_PLL_FMIN (1500UL * MHZ)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcw_chg_reg, _div_table) { \
+ .id = _id, \
+ .name = _name, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .flags = _flags, \
+ .rst_bar_mask = _rst_bar_mask, \
+ .fmax = MT8183_PLL_FMAX, \
+ .fmin = MT8183_PLL_FMIN, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = _pcwibits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _pcw_chg_reg, \
+ .div_table = _div_table, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcw_chg_reg) \
+ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
+ _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcw_chg_reg, NULL)
+
+static const struct mtk_pll_div_table armpll_div_table[] = {
+ { .div = 0, .freq = MT8183_PLL_FMAX },
+ { .div = 1, .freq = 1500 * MHZ },
+ { .div = 2, .freq = 750 * MHZ },
+ { .div = 3, .freq = 375 * MHZ },
+ { .div = 4, .freq = 187500000 },
+ { } /* sentinel */
+};
+
+static const struct mtk_pll_div_table mfgpll_div_table[] = {
+ { .div = 0, .freq = MT8183_PLL_FMAX },
+ { .div = 1, .freq = 1600 * MHZ },
+ { .div = 2, .freq = 800 * MHZ },
+ { .div = 3, .freq = 400 * MHZ },
+ { .div = 4, .freq = 200 * MHZ },
+ { } /* sentinel */
+};
+
+static const struct mtk_pll_data plls[] = {
+ PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
+ HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
+ 0x0204, 0, 0, armpll_div_table),
+ PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
+ HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
+ 0x0214, 0, 0, armpll_div_table),
+ PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
+ HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
+ 0x0294, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
+ HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
+ 0x0224, 0, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
+ HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
+ 0x0234, 0, 0),
+ PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
+ 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
+ mfgpll_div_table),
+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
+ 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
+ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
+ 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
+ HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
+ 0x0274, 0, 0),
+ PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
+ 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
+ PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
+ 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
+};
+
+static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int clk_mt8183_top_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ void __iomem *base;
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ clk_data);
+
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+
+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
+ node, &mt8183_clk_lock, clk_data);
+
+ mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
+ base, &mt8183_clk_lock, clk_data);
+
+ mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
+ base, &mt8183_clk_lock, clk_data);
+
+ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int clk_mt8183_infra_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static int clk_mt8183_mcu_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+
+ mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
+ &mt8183_clk_lock, clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8183[] = {
+ {
+ .compatible = "mediatek,mt8183-apmixedsys",
+ .data = clk_mt8183_apmixed_probe,
+ }, {
+ .compatible = "mediatek,mt8183-topckgen",
+ .data = clk_mt8183_top_probe,
+ }, {
+ .compatible = "mediatek,mt8183-infracfg",
+ .data = clk_mt8183_infra_probe,
+ }, {
+ .compatible = "mediatek,mt8183-mcucfg",
+ .data = clk_mt8183_mcu_probe,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt8183_probe(struct platform_device *pdev)
+{
+ int (*clk_probe)(struct platform_device *pdev);
+ int r;
+
+ clk_probe = of_device_get_match_data(&pdev->dev);
+ if (!clk_probe)
+ return -EINVAL;
+
+ r = clk_probe(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt8183_drv = {
+ .probe = clk_mt8183_probe,
+ .driver = {
+ .name = "clk-mt8183",
+ .of_match_table = of_match_clk_mt8183,
+ },
+};
+
+static int __init clk_mt8183_init(void)
+{
+ return platform_driver_register(&clk_mt8183_drv);
+}
+
+arch_initcall(clk_mt8183_init);
--
2.18.0
On some Mediatek platforms, there are critical clocks of
clock gate type.
To register clock gate with flags CLK_IS_CRITICAL,
we need to add the flags field in mtk_gate data and register APIs.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/clk-gate.c | 5 +++--
drivers/clk/mediatek/clk-gate.h | 3 ++-
drivers/clk/mediatek/clk-mtk.c | 3 ++-
drivers/clk/mediatek/clk-mtk.h | 1 +
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 934bf0e45e26..85daf826619a 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
int clr_ofs,
int sta_ofs,
u8 bit,
- const struct clk_ops *ops)
+ const struct clk_ops *ops,
+ unsigned long flags)
{
struct mtk_clk_gate *cg;
struct clk *clk;
@@ -168,7 +169,7 @@ struct clk *mtk_clk_register_gate(
return ERR_PTR(-ENOMEM);
init.name = name;
- init.flags = CLK_SET_RATE_PARENT;
+ init.flags = flags | CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
init.ops = ops;
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 72ef89b3ad7b..9f766dfe1d57 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
int clr_ofs,
int sta_ofs,
u8 bit,
- const struct clk_ops *ops);
+ const struct clk_ops *ops,
+ unsigned long flags);
#endif /* __DRV_CLK_GATE_H */
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 9c0ae4278a94..35359e5397c7 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -130,7 +130,8 @@ int mtk_clk_register_gates(struct device_node *node,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
- gate->shift, gate->ops);
+ gate->shift, gate->ops,
+ gate->flags);
if (IS_ERR(clk)) {
pr_err("Failed to register clk %s: %ld\n",
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 11b5517903d0..928905496c4b 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -158,6 +158,7 @@ struct mtk_gate {
const struct mtk_gate_regs *regs;
int shift;
const struct clk_ops *ops;
+ unsigned long flags;
};
int mtk_clk_register_gates(struct device_node *node,
--
2.18.0
From: James Liao <[email protected]>
Some modules may need to change its clock rate before turn on it.
So changing PLL's rate when it is off should be allowed.
This patch removes PLL enabled check before set rate, so that
PLLs can set new frequency even if they are off.
On MT8173 for example, ARMPLL's enable bit can be controlled by
other HW. That means ARMPLL may be turned on even if we (CPU / SW)
set ARMPLL's enable bit as 0. In this case, SW may want and can
still change ARMPLL's rate by changing its pcw and postdiv settings.
But without this patch, new pcw setting will not be applied because
its enable bit is 0.
Signed-off-by: James Liao <[email protected]>
Acked-by: Michael Turquette <[email protected]>
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/clk-pll.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 65cee1d6c400..8d556fc99fed 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
int postdiv)
{
u32 chg, val;
- int pll_en;
-
- pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
/* disable tuner */
__mtk_pll_tuner_disable(pll);
@@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
pll->data->pcw_shift);
val |= pcw << pll->data->pcw_shift;
writel(val, pll->pcw_addr);
-
- chg = readl(pll->pcw_chg_addr);
-
- if (pll_en)
- chg |= PCW_CHG_MASK;
-
+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
writel(chg, pll->pcw_chg_addr);
if (pll->tuner_addr)
writel(val + 1, pll->tuner_addr);
@@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
/* restore tuner_en */
__mtk_pll_tuner_enable(pll);
- if (pll_en)
- udelay(20);
+ udelay(20);
}
/*
--
2.18.0
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: Owen Chen <[email protected]>
>
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
>
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <[email protected]>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: James Liao <[email protected]>
> ---
> drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++----------
> 1 file changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index f54e4015b0b1..18842d660317 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
> return ((unsigned long)vco + postdiv - 1) / postdiv;
> }
>
> +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
> +{
> + u32 r;
> +
> + if (pll->tuner_en_addr) {
> + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> + writel(r, pll->tuner_en_addr);
> + } else if (pll->tuner_addr) {
> + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> + writel(r, pll->tuner_addr);
> + }
> +}
> +
> +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
> +{
> + u32 r;
> +
> + if (pll->tuner_en_addr) {
> + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> + writel(r, pll->tuner_en_addr);
> + } else if (pll->tuner_addr) {
> + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> + writel(r, pll->tuner_addr);
> + }
> +}
> +
> static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> int postdiv)
> {
> @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>
> pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>
> + /* disable tuner */
> + __mtk_pll_tuner_disable(pll);
> +
> /* set postdiv */
> val = readl(pll->pd_addr);
> val &= ~(POSTDIV_MASK << pll->data->pd_shift);
> @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> if (pll->tuner_addr)
> writel(con1 + 1, pll->tuner_addr);
>
> + /* restore tuner_en */
> + __mtk_pll_tuner_enable(pll);
> +
> if (pll_en)
> udelay(20);
> }
> @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> r |= pll->data->en_mask;
> writel(r, pll->base_addr + REG_CON0);
>
> - if (pll->tuner_en_addr) {
> - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> - writel(r, pll->tuner_en_addr);
> - } else if (pll->tuner_addr) {
> - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> - writel(r, pll->tuner_addr);
> - }
> + __mtk_pll_tuner_enable(pll);
>
> udelay(20);
>
> @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
> writel(r, pll->base_addr + REG_CON0);
> }
>
> - if (pll->tuner_en_addr) {
> - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> - writel(r, pll->tuner_en_addr);
> - } else if (pll->tuner_addr) {
> - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> - writel(r, pll->tuner_addr);
> - }
> + __mtk_pll_tuner_disable(pll);
>
> r = readl(pll->base_addr + REG_CON0);
> r &= ~CON0_BASE_EN;
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: Owen Chen <[email protected]>
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new API to handle this hw change with
> a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: James Liao <[email protected]>
> ---
> drivers/clk/mediatek/Makefile | 3 +-
> drivers/clk/mediatek/clk-mux.c | 223 +++++++++++++++++++++++++++++++++
> drivers/clk/mediatek/clk-mux.h | 89 +++++++++++++
> 3 files changed, 314 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mux.c
> create mode 100644 drivers/clk/mediatek/clk-mux.h
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index ee4410ff43ab..20cf9eea4171 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
> +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
> +
> obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
> obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
> obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
> diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
> new file mode 100644
> index 000000000000..877a883fa616
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mux.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <[email protected]>
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/mfd/syscon.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
> +{
> + return container_of(hw, struct mtk_clk_mux, hw);
> +}
> +
> +static int mtk_clk_mux_enable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
> + mask, ~mask);
> +}
> +
> +static void mtk_clk_mux_disable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
> +}
> +
> +static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + return regmap_write(mux->regmap, mux->data->clr_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + regmap_write(mux->regmap, mux->data->set_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &val);
> +
> + return (val & BIT(mux->data->gate_shift)) == 0;
> +}
> +
> +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &val);
> + val = (val >> mux->data->mux_shift) & mask;
> +
> + return val;
> +}
> +
> +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + unsigned long flags;
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
> + index << mux->data->mux_shift);
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return 0;
> +}
> +
> +static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + u32 val, orig;
> + unsigned long flags;
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
> + val = (orig & ~(mask << mux->data->mux_shift))
> + | (index << mux->data->mux_shift);
> +
> + if (val != orig) {
> + regmap_write(mux->regmap, mux->data->clr_ofs,
> + mask << mux->data->mux_shift);
> + regmap_write(mux->regmap, mux->data->set_ofs,
> + index << mux->data->mux_shift);
> +
> + if (mux->data->upd_shift >= 0)
> + regmap_write(mux->regmap, mux->data->upd_ofs,
> + BIT(mux->data->upd_shift));
> + }
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return 0;
> +}
> +
> +const struct clk_ops mtk_mux_ops = {
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_lock,
> +};
> +
> +const struct clk_ops mtk_mux_clr_set_upd_ops = {
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> +};
> +
> +const struct clk_ops mtk_mux_gate_ops = {
> + .enable = mtk_clk_mux_enable,
> + .disable = mtk_clk_mux_disable,
> + .is_enabled = mtk_clk_mux_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_lock,
> +};
> +
> +const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
> + .enable = mtk_clk_mux_enable_setclr,
> + .disable = mtk_clk_mux_disable_setclr,
> + .is_enabled = mtk_clk_mux_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> +};
> +
> +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> + struct regmap *regmap,
> + spinlock_t *lock)
> +{
> + struct mtk_clk_mux *clk_mux;
> + struct clk_init_data init;
> + struct clk *clk;
> +
> + clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
> + if (!clk_mux)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = mux->name;
> + init.flags = mux->flags | CLK_SET_RATE_PARENT;
> + init.parent_names = mux->parent_names;
> + init.num_parents = mux->num_parents;
> + init.ops = mux->ops;
> +
> + clk_mux->regmap = regmap;
> + clk_mux->data = mux;
> + clk_mux->lock = lock;
> + clk_mux->hw.init = &init;
> +
> + clk = clk_register(NULL, &clk_mux->hw);
> + if (IS_ERR(clk)) {
> + kfree(clk_mux);
> + return clk;
> + }
> +
> + return clk;
> +}
> +
> +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> + int num, struct device_node *node,
> + spinlock_t *lock,
> + struct clk_onecell_data *clk_data)
> +{
> + struct regmap *regmap;
> + struct clk *clk;
> + int i;
> +
> + regmap = syscon_node_to_regmap(node);
> + if (IS_ERR(regmap)) {
> + pr_err("Cannot find regmap for %pOF: %ld\n", node,
> + PTR_ERR(regmap));
> + return PTR_ERR(regmap);
> + }
> +
> + for (i = 0; i < num; i++) {
> + const struct mtk_mux *mux = &muxes[i];
> +
> + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
> + clk = mtk_clk_register_mux(mux, regmap, lock);
> +
> + if (IS_ERR(clk)) {
> + pr_err("Failed to register clk %s: %ld\n",
> + mux->name, PTR_ERR(clk));
> + continue;
> + }
> +
> + clk_data->clks[mux->id] = clk;
> + }
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> new file mode 100644
> index 000000000000..f5625f4d9e6c
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mux.h
> @@ -0,0 +1,89 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <[email protected]>
> + */
> +
> +#ifndef __DRV_CLK_MTK_MUX_H
> +#define __DRV_CLK_MTK_MUX_H
> +
> +#include <linux/clk-provider.h>
> +
> +struct mtk_clk_mux {
> + struct clk_hw hw;
> + struct regmap *regmap;
> + const struct mtk_mux *data;
> + spinlock_t *lock;
> +};
> +
> +struct mtk_mux {
> + int id;
> + const char *name;
> + const char * const *parent_names;
> + unsigned int flags;
> +
> + u32 mux_ofs;
> + u32 set_ofs;
> + u32 clr_ofs;
> + u32 upd_ofs;
> +
> + u8 mux_shift;
> + u8 mux_width;
> + u8 gate_shift;
> + s8 upd_shift;
> +
> + const struct clk_ops *ops;
> +
> + signed char num_parents;
> +};
> +
> +extern const struct clk_ops mtk_mux_ops;
> +extern const struct clk_ops mtk_mux_clr_set_upd_ops;
> +extern const struct clk_ops mtk_mux_gate_ops;
> +extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
> +
> +#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags, _ops) { \
> + .id = _id, \
> + .name = _name, \
> + .mux_ofs = _mux_ofs, \
> + .set_ofs = _mux_set_ofs, \
> + .clr_ofs = _mux_clr_ofs, \
> + .upd_ofs = _upd_ofs, \
> + .mux_shift = _shift, \
> + .mux_width = _width, \
> + .gate_shift = _gate, \
> + .upd_shift = _upd, \
> + .parent_names = _parents, \
> + .num_parents = ARRAY_SIZE(_parents), \
> + .flags = _flags, \
> + .ops = &_ops, \
> + }
> +
> +#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags) \
> + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags, \
> + mtk_mux_gate_clr_set_upd_ops)
> +
> +#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd) \
> + MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
> + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
> + _width, _gate, _upd_ofs, _upd, \
> + CLK_SET_RATE_PARENT)
> +
> +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> + struct regmap *regmap,
> + spinlock_t *lock);
> +
> +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> + int num, struct device_node *node,
> + spinlock_t *lock,
> + struct clk_onecell_data *clk_data);
> +
> +#endif /* __DRV_CLK_MTK_MUX_H */
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> On some Mediatek platforms, there are critical clocks of
> clock gate type.
> To register clock gate with flags CLK_IS_CRITICAL,
> we need to add the flags field in mtk_gate data and register APIs.
>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: James Liao <[email protected]>
> ---
> drivers/clk/mediatek/clk-gate.c | 5 +++--
> drivers/clk/mediatek/clk-gate.h | 3 ++-
> drivers/clk/mediatek/clk-mtk.c | 3 ++-
> drivers/clk/mediatek/clk-mtk.h | 1 +
> 4 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> index 934bf0e45e26..85daf826619a 100644
> --- a/drivers/clk/mediatek/clk-gate.c
> +++ b/drivers/clk/mediatek/clk-gate.c
> @@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
> int clr_ofs,
> int sta_ofs,
> u8 bit,
> - const struct clk_ops *ops)
> + const struct clk_ops *ops,
> + unsigned long flags)
> {
> struct mtk_clk_gate *cg;
> struct clk *clk;
> @@ -168,7 +169,7 @@ struct clk *mtk_clk_register_gate(
> return ERR_PTR(-ENOMEM);
>
> init.name = name;
> - init.flags = CLK_SET_RATE_PARENT;
> + init.flags = flags | CLK_SET_RATE_PARENT;
> init.parent_names = parent_name ? &parent_name : NULL;
> init.num_parents = parent_name ? 1 : 0;
> init.ops = ops;
> diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
> index 72ef89b3ad7b..9f766dfe1d57 100644
> --- a/drivers/clk/mediatek/clk-gate.h
> +++ b/drivers/clk/mediatek/clk-gate.h
> @@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
> int clr_ofs,
> int sta_ofs,
> u8 bit,
> - const struct clk_ops *ops);
> + const struct clk_ops *ops,
> + unsigned long flags);
>
> #endif /* __DRV_CLK_GATE_H */
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index 9c0ae4278a94..35359e5397c7 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -130,7 +130,8 @@ int mtk_clk_register_gates(struct device_node *node,
> gate->regs->set_ofs,
> gate->regs->clr_ofs,
> gate->regs->sta_ofs,
> - gate->shift, gate->ops);
> + gate->shift, gate->ops,
> + gate->flags);
>
> if (IS_ERR(clk)) {
> pr_err("Failed to register clk %s: %ld\n",
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 11b5517903d0..928905496c4b 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -158,6 +158,7 @@ struct mtk_gate {
> const struct mtk_gate_regs *regs;
> int shift;
> const struct clk_ops *ops;
> + unsigned long flags;
> };
>
> int mtk_clk_register_gates(struct device_node *node,
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> In previous MediaTek PLL design, it assumes the pcw change control
> is always on the CON1 register.
> However, the pcw change bit on MT8183 was moved onto CON0 because
> the the PCW length of audio PLLs are extended to 32-bit.
> Add configurable pcw_chg_reg to set the pcw change control register
> address or using the default control register CON1 if without
> setting in pll data.
>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: James Liao <[email protected]>
> ---
> drivers/clk/mediatek/clk-mtk.h | 1 +
> drivers/clk/mediatek/clk-pll.c | 17 +++++++++++------
> 2 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 928905496c4b..37ae944548e9 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -221,6 +221,7 @@ struct mtk_pll_data {
> int pcwibits;
> uint32_t pcw_reg;
> int pcw_shift;
> + uint32_t pcw_chg_reg;
> const struct mtk_pll_div_table *div_table;
> const char *parent_name;
> };
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 67aaa3082d9b..65cee1d6c400 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -27,7 +27,7 @@
> #define CON0_BASE_EN BIT(0)
> #define CON0_PWR_ON BIT(0)
> #define CON0_ISO_EN BIT(1)
> -#define CON0_PCW_CHG BIT(31)
> +#define PCW_CHG_MASK BIT(31)
>
> #define AUDPLL_TUNER_EN BIT(31)
>
> @@ -51,6 +51,7 @@ struct mtk_clk_pll {
> void __iomem *tuner_addr;
> void __iomem *tuner_en_addr;
> void __iomem *pcw_addr;
> + void __iomem *pcw_chg_addr;
> const struct mtk_pll_data *data;
> };
>
> @@ -122,7 +123,7 @@ static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
> static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> int postdiv)
> {
> - u32 con1, val;
> + u32 chg, val;
> int pll_en;
>
> pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
> @@ -147,14 +148,14 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> val |= pcw << pll->data->pcw_shift;
> writel(val, pll->pcw_addr);
>
> - con1 = readl(pll->base_addr + REG_CON1);
> + chg = readl(pll->pcw_chg_addr);
>
> if (pll_en)
> - con1 |= CON0_PCW_CHG;
> + chg |= PCW_CHG_MASK;
>
> - writel(con1, pll->base_addr + REG_CON1);
> + writel(chg, pll->pcw_chg_addr);
> if (pll->tuner_addr)
> - writel(con1 + 1, pll->tuner_addr);
> + writel(val + 1, pll->tuner_addr);
>
> /* restore tuner_en */
> __mtk_pll_tuner_enable(pll);
> @@ -329,6 +330,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
> pll->pwr_addr = base + data->pwr_reg;
> pll->pd_addr = base + data->pd_reg;
> pll->pcw_addr = base + data->pcw_reg;
> + if (data->pcw_chg_reg)
> + pll->pcw_chg_addr = base + data->pcw_chg_reg;
> + else
> + pll->pcw_chg_addr = pll->base_addr + REG_CON1;
> if (data->tuner_reg)
> pll->tuner_addr = base + data->tuner_reg;
> if (data->tuner_en_reg)
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: Owen Chen <[email protected]>
>
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> add a variable to indicate this change and
> backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
> 1.5Ghz, add a variable to indicate platform-dependent.
>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
> Acked-by: Sean Wang <[email protected]>
Reviewed-by: James Liao <[email protected]>
> ---
> drivers/clk/mediatek/clk-mtk.h | 2 ++
> drivers/clk/mediatek/clk-pll.c | 15 +++++++++++----
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index f83c2bbb677e..11b5517903d0 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -214,8 +214,10 @@ struct mtk_pll_data {
> unsigned int flags;
> const struct clk_ops *ops;
> u32 rst_bar_mask;
> + unsigned long fmin;
> unsigned long fmax;
> int pcwbits;
> + int pcwibits;
> uint32_t pcw_reg;
> int pcw_shift;
> const struct mtk_pll_div_table *div_table;
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 18842d660317..67aaa3082d9b 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -32,6 +32,8 @@
> #define AUDPLL_TUNER_EN BIT(31)
>
> #define POSTDIV_MASK 0x7
> +
> +/* default 7 bits integer, can be overridden with pcwibits. */
> #define INTEGER_BITS 7
>
> /*
> @@ -68,12 +70,15 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
> u32 pcw, int postdiv)
> {
> int pcwbits = pll->data->pcwbits;
> - int pcwfbits;
> + int pcwfbits = 0;
> + int ibits;
> u64 vco;
> u8 c = 0;
>
> /* The fractional part of the PLL divider. */
> - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
> + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> + if (pcwbits > ibits)
> + pcwfbits = pcwbits - ibits;
>
> vco = (u64)fin * pcw;
>
> @@ -170,9 +175,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> u32 freq, u32 fin)
> {
> - unsigned long fmin = 1000 * MHZ;
> + unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
> const struct mtk_pll_div_table *div_table = pll->data->div_table;
> u64 _pcw;
> + int ibits;
> u32 val;
>
> if (freq > pll->data->fmax)
> @@ -196,7 +202,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> }
>
> /* _pcw = freq * postdiv / fin * 2^pcwfbits */
> - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
> + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
> do_div(_pcw, fin);
>
> *pcw = (u32)_pcw;
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
> From: James Liao <[email protected]>
>
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
>
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
>
> Signed-off-by: James Liao <[email protected]>
> Acked-by: Michael Turquette <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: James Liao <[email protected]>
> ---
> drivers/clk/mediatek/clk-pll.c | 13 ++-----------
> 1 file changed, 2 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 65cee1d6c400..8d556fc99fed 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> int postdiv)
> {
> u32 chg, val;
> - int pll_en;
> -
> - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>
> /* disable tuner */
> __mtk_pll_tuner_disable(pll);
> @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> pll->data->pcw_shift);
> val |= pcw << pll->data->pcw_shift;
> writel(val, pll->pcw_addr);
> -
> - chg = readl(pll->pcw_chg_addr);
> -
> - if (pll_en)
> - chg |= PCW_CHG_MASK;
> -
> + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
> writel(chg, pll->pcw_chg_addr);
> if (pll->tuner_addr)
> writel(val + 1, pll->tuner_addr);
> @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> /* restore tuner_en */
> __mtk_pll_tuner_enable(pll);
>
> - if (pll_en)
> - udelay(20);
> + udelay(20);
> }
>
> /*
Quoting Weiyi Lu (2019-03-04 21:05:37)
> Resend clock patches from v4 based on v5.0-rc1.
>
Please stop sending two cover letters with the same content. Is there
something different about your git-send-email workflow that's causing
this? Hopefully git itself isn't doing this.
On 05/03/2019 06:05, Weiyi Lu wrote:
> From: Owen Chen <[email protected]>
>
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
>
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <[email protected]>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
> ---
> drivers/clk/mediatek/clk-pll.c | 48 ++++++++++++++++++++++++----------
> 1 file changed, 34 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index f54e4015b0b1..18842d660317 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
> return ((unsigned long)vco + postdiv - 1) / postdiv;
> }
>
> +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
> +{
> + u32 r;
> +
> + if (pll->tuner_en_addr) {
> + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> + writel(r, pll->tuner_en_addr);
> + } else if (pll->tuner_addr) {
> + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> + writel(r, pll->tuner_addr);
> + }
> +}
> +
> +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
> +{
> + u32 r;
> +
> + if (pll->tuner_en_addr) {
> + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> + writel(r, pll->tuner_en_addr);
> + } else if (pll->tuner_addr) {
> + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> + writel(r, pll->tuner_addr);
> + }
> +}
> +
> static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> int postdiv)
> {
> @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>
> pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
>
> + /* disable tuner */
> + __mtk_pll_tuner_disable(pll);
> +
> /* set postdiv */
> val = readl(pll->pd_addr);
> val &= ~(POSTDIV_MASK << pll->data->pd_shift);
> @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> if (pll->tuner_addr)
> writel(con1 + 1, pll->tuner_addr);
>
> + /* restore tuner_en */
> + __mtk_pll_tuner_enable(pll);
> +
> if (pll_en)
> udelay(20);
> }
> @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> r |= pll->data->en_mask;
> writel(r, pll->base_addr + REG_CON0);
>
> - if (pll->tuner_en_addr) {
> - r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
> - writel(r, pll->tuner_en_addr);
> - } else if (pll->tuner_addr) {
> - r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
> - writel(r, pll->tuner_addr);
> - }
> + __mtk_pll_tuner_enable(pll);
>
> udelay(20);
>
> @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
> writel(r, pll->base_addr + REG_CON0);
> }
>
> - if (pll->tuner_en_addr) {
> - r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
> - writel(r, pll->tuner_en_addr);
> - } else if (pll->tuner_addr) {
> - r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
> - writel(r, pll->tuner_addr);
> - }
> + __mtk_pll_tuner_disable(pll);
>
> r = readl(pll->base_addr + REG_CON0);
> r &= ~CON0_BASE_EN;
>
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <[email protected]> wrote:
>
> From: Owen Chen <[email protected]>
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new API to handle this hw change with
> a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-and-tested-by: Nicolas Boichat <[email protected]>
> ---
> drivers/clk/mediatek/Makefile | 3 +-
> drivers/clk/mediatek/clk-mux.c | 223 +++++++++++++++++++++++++++++++++
> drivers/clk/mediatek/clk-mux.h | 89 +++++++++++++
> 3 files changed, 314 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mux.c
> create mode 100644 drivers/clk/mediatek/clk-mux.h
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index ee4410ff43ab..20cf9eea4171 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
> +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
> +
> obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
> obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
> obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
> diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
> new file mode 100644
> index 000000000000..877a883fa616
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mux.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <[email protected]>
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/mfd/syscon.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
> +{
> + return container_of(hw, struct mtk_clk_mux, hw);
> +}
> +
> +static int mtk_clk_mux_enable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
> + mask, ~mask);
> +}
> +
> +static void mtk_clk_mux_disable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
> +}
> +
> +static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + return regmap_write(mux->regmap, mux->data->clr_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + regmap_write(mux->regmap, mux->data->set_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &val);
> +
> + return (val & BIT(mux->data->gate_shift)) == 0;
> +}
> +
> +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &val);
> + val = (val >> mux->data->mux_shift) & mask;
> +
> + return val;
> +}
> +
> +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + unsigned long flags;
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
> + index << mux->data->mux_shift);
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return 0;
> +}
> +
> +static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + u32 val, orig;
> + unsigned long flags;
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
> + val = (orig & ~(mask << mux->data->mux_shift))
> + | (index << mux->data->mux_shift);
> +
> + if (val != orig) {
> + regmap_write(mux->regmap, mux->data->clr_ofs,
> + mask << mux->data->mux_shift);
> + regmap_write(mux->regmap, mux->data->set_ofs,
> + index << mux->data->mux_shift);
> +
> + if (mux->data->upd_shift >= 0)
> + regmap_write(mux->regmap, mux->data->upd_ofs,
> + BIT(mux->data->upd_shift));
> + }
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return 0;
> +}
> +
> +const struct clk_ops mtk_mux_ops = {
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_lock,
> +};
> +
> +const struct clk_ops mtk_mux_clr_set_upd_ops = {
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> +};
> +
> +const struct clk_ops mtk_mux_gate_ops = {
> + .enable = mtk_clk_mux_enable,
> + .disable = mtk_clk_mux_disable,
> + .is_enabled = mtk_clk_mux_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_lock,
> +};
> +
> +const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
> + .enable = mtk_clk_mux_enable_setclr,
> + .disable = mtk_clk_mux_disable_setclr,
> + .is_enabled = mtk_clk_mux_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> +};
> +
> +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> + struct regmap *regmap,
> + spinlock_t *lock)
> +{
> + struct mtk_clk_mux *clk_mux;
> + struct clk_init_data init;
> + struct clk *clk;
> +
> + clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
> + if (!clk_mux)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = mux->name;
> + init.flags = mux->flags | CLK_SET_RATE_PARENT;
> + init.parent_names = mux->parent_names;
> + init.num_parents = mux->num_parents;
> + init.ops = mux->ops;
> +
> + clk_mux->regmap = regmap;
> + clk_mux->data = mux;
> + clk_mux->lock = lock;
> + clk_mux->hw.init = &init;
> +
> + clk = clk_register(NULL, &clk_mux->hw);
> + if (IS_ERR(clk)) {
> + kfree(clk_mux);
> + return clk;
> + }
> +
> + return clk;
> +}
> +
> +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> + int num, struct device_node *node,
> + spinlock_t *lock,
> + struct clk_onecell_data *clk_data)
> +{
> + struct regmap *regmap;
> + struct clk *clk;
> + int i;
> +
> + regmap = syscon_node_to_regmap(node);
> + if (IS_ERR(regmap)) {
> + pr_err("Cannot find regmap for %pOF: %ld\n", node,
> + PTR_ERR(regmap));
> + return PTR_ERR(regmap);
> + }
> +
> + for (i = 0; i < num; i++) {
> + const struct mtk_mux *mux = &muxes[i];
> +
> + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
> + clk = mtk_clk_register_mux(mux, regmap, lock);
> +
> + if (IS_ERR(clk)) {
> + pr_err("Failed to register clk %s: %ld\n",
> + mux->name, PTR_ERR(clk));
> + continue;
> + }
> +
> + clk_data->clks[mux->id] = clk;
> + }
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> new file mode 100644
> index 000000000000..f5625f4d9e6c
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mux.h
> @@ -0,0 +1,89 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <[email protected]>
> + */
> +
> +#ifndef __DRV_CLK_MTK_MUX_H
> +#define __DRV_CLK_MTK_MUX_H
> +
> +#include <linux/clk-provider.h>
> +
> +struct mtk_clk_mux {
> + struct clk_hw hw;
> + struct regmap *regmap;
> + const struct mtk_mux *data;
> + spinlock_t *lock;
> +};
> +
> +struct mtk_mux {
> + int id;
> + const char *name;
> + const char * const *parent_names;
> + unsigned int flags;
> +
> + u32 mux_ofs;
> + u32 set_ofs;
> + u32 clr_ofs;
> + u32 upd_ofs;
> +
> + u8 mux_shift;
> + u8 mux_width;
> + u8 gate_shift;
> + s8 upd_shift;
> +
> + const struct clk_ops *ops;
> +
> + signed char num_parents;
> +};
> +
> +extern const struct clk_ops mtk_mux_ops;
> +extern const struct clk_ops mtk_mux_clr_set_upd_ops;
> +extern const struct clk_ops mtk_mux_gate_ops;
> +extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
> +
> +#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags, _ops) { \
> + .id = _id, \
> + .name = _name, \
> + .mux_ofs = _mux_ofs, \
> + .set_ofs = _mux_set_ofs, \
> + .clr_ofs = _mux_clr_ofs, \
> + .upd_ofs = _upd_ofs, \
> + .mux_shift = _shift, \
> + .mux_width = _width, \
> + .gate_shift = _gate, \
> + .upd_shift = _upd, \
> + .parent_names = _parents, \
> + .num_parents = ARRAY_SIZE(_parents), \
> + .flags = _flags, \
> + .ops = &_ops, \
> + }
> +
> +#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags) \
> + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags, \
> + mtk_mux_gate_clr_set_upd_ops)
> +
> +#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd) \
> + MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
> + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
> + _width, _gate, _upd_ofs, _upd, \
> + CLK_SET_RATE_PARENT)
> +
> +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> + struct regmap *regmap,
> + spinlock_t *lock);
> +
> +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> + int num, struct device_node *node,
> + spinlock_t *lock,
> + struct clk_onecell_data *clk_data);
> +
> +#endif /* __DRV_CLK_MTK_MUX_H */
> --
> 2.18.0
>
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <[email protected]> wrote:
>
> From: Owen Chen <[email protected]>
>
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> add a variable to indicate this change and
> backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
Minor nit: frequency (Stephen I guess you could fix that when applying...)
> 1.5Ghz, add a variable to indicate platform-dependent.
>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
> Acked-by: Sean Wang <[email protected]>
Reviewed-and-tested-by: Nicolas Boichat <[email protected]>
> ---
> drivers/clk/mediatek/clk-mtk.h | 2 ++
> drivers/clk/mediatek/clk-pll.c | 15 +++++++++++----
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index f83c2bbb677e..11b5517903d0 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -214,8 +214,10 @@ struct mtk_pll_data {
> unsigned int flags;
> const struct clk_ops *ops;
> u32 rst_bar_mask;
> + unsigned long fmin;
> unsigned long fmax;
> int pcwbits;
> + int pcwibits;
> uint32_t pcw_reg;
> int pcw_shift;
> const struct mtk_pll_div_table *div_table;
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 18842d660317..67aaa3082d9b 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -32,6 +32,8 @@
> #define AUDPLL_TUNER_EN BIT(31)
>
> #define POSTDIV_MASK 0x7
> +
> +/* default 7 bits integer, can be overridden with pcwibits. */
> #define INTEGER_BITS 7
>
> /*
> @@ -68,12 +70,15 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
> u32 pcw, int postdiv)
> {
> int pcwbits = pll->data->pcwbits;
> - int pcwfbits;
> + int pcwfbits = 0;
> + int ibits;
> u64 vco;
> u8 c = 0;
>
> /* The fractional part of the PLL divider. */
> - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
> + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> + if (pcwbits > ibits)
> + pcwfbits = pcwbits - ibits;
>
> vco = (u64)fin * pcw;
>
> @@ -170,9 +175,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> u32 freq, u32 fin)
> {
> - unsigned long fmin = 1000 * MHZ;
> + unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
> const struct mtk_pll_div_table *div_table = pll->data->div_table;
> u64 _pcw;
> + int ibits;
> u32 val;
>
> if (freq > pll->data->fmax)
> @@ -196,7 +202,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> }
>
> /* _pcw = freq * postdiv / fin * 2^pcwfbits */
> - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
> + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
> do_div(_pcw, fin);
>
> *pcw = (u32)_pcw;
> --
> 2.18.0
>
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <[email protected]> wrote:
>
> On some Mediatek platforms, there are critical clocks of
> clock gate type.
> To register clock gate with flags CLK_IS_CRITICAL,
> we need to add the flags field in mtk_gate data and register APIs.
>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-and-tested-by: Nicolas Boichat <[email protected]>
> ---
> drivers/clk/mediatek/clk-gate.c | 5 +++--
> drivers/clk/mediatek/clk-gate.h | 3 ++-
> drivers/clk/mediatek/clk-mtk.c | 3 ++-
> drivers/clk/mediatek/clk-mtk.h | 1 +
> 4 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
> index 934bf0e45e26..85daf826619a 100644
> --- a/drivers/clk/mediatek/clk-gate.c
> +++ b/drivers/clk/mediatek/clk-gate.c
> @@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
> int clr_ofs,
> int sta_ofs,
> u8 bit,
> - const struct clk_ops *ops)
> + const struct clk_ops *ops,
> + unsigned long flags)
> {
> struct mtk_clk_gate *cg;
> struct clk *clk;
> @@ -168,7 +169,7 @@ struct clk *mtk_clk_register_gate(
> return ERR_PTR(-ENOMEM);
>
> init.name = name;
> - init.flags = CLK_SET_RATE_PARENT;
> + init.flags = flags | CLK_SET_RATE_PARENT;
> init.parent_names = parent_name ? &parent_name : NULL;
> init.num_parents = parent_name ? 1 : 0;
> init.ops = ops;
> diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
> index 72ef89b3ad7b..9f766dfe1d57 100644
> --- a/drivers/clk/mediatek/clk-gate.h
> +++ b/drivers/clk/mediatek/clk-gate.h
> @@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
> int clr_ofs,
> int sta_ofs,
> u8 bit,
> - const struct clk_ops *ops);
> + const struct clk_ops *ops,
> + unsigned long flags);
>
> #endif /* __DRV_CLK_GATE_H */
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index 9c0ae4278a94..35359e5397c7 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -130,7 +130,8 @@ int mtk_clk_register_gates(struct device_node *node,
> gate->regs->set_ofs,
> gate->regs->clr_ofs,
> gate->regs->sta_ofs,
> - gate->shift, gate->ops);
> + gate->shift, gate->ops,
> + gate->flags);
>
> if (IS_ERR(clk)) {
> pr_err("Failed to register clk %s: %ld\n",
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 11b5517903d0..928905496c4b 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -158,6 +158,7 @@ struct mtk_gate {
> const struct mtk_gate_regs *regs;
> int shift;
> const struct clk_ops *ops;
> + unsigned long flags;
> };
>
> int mtk_clk_register_gates(struct device_node *node,
> --
> 2.18.0
>
On Tue, Mar 5, 2019 at 1:05 PM Weiyi Lu <[email protected]> wrote:
>
> In previous MediaTek PLL design, it assumes the pcw change control
> is always on the CON1 register.
> However, the pcw change bit on MT8183 was moved onto CON0 because
> the the PCW length of audio PLLs are extended to 32-bit.
> Add configurable pcw_chg_reg to set the pcw change control register
> address or using the default control register CON1 if without
> setting in pll data.
>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-and-tested-by: Nicolas Boichat <[email protected]>
> ---
> drivers/clk/mediatek/clk-mtk.h | 1 +
> drivers/clk/mediatek/clk-pll.c | 17 +++++++++++------
> 2 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 928905496c4b..37ae944548e9 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -221,6 +221,7 @@ struct mtk_pll_data {
> int pcwibits;
> uint32_t pcw_reg;
> int pcw_shift;
> + uint32_t pcw_chg_reg;
> const struct mtk_pll_div_table *div_table;
> const char *parent_name;
> };
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 67aaa3082d9b..65cee1d6c400 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -27,7 +27,7 @@
> #define CON0_BASE_EN BIT(0)
> #define CON0_PWR_ON BIT(0)
> #define CON0_ISO_EN BIT(1)
> -#define CON0_PCW_CHG BIT(31)
> +#define PCW_CHG_MASK BIT(31)
>
> #define AUDPLL_TUNER_EN BIT(31)
>
> @@ -51,6 +51,7 @@ struct mtk_clk_pll {
> void __iomem *tuner_addr;
> void __iomem *tuner_en_addr;
> void __iomem *pcw_addr;
> + void __iomem *pcw_chg_addr;
> const struct mtk_pll_data *data;
> };
>
> @@ -122,7 +123,7 @@ static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
> static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> int postdiv)
> {
> - u32 con1, val;
> + u32 chg, val;
> int pll_en;
>
> pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
> @@ -147,14 +148,14 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
> val |= pcw << pll->data->pcw_shift;
> writel(val, pll->pcw_addr);
>
> - con1 = readl(pll->base_addr + REG_CON1);
> + chg = readl(pll->pcw_chg_addr);
>
> if (pll_en)
> - con1 |= CON0_PCW_CHG;
> + chg |= PCW_CHG_MASK;
>
> - writel(con1, pll->base_addr + REG_CON1);
> + writel(chg, pll->pcw_chg_addr);
> if (pll->tuner_addr)
> - writel(con1 + 1, pll->tuner_addr);
> + writel(val + 1, pll->tuner_addr);
>
> /* restore tuner_en */
> __mtk_pll_tuner_enable(pll);
> @@ -329,6 +330,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
> pll->pwr_addr = base + data->pwr_reg;
> pll->pd_addr = base + data->pd_reg;
> pll->pcw_addr = base + data->pcw_reg;
> + if (data->pcw_chg_reg)
> + pll->pcw_chg_addr = base + data->pcw_chg_reg;
> + else
> + pll->pcw_chg_addr = pll->base_addr + REG_CON1;
> if (data->tuner_reg)
> pll->tuner_addr = base + data->tuner_reg;
> if (data->tuner_en_reg)
> --
> 2.18.0
>
)
On Tue, Mar 5, 2019 at 1:05 PM Weiyi Lu <[email protected]> wrote:
>
> Add MT8183 clock support, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu <[email protected]>
In v1 a while back (https://patchwork.kernel.org/patch/10669765/) I
was complaining about code duplication between these many files, and
wondering if we can make simplify a lot of this code.
Apart from that:
Tested-by: Nicolas Boichat <[email protected]>
> ---
> drivers/clk/mediatek/Kconfig | 75 ++
> drivers/clk/mediatek/Makefile | 12 +
> drivers/clk/mediatek/clk-gate.h | 14 +
> drivers/clk/mediatek/clk-mt8183-audio.c | 105 ++
> drivers/clk/mediatek/clk-mt8183-cam.c | 63 +
> drivers/clk/mediatek/clk-mt8183-img.c | 63 +
> drivers/clk/mediatek/clk-mt8183-ipu0.c | 56 +
> drivers/clk/mediatek/clk-mt8183-ipu1.c | 56 +
> drivers/clk/mediatek/clk-mt8183-ipu_adl.c | 54 +
> drivers/clk/mediatek/clk-mt8183-ipu_conn.c | 123 ++
> drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 54 +
> drivers/clk/mediatek/clk-mt8183-mm.c | 111 ++
> drivers/clk/mediatek/clk-mt8183-vdec.c | 67 +
> drivers/clk/mediatek/clk-mt8183-venc.c | 59 +
> drivers/clk/mediatek/clk-mt8183.c | 1284 ++++++++++++++++++++
> 15 files changed, 2196 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8183-audio.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-cam.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-img.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu0.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu1.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_adl.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-ipu_conn.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-mfgcfg.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-mm.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-vdec.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183-venc.c
> create mode 100644 drivers/clk/mediatek/clk-mt8183.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 53edade25a1d..1cc414290818 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -216,4 +216,79 @@ config COMMON_CLK_MT8173
> default ARCH_MEDIATEK
> ---help---
> This driver supports MediaTek MT8173 clocks.
> +
> +config COMMON_CLK_MT8183
> + bool "Clock driver for MediaTek MT8183"
> + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
> + select COMMON_CLK_MEDIATEK
> + default ARCH_MEDIATEK && ARM64
> + help
> + This driver supports MediaTek MT8183 basic clocks.
> +
> +config COMMON_CLK_MT8183_AUDIOSYS
> + bool "Clock driver for MediaTek MT8183 audiosys"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 audiosys clocks.
> +
> +config COMMON_CLK_MT8183_CAMSYS
> + bool "Clock driver for MediaTek MT8183 camsys"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 camsys clocks.
> +
> +config COMMON_CLK_MT8183_IMGSYS
> + bool "Clock driver for MediaTek MT8183 imgsys"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 imgsys clocks.
> +
> +config COMMON_CLK_MT8183_IPU_CORE0
> + bool "Clock driver for MediaTek MT8183 ipu_core0"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 ipu_core0 clocks.
> +
> +config COMMON_CLK_MT8183_IPU_CORE1
> + bool "Clock driver for MediaTek MT8183 ipu_core1"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 ipu_core1 clocks.
> +
> +config COMMON_CLK_MT8183_IPU_ADL
> + bool "Clock driver for MediaTek MT8183 ipu_adl"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 ipu_adl clocks.
> +
> +config COMMON_CLK_MT8183_IPU_CONN
> + bool "Clock driver for MediaTek MT8183 ipu_conn"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 ipu_conn clocks.
> +
> +config COMMON_CLK_MT8183_MFGCFG
> + bool "Clock driver for MediaTek MT8183 mfgcfg"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 mfgcfg clocks.
> +
> +config COMMON_CLK_MT8183_MMSYS
> + bool "Clock driver for MediaTek MT8183 mmsys"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 mmsys clocks.
> +
> +config COMMON_CLK_MT8183_VDECSYS
> + bool "Clock driver for MediaTek MT8183 vdecsys"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 vdecsys clocks.
> +
> +config COMMON_CLK_MT8183_VENCSYS
> + bool "Clock driver for MediaTek MT8183 vencsys"
> + depends on COMMON_CLK_MT8183
> + help
> + This driver supports MediaTek MT8183 vencsys clocks.
> +
> endmenu
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 20cf9eea4171..3dc1b9f15ea2 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -32,3 +32,15 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
> obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
> obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
> obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
> +obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) += clk-mt8183-img.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE0) += clk-mt8183-ipu0.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CORE1) += clk-mt8183-ipu1.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_IPU_ADL) += clk-mt8183-ipu_adl.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_IPU_CONN) += clk-mt8183-ipu_conn.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
> +obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
> diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
> index 9f766dfe1d57..ab240163f9f8 100644
> --- a/drivers/clk/mediatek/clk-gate.h
> +++ b/drivers/clk/mediatek/clk-gate.h
> @@ -50,4 +50,18 @@ struct clk *mtk_clk_register_gate(
> const struct clk_ops *ops,
> unsigned long flags);
>
> +#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
> + _ops, _flags) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = _regs, \
> + .shift = _shift, \
> + .ops = _ops, \
> + .flags = _flags, \
> + }
> +
> +#define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
> + GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
> +
> #endif /* __DRV_CLK_GATE_H */
> diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c
> new file mode 100644
> index 000000000000..c87450180b7b
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-audio.c
> @@ -0,0 +1,105 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs audio0_cg_regs = {
> + .set_ofs = 0x0,
> + .clr_ofs = 0x0,
> + .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs audio1_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x4,
> + .sta_ofs = 0x4,
> +};
> +
> +#define GATE_AUDIO0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr)
> +
> +#define GATE_AUDIO1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr)
> +
> +static const struct mtk_gate audio_clks[] = {
> + /* AUDIO0 */
> + GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
> + 2),
> + GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
> + 8),
> + GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
> + 9),
> + GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
> + 18),
> + GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
> + 19),
> + GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
> + 20),
> + GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
> + 24),
> + GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
> + 25),
> + GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
> + 26),
> + GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
> + 27),
> + /* AUDIO1 */
> + GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
> + 4),
> + GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
> + 5),
> + GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
> + 6),
> + GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
> + 7),
> + GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
> + 20),
> +};
> +
> +static int clk_mt8183_audio_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + int r;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
> +
> + mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
> + clk_data);
> +
> + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> + if (r)
> + return r;
> +
> + r = devm_of_platform_populate(&pdev->dev);
> + if (r)
> + of_clk_del_provider(node);
> +
> + return r;
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_audio[] = {
> + { .compatible = "mediatek,mt8183-audiosys", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_audio_drv = {
> + .probe = clk_mt8183_audio_probe,
> + .driver = {
> + .name = "clk-mt8183-audio",
> + .of_match_table = of_match_clk_mt8183_audio,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_audio_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-cam.c b/drivers/clk/mediatek/clk-mt8183-cam.c
> new file mode 100644
> index 000000000000..8643802c4471
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-cam.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs cam_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_CAM(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate cam_clks[] = {
> + GATE_CAM(CLK_CAM_LARB6, "cam_larb6", "cam_sel", 0),
> + GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
> + GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "cam_sel", 2),
> + GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
> + GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
> + GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
> + GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
> + GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
> + GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
> + GATE_CAM(CLK_CAM_CCU, "cam_ccu", "cam_sel", 12),
> +};
> +
> +static int clk_mt8183_cam_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
> +
> + mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_cam[] = {
> + { .compatible = "mediatek,mt8183-camsys", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_cam_drv = {
> + .probe = clk_mt8183_cam_probe,
> + .driver = {
> + .name = "clk-mt8183-cam",
> + .of_match_table = of_match_clk_mt8183_cam,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_cam_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/clk-mt8183-img.c
> new file mode 100644
> index 000000000000..470d676a4a10
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-img.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs img_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_IMG(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate img_clks[] = {
> + GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
> + GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
> + GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
> + GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
> + GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
> + GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
> + GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
> + GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
> + GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
> + GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
> +};
> +
> +static int clk_mt8183_img_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
> +
> + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_img[] = {
> + { .compatible = "mediatek,mt8183-imgsys", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_img_drv = {
> + .probe = clk_mt8183_img_probe,
> + .driver = {
> + .name = "clk-mt8183-img",
> + .of_match_table = of_match_clk_mt8183_img,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_img_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-ipu0.c b/drivers/clk/mediatek/clk-mt8183-ipu0.c
> new file mode 100644
> index 000000000000..c5cb76fc9e5e
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-ipu0.c
> @@ -0,0 +1,56 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs ipu_core0_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_IPU_CORE0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_core0_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate ipu_core0_clks[] = {
> + GATE_IPU_CORE0(CLK_IPU_CORE0_JTAG, "ipu_core0_jtag", "dsp_sel", 0),
> + GATE_IPU_CORE0(CLK_IPU_CORE0_AXI, "ipu_core0_axi", "dsp_sel", 1),
> + GATE_IPU_CORE0(CLK_IPU_CORE0_IPU, "ipu_core0_ipu", "dsp_sel", 2),
> +};
> +
> +static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
> +
> + mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
> + { .compatible = "mediatek,mt8183-ipu_core0", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_ipu_core0_drv = {
> + .probe = clk_mt8183_ipu_core0_probe,
> + .driver = {
> + .name = "clk-mt8183-ipu_core0",
> + .of_match_table = of_match_clk_mt8183_ipu_core0,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_ipu_core0_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-ipu1.c b/drivers/clk/mediatek/clk-mt8183-ipu1.c
> new file mode 100644
> index 000000000000..8fd5fe002890
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-ipu1.c
> @@ -0,0 +1,56 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs ipu_core1_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_IPU_CORE1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_core1_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate ipu_core1_clks[] = {
> + GATE_IPU_CORE1(CLK_IPU_CORE1_JTAG, "ipu_core1_jtag", "dsp_sel", 0),
> + GATE_IPU_CORE1(CLK_IPU_CORE1_AXI, "ipu_core1_axi", "dsp_sel", 1),
> + GATE_IPU_CORE1(CLK_IPU_CORE1_IPU, "ipu_core1_ipu", "dsp_sel", 2),
> +};
> +
> +static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK);
> +
> + mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {
> + { .compatible = "mediatek,mt8183-ipu_core1", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_ipu_core1_drv = {
> + .probe = clk_mt8183_ipu_core1_probe,
> + .driver = {
> + .name = "clk-mt8183-ipu_core1",
> + .of_match_table = of_match_clk_mt8183_ipu_core1,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_ipu_core1_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c
> new file mode 100644
> index 000000000000..3f37d0ef1df1
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs ipu_adl_cg_regs = {
> + .set_ofs = 0x204,
> + .clr_ofs = 0x204,
> + .sta_ofs = 0x204,
> +};
> +
> +#define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate ipu_adl_clks[] = {
> + GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
> +};
> +
> +static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
> +
> + mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
> + { .compatible = "mediatek,mt8183-ipu_adl", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_ipu_adl_drv = {
> + .probe = clk_mt8183_ipu_adl_probe,
> + .driver = {
> + .name = "clk-mt8183-ipu_adl",
> + .of_match_table = of_match_clk_mt8183_ipu_adl,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_ipu_adl_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c
> new file mode 100644
> index 000000000000..7e0eef79c461
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs ipu_conn_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs ipu_conn_apb_cg_regs = {
> + .set_ofs = 0x10,
> + .clr_ofs = 0x10,
> + .sta_ofs = 0x10,
> +};
> +
> +static const struct mtk_gate_regs ipu_conn_axi_cg_regs = {
> + .set_ofs = 0x18,
> + .clr_ofs = 0x18,
> + .sta_ofs = 0x18,
> +};
> +
> +static const struct mtk_gate_regs ipu_conn_axi1_cg_regs = {
> + .set_ofs = 0x1c,
> + .clr_ofs = 0x1c,
> + .sta_ofs = 0x1c,
> +};
> +
> +static const struct mtk_gate_regs ipu_conn_axi2_cg_regs = {
> + .set_ofs = 0x20,
> + .clr_ofs = 0x20,
> + .sta_ofs = 0x20,
> +};
> +
> +#define GATE_IPU_CONN(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr)
> +
> +#define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr_inv)
> +
> +#define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate ipu_conn_clks[] = {
> + GATE_IPU_CONN(CLK_IPU_CONN_IPU,
> + "ipu_conn_ipu", "dsp_sel", 0),
> + GATE_IPU_CONN(CLK_IPU_CONN_AHB,
> + "ipu_conn_ahb", "dsp_sel", 1),
> + GATE_IPU_CONN(CLK_IPU_CONN_AXI,
> + "ipu_conn_axi", "dsp_sel", 2),
> + GATE_IPU_CONN(CLK_IPU_CONN_ISP,
> + "ipu_conn_isp", "dsp_sel", 3),
> + GATE_IPU_CONN(CLK_IPU_CONN_CAM_ADL,
> + "ipu_conn_cam_adl", "dsp_sel", 4),
> + GATE_IPU_CONN(CLK_IPU_CONN_IMG_ADL,
> + "ipu_conn_img_adl", "dsp_sel", 5),
> + GATE_IPU_CONN_APB(CLK_IPU_CONN_DAP_RX,
> + "ipu_conn_dap_rx", "dsp1_sel", 0),
> + GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AXI,
> + "ipu_conn_apb2axi", "dsp1_sel", 3),
> + GATE_IPU_CONN_APB(CLK_IPU_CONN_APB2AHB,
> + "ipu_conn_apb2ahb", "dsp1_sel", 20),
> + GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU_CAB1TO2,
> + "ipu_conn_ipu_cab1to2", "dsp1_sel", 6),
> + GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU1_CAB1TO2,
> + "ipu_conn_ipu1_cab1to2", "dsp1_sel", 13),
> + GATE_IPU_CONN_AXI_I(CLK_IPU_CONN_IPU2_CAB1TO2,
> + "ipu_conn_ipu2_cab1to2", "dsp1_sel", 20),
> + GATE_IPU_CONN_AXI1_I(CLK_IPU_CONN_CAB3TO3,
> + "ipu_conn_cab3to3", "dsp1_sel", 0),
> + GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB2TO1,
> + "ipu_conn_cab2to1", "dsp1_sel", 14),
> + GATE_IPU_CONN_AXI2_I(CLK_IPU_CONN_CAB3TO1_SLICE,
> + "ipu_conn_cab3to1_slice", "dsp1_sel", 17),
> +};
> +
> +static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
> +
> + mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
> + { .compatible = "mediatek,mt8183-ipu_conn", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_ipu_conn_drv = {
> + .probe = clk_mt8183_ipu_conn_probe,
> + .driver = {
> + .name = "clk-mt8183-ipu_conn",
> + .of_match_table = of_match_clk_mt8183_ipu_conn,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_ipu_conn_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
> new file mode 100644
> index 000000000000..99a6b020833e
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs mfg_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_MFG(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate mfg_clks[] = {
> + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0)
> +};
> +
> +static int clk_mt8183_mfg_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
> +
> + mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_mfg[] = {
> + { .compatible = "mediatek,mt8183-mfgcfg", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_mfg_drv = {
> + .probe = clk_mt8183_mfg_probe,
> + .driver = {
> + .name = "clk-mt8183-mfg",
> + .of_match_table = of_match_clk_mt8183_mfg,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_mfg_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/clk-mt8183-mm.c
> new file mode 100644
> index 000000000000..720c696b506d
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-mm.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs mm0_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs mm1_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +#define GATE_MM0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_MM1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate mm_clks[] = {
> + /* MM0 */
> + GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
> + GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
> + GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
> + GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
> + GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
> + GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
> + GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
> + GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
> + GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
> + GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
> + GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
> + GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
> + GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
> + GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
> + GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
> + GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
> + GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
> + GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
> + GATE_MM0(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 18),
> + GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
> + GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
> + GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
> + GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
> + GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
> + GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
> + GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
> + GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
> + GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
> + GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
> + GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
> + GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
> + GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
> + /* MM1 */
> + GATE_MM1(CLK_MM_DSI0_MM, "mm_dsi0_mm", "mm_sel", 0),
> + GATE_MM1(CLK_MM_DSI0_IF, "mm_dsi0_if", "mm_sel", 1),
> + GATE_MM1(CLK_MM_DPI_MM, "mm_dpi_mm", "mm_sel", 2),
> + GATE_MM1(CLK_MM_DPI_IF, "mm_dpi_if", "dpi0_sel", 3),
> + GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
> + GATE_MM1(CLK_MM_MDP_DL_RX, "mm_mdp_dl_rx", "mm_sel", 5),
> + GATE_MM1(CLK_MM_IPU_DL_RX, "mm_ipu_dl_rx", "mm_sel", 6),
> + GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
> + GATE_MM1(CLK_MM_MMSYS_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
> + GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
> + GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
> + GATE_MM1(CLK_MM_MDP_CCORR, "mm_mdp_ccorr", "mm_sel", 11),
> + GATE_MM1(CLK_MM_DBI_MM, "mm_dbi_mm", "mm_sel", 12),
> + GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13),
> +};
> +
> +static int clk_mt8183_mm_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
> +
> + mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_mm[] = {
> + { .compatible = "mediatek,mt8183-mmsys", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_mm_drv = {
> + .probe = clk_mt8183_mm_probe,
> + .driver = {
> + .name = "clk-mt8183-mm",
> + .of_match_table = of_match_clk_mt8183_mm,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_mm_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/clk-mt8183-vdec.c
> new file mode 100644
> index 000000000000..6250fd1e0edc
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs vdec0_cg_regs = {
> + .set_ofs = 0x0,
> + .clr_ofs = 0x4,
> + .sta_ofs = 0x0,
> +};
> +
> +static const struct mtk_gate_regs vdec1_cg_regs = {
> + .set_ofs = 0x8,
> + .clr_ofs = 0xc,
> + .sta_ofs = 0x8,
> +};
> +
> +#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr_inv)
> +
> +#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate vdec_clks[] = {
> + /* VDEC0 */
> + GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0),
> + /* VDEC1 */
> + GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0),
> +};
> +
> +static int clk_mt8183_vdec_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
> +
> + mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_vdec[] = {
> + { .compatible = "mediatek,mt8183-vdecsys", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_vdec_drv = {
> + .probe = clk_mt8183_vdec_probe,
> + .driver = {
> + .name = "clk-mt8183-vdec",
> + .of_match_table = of_match_clk_mt8183_vdec,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_vdec_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183-venc.c b/drivers/clk/mediatek/clk-mt8183-venc.c
> new file mode 100644
> index 000000000000..6678ef03fab2
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183-venc.c
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static const struct mtk_gate_regs venc_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_VENC_I(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr_inv)
> +
> +static const struct mtk_gate venc_clks[] = {
> + GATE_VENC_I(CLK_VENC_LARB, "venc_larb",
> + "mm_sel", 0),
> + GATE_VENC_I(CLK_VENC_VENC, "venc_venc",
> + "mm_sel", 4),
> + GATE_VENC_I(CLK_VENC_JPGENC, "venc_jpgenc",
> + "mm_sel", 8),
> +};
> +
> +static int clk_mt8183_venc_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
> +
> + mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183_venc[] = {
> + { .compatible = "mediatek,mt8183-vencsys", },
> + {}
> +};
> +
> +static struct platform_driver clk_mt8183_venc_drv = {
> + .probe = clk_mt8183_venc_probe,
> + .driver = {
> + .name = "clk-mt8183-venc",
> + .of_match_table = of_match_clk_mt8183_venc,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8183_venc_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
> new file mode 100644
> index 000000000000..68f157b31b28
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8183.c
> @@ -0,0 +1,1284 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2018 MediaTek Inc.
> +// Author: Weiyi Lu <[email protected]>
> +
> +#include <linux/delay.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +
> +static DEFINE_SPINLOCK(mt8183_clk_lock);
> +
> +static const struct mtk_fixed_clk top_fixed_clks[] = {
> + FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
> + FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
> + FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
> +};
> +
> +static const struct mtk_fixed_factor top_divs[] = {
> + FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
> + 2),
> + FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
> + 2),
> + FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
> + 1),
> + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
> + 2),
> + FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
> + 2),
> + FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
> + 4),
> + FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
> + 8),
> + FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
> + 16),
> + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
> + 3),
> + FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
> + 2),
> + FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
> + 4),
> + FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
> + 8),
> + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
> + 5),
> + FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
> + 2),
> + FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
> + 4),
> + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
> + 7),
> + FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
> + 2),
> + FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
> + 4),
> + FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
> + 1),
> + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
> + 2),
> + FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
> + 2),
> + FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
> + 4),
> + FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
> + 8),
> + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
> + 3),
> + FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
> + 2),
> + FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
> + 4),
> + FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
> + 8),
> + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
> + 5),
> + FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
> + 2),
> + FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
> + 4),
> + FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
> + 8),
> + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
> + 7),
> + FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
> + 1),
> + FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
> + 2),
> + FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
> + 4),
> + FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
> + 8),
> + FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
> + 16),
> + FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
> + 32),
> + FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
> + 1),
> + FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
> + 2),
> + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
> + 4),
> + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
> + 8),
> + FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
> + 1),
> + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
> + 2),
> + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
> + 4),
> + FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
> + 8),
> + FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
> + 1),
> + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
> + 2),
> + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
> + 4),
> + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
> + 8),
> + FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
> + 16),
> + FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
> + 1),
> + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
> + 4),
> + FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
> + 2),
> + FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
> + 4),
> + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
> + 5),
> + FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
> + 2),
> + FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
> + 4),
> + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
> + 6),
> + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
> + 7),
> + FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
> + 1),
> + FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
> + 1),
> + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
> + 2),
> + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
> + 4),
> + FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
> + 8),
> + FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
> + 16),
> + FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
> + 1),
> + FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
> + 2),
> + FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
> + 4),
> + FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
> + 8),
> + FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
> + 16),
> + FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
> + 2),
> + FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
> + 16),
> +};
> +
> +static const char * const axi_parents[] = {
> + "clk26m",
> + "syspll_d2_d4",
> + "syspll_d7",
> + "osc_d4"
> +};
> +
> +static const char * const mm_parents[] = {
> + "clk26m",
> + "mmpll_d7",
> + "syspll_d3",
> + "univpll_d2_d2",
> + "syspll_d2_d2",
> + "syspll_d3_d2"
> +};
> +
> +static const char * const img_parents[] = {
> + "clk26m",
> + "mmpll_d6",
> + "univpll_d3",
> + "syspll_d3",
> + "univpll_d2_d2",
> + "syspll_d2_d2",
> + "univpll_d3_d2",
> + "syspll_d3_d2"
> +};
> +
> +static const char * const cam_parents[] = {
> + "clk26m",
> + "syspll_d2",
> + "mmpll_d6",
> + "syspll_d3",
> + "mmpll_d7",
> + "univpll_d3",
> + "univpll_d2_d2",
> + "syspll_d2_d2",
> + "syspll_d3_d2",
> + "univpll_d3_d2"
> +};
> +
> +static const char * const dsp_parents[] = {
> + "clk26m",
> + "mmpll_d6",
> + "mmpll_d7",
> + "univpll_d3",
> + "syspll_d3",
> + "univpll_d2_d2",
> + "syspll_d2_d2",
> + "univpll_d3_d2",
> + "syspll_d3_d2"
> +};
> +
> +static const char * const dsp1_parents[] = {
> + "clk26m",
> + "mmpll_d6",
> + "mmpll_d7",
> + "univpll_d3",
> + "syspll_d3",
> + "univpll_d2_d2",
> + "syspll_d2_d2",
> + "univpll_d3_d2",
> + "syspll_d3_d2"
> +};
> +
> +static const char * const dsp2_parents[] = {
> + "clk26m",
> + "mmpll_d6",
> + "mmpll_d7",
> + "univpll_d3",
> + "syspll_d3",
> + "univpll_d2_d2",
> + "syspll_d2_d2",
> + "univpll_d3_d2",
> + "syspll_d3_d2"
> +};
> +
> +static const char * const ipu_if_parents[] = {
> + "clk26m",
> + "mmpll_d6",
> + "mmpll_d7",
> + "univpll_d3",
> + "syspll_d3",
> + "univpll_d2_d2",
> + "syspll_d2_d2",
> + "univpll_d3_d2",
> + "syspll_d3_d2"
> +};
> +
> +static const char * const mfg_parents[] = {
> + "clk26m",
> + "mfgpll_ck",
> + "univpll_d3",
> + "syspll_d3"
> +};
> +
> +static const char * const f52m_mfg_parents[] = {
> + "clk26m",
> + "univpll_d3_d2",
> + "univpll_d3_d4",
> + "univpll_d3_d8"
> +};
> +
> +static const char * const camtg_parents[] = {
> + "clk26m",
> + "univ_192m_d8",
> + "univpll_d3_d8",
> + "univ_192m_d4",
> + "univpll_d3_d16",
> + "csw_f26m_ck_d2",
> + "univ_192m_d16",
> + "univ_192m_d32"
> +};
> +
> +static const char * const camtg2_parents[] = {
> + "clk26m",
> + "univ_192m_d8",
> + "univpll_d3_d8",
> + "univ_192m_d4",
> + "univpll_d3_d16",
> + "csw_f26m_ck_d2",
> + "univ_192m_d16",
> + "univ_192m_d32"
> +};
> +
> +static const char * const camtg3_parents[] = {
> + "clk26m",
> + "univ_192m_d8",
> + "univpll_d3_d8",
> + "univ_192m_d4",
> + "univpll_d3_d16",
> + "csw_f26m_ck_d2",
> + "univ_192m_d16",
> + "univ_192m_d32"
> +};
> +
> +static const char * const camtg4_parents[] = {
> + "clk26m",
> + "univ_192m_d8",
> + "univpll_d3_d8",
> + "univ_192m_d4",
> + "univpll_d3_d16",
> + "csw_f26m_ck_d2",
> + "univ_192m_d16",
> + "univ_192m_d32"
> +};
> +
> +static const char * const uart_parents[] = {
> + "clk26m",
> + "univpll_d3_d8"
> +};
> +
> +static const char * const spi_parents[] = {
> + "clk26m",
> + "syspll_d5_d2",
> + "syspll_d3_d4",
> + "msdcpll_d4"
> +};
> +
> +static const char * const msdc50_hclk_parents[] = {
> + "clk26m",
> + "syspll_d2_d2",
> + "syspll_d3_d2"
> +};
> +
> +static const char * const msdc50_0_parents[] = {
> + "clk26m",
> + "msdcpll_ck",
> + "msdcpll_d2",
> + "univpll_d2_d4",
> + "syspll_d3_d2",
> + "univpll_d2_d2"
> +};
> +
> +static const char * const msdc30_1_parents[] = {
> + "clk26m",
> + "univpll_d3_d2",
> + "syspll_d3_d2",
> + "syspll_d7",
> + "msdcpll_d2"
> +};
> +
> +static const char * const msdc30_2_parents[] = {
> + "clk26m",
> + "univpll_d3_d2",
> + "syspll_d3_d2",
> + "syspll_d7",
> + "msdcpll_d2"
> +};
> +
> +static const char * const audio_parents[] = {
> + "clk26m",
> + "syspll_d5_d4",
> + "syspll_d7_d4",
> + "syspll_d2_d16"
> +};
> +
> +static const char * const aud_intbus_parents[] = {
> + "clk26m",
> + "syspll_d2_d4",
> + "syspll_d7_d2"
> +};
> +
> +static const char * const pmicspi_parents[] = {
> + "clk26m",
> + "syspll_d2_d8",
> + "osc_d8"
> +};
> +
> +static const char * const fpwrap_ulposc_parents[] = {
> + "clk26m",
> + "osc_d16",
> + "osc_d4",
> + "osc_d8"
> +};
> +
> +static const char * const atb_parents[] = {
> + "clk26m",
> + "syspll_d2_d2",
> + "syspll_d5"
> +};
> +
> +static const char * const sspm_parents[] = {
> + "clk26m",
> + "univpll_d2_d4",
> + "syspll_d2_d2",
> + "univpll_d2_d2",
> + "syspll_d3"
> +};
> +
> +static const char * const dpi0_parents[] = {
> + "clk26m",
> + "tvdpll_d2",
> + "tvdpll_d4",
> + "tvdpll_d8",
> + "tvdpll_d16",
> + "univpll_d5_d2",
> + "univpll_d3_d4",
> + "syspll_d3_d4",
> + "univpll_d3_d8"
> +};
> +
> +static const char * const scam_parents[] = {
> + "clk26m",
> + "syspll_d5_d2"
> +};
> +
> +static const char * const disppwm_parents[] = {
> + "clk26m",
> + "univpll_d3_d4",
> + "osc_d2",
> + "osc_d4",
> + "osc_d16"
> +};
> +
> +static const char * const usb_top_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d3_d4",
> + "univpll_d5_d2"
> +};
> +
> +
> +static const char * const ssusb_top_xhci_parents[] = {
> + "clk26m",
> + "univpll_d5_d4",
> + "univpll_d3_d4",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const spm_parents[] = {
> + "clk26m",
> + "syspll_d2_d8"
> +};
> +
> +static const char * const i2c_parents[] = {
> + "clk26m",
> + "syspll_d2_d8",
> + "univpll_d5_d2"
> +};
> +
> +static const char * const scp_parents[] = {
> + "clk26m",
> + "univpll_d2_d8",
> + "syspll_d5",
> + "syspll_d2_d2",
> + "univpll_d2_d2",
> + "syspll_d3",
> + "univpll_d3"
> +};
> +
> +static const char * const seninf_parents[] = {
> + "clk26m",
> + "univpll_d2_d2",
> + "univpll_d3_d2",
> + "univpll_d2_d4"
> +};
> +
> +static const char * const dxcc_parents[] = {
> + "clk26m",
> + "syspll_d2_d2",
> + "syspll_d2_d4",
> + "syspll_d2_d8"
> +};
> +
> +static const char * const aud_engen1_parents[] = {
> + "clk26m",
> + "apll1_d2",
> + "apll1_d4",
> + "apll1_d8"
> +};
> +
> +static const char * const aud_engen2_parents[] = {
> + "clk26m",
> + "apll2_d2",
> + "apll2_d4",
> + "apll2_d8"
> +};
> +
> +static const char * const faes_ufsfde_parents[] = {
> + "clk26m",
> + "syspll_d2",
> + "syspll_d2_d2",
> + "syspll_d3",
> + "syspll_d2_d4",
> + "univpll_d3"
> +};
> +
> +static const char * const fufs_parents[] = {
> + "clk26m",
> + "syspll_d2_d4",
> + "syspll_d2_d8",
> + "syspll_d2_d16"
> +};
> +
> +static const char * const aud_1_parents[] = {
> + "clk26m",
> + "apll1_ck"
> +};
> +
> +static const char * const aud_2_parents[] = {
> + "clk26m",
> + "apll2_ck"
> +};
> +
> +/*
> + * CRITICAL CLOCK:
> + * axi_sel is the main bus clock of whole SOC.
> + * spm_sel is the clock of the always-on co-processor.
> + */
> +static const struct mtk_mux top_muxes[] = {
> + /* CLK_CFG_0 */
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
> + axi_parents, 0x40,
> + 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
> + mm_parents, 0x40,
> + 0x44, 0x48, 8, 3, 15, 0x004, 1),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
> + img_parents, 0x40,
> + 0x44, 0x48, 16, 3, 23, 0x004, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
> + cam_parents, 0x40,
> + 0x44, 0x48, 24, 4, 31, 0x004, 3),
> + /* CLK_CFG_1 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
> + dsp_parents, 0x50,
> + 0x54, 0x58, 0, 4, 7, 0x004, 4),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
> + dsp1_parents, 0x50,
> + 0x54, 0x58, 8, 4, 15, 0x004, 5),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
> + dsp2_parents, 0x50,
> + 0x54, 0x58, 16, 4, 23, 0x004, 6),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
> + ipu_if_parents, 0x50,
> + 0x54, 0x58, 24, 4, 31, 0x004, 7),
> + /* CLK_CFG_2 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
> + mfg_parents, 0x60,
> + 0x64, 0x68, 0, 2, 7, 0x004, 8),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
> + f52m_mfg_parents, 0x60,
> + 0x64, 0x68, 8, 2, 15, 0x004, 9),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
> + camtg_parents, 0x60,
> + 0x64, 0x68, 16, 3, 23, 0x004, 10),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
> + camtg2_parents, 0x60,
> + 0x64, 0x68, 24, 3, 31, 0x004, 11),
> + /* CLK_CFG_3 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
> + camtg3_parents, 0x70,
> + 0x74, 0x78, 0, 3, 7, 0x004, 12),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
> + camtg4_parents, 0x70,
> + 0x74, 0x78, 8, 3, 15, 0x004, 13),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
> + uart_parents, 0x70,
> + 0x74, 0x78, 16, 1, 23, 0x004, 14),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
> + spi_parents, 0x70,
> + 0x74, 0x78, 24, 2, 31, 0x004, 15),
> + /* CLK_CFG_4 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
> + msdc50_hclk_parents, 0x80,
> + 0x84, 0x88, 0, 2, 7, 0x004, 16),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
> + msdc50_0_parents, 0x80,
> + 0x84, 0x88, 8, 3, 15, 0x004, 17),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
> + msdc30_1_parents, 0x80,
> + 0x84, 0x88, 16, 3, 23, 0x004, 18),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
> + msdc30_2_parents, 0x80,
> + 0x84, 0x88, 24, 3, 31, 0x004, 19),
> + /* CLK_CFG_5 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
> + audio_parents, 0x90,
> + 0x94, 0x98, 0, 2, 7, 0x004, 20),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
> + aud_intbus_parents, 0x90,
> + 0x94, 0x98, 8, 2, 15, 0x004, 21),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
> + pmicspi_parents, 0x90,
> + 0x94, 0x98, 16, 2, 23, 0x004, 22),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
> + fpwrap_ulposc_parents, 0x90,
> + 0x94, 0x98, 24, 2, 31, 0x004, 23),
> + /* CLK_CFG_6 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
> + atb_parents, 0xa0,
> + 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSPM, "sspm_sel",
> + sspm_parents, 0xa0,
> + 0xa4, 0xa8, 8, 3, 15, 0x004, 25),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
> + dpi0_parents, 0xa0,
> + 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
> + scam_parents, 0xa0,
> + 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
> + /* CLK_CFG_7 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
> + disppwm_parents, 0xb0,
> + 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
> + usb_top_parents, 0xb0,
> + 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
> + ssusb_top_xhci_parents, 0xb0,
> + 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
> + spm_parents, 0xb0,
> + 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
> + /* CLK_CFG_8 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
> + i2c_parents, 0xc0,
> + 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
> + scp_parents, 0xc0,
> + 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
> + seninf_parents, 0xc0,
> + 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
> + dxcc_parents, 0xc0,
> + 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
> + /* CLK_CFG_9 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
> + aud_engen1_parents, 0xd0,
> + 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
> + aud_engen2_parents, 0xd0,
> + 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
> + faes_ufsfde_parents, 0xd0,
> + 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
> + fufs_parents, 0xd0,
> + 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
> + /* CLK_CFG_10 */
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
> + aud_1_parents, 0xe0,
> + 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
> + aud_2_parents, 0xe0,
> + 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
> +};
> +
> +static const char * const apll_i2s0_parents[] = {
> + "aud_1_sel",
> + "aud_2_sel"
> +};
> +
> +static const char * const apll_i2s1_parents[] = {
> + "aud_1_sel",
> + "aud_2_sel"
> +};
> +
> +static const char * const apll_i2s2_parents[] = {
> + "aud_1_sel",
> + "aud_2_sel"
> +};
> +
> +static const char * const apll_i2s3_parents[] = {
> + "aud_1_sel",
> + "aud_2_sel"
> +};
> +
> +static const char * const apll_i2s4_parents[] = {
> + "aud_1_sel",
> + "aud_2_sel"
> +};
> +
> +static const char * const apll_i2s5_parents[] = {
> + "aud_1_sel",
> + "aud_2_sel"
> +};
> +
> +static struct mtk_composite top_aud_muxes[] = {
> + MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
> + 0x320, 8, 1),
> + MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
> + 0x320, 9, 1),
> + MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
> + 0x320, 10, 1),
> + MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
> + 0x320, 11, 1),
> + MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
> + 0x320, 12, 1),
> + MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
> + 0x328, 20, 1),
> +};
> +
> +static const char * const mcu_mp0_parents[] = {
> + "clk26m",
> + "armpll_ll",
> + "armpll_div_pll1",
> + "armpll_div_pll2"
> +};
> +
> +static const char * const mcu_mp2_parents[] = {
> + "clk26m",
> + "armpll_l",
> + "armpll_div_pll1",
> + "armpll_div_pll2"
> +};
> +
> +static const char * const mcu_bus_parents[] = {
> + "clk26m",
> + "ccipll",
> + "armpll_div_pll1",
> + "armpll_div_pll2"
> +};
> +
> +static struct mtk_composite mcu_muxes[] = {
> + /* mp0_pll_divider_cfg */
> + MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
> + /* mp2_pll_divider_cfg */
> + MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
> + /* bus_pll_divider_cfg */
> + MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
> +};
> +
> +static struct mtk_composite top_aud_divs[] = {
> + DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
> + 0x320, 2, 0x324, 8, 0),
> + DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
> + 0x320, 3, 0x324, 8, 8),
> + DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel",
> + 0x320, 4, 0x324, 8, 16),
> + DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel",
> + 0x320, 5, 0x324, 8, 24),
> + DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
> + 0x320, 6, 0x328, 8, 0),
> + DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
> + 0x320, 7, 0x328, 8, 8),
> +};
> +
> +static const struct mtk_gate_regs top_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x104,
> + .sta_ofs = 0x104,
> +};
> +
> +#define GATE_TOP(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
> + &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate top_clks[] = {
> + /* TOP */
> + GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
> + GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
> +};
> +
> +static const struct mtk_gate_regs infra0_cg_regs = {
> + .set_ofs = 0x80,
> + .clr_ofs = 0x84,
> + .sta_ofs = 0x90,
> +};
> +
> +static const struct mtk_gate_regs infra1_cg_regs = {
> + .set_ofs = 0x88,
> + .clr_ofs = 0x8c,
> + .sta_ofs = 0x94,
> +};
> +
> +static const struct mtk_gate_regs infra2_cg_regs = {
> + .set_ofs = 0xa4,
> + .clr_ofs = 0xa8,
> + .sta_ofs = 0xac,
> +};
> +
> +static const struct mtk_gate_regs infra3_cg_regs = {
> + .set_ofs = 0xc0,
> + .clr_ofs = 0xc4,
> + .sta_ofs = 0xc8,
> +};
> +
> +#define GATE_INFRA0(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_INFRA1(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_INFRA2(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_INFRA3(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
> + &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate infra_clks[] = {
> + /* INFRA0 */
> + GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
> + "axi_sel", 0),
> + GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
> + "axi_sel", 1),
> + GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
> + "axi_sel", 2),
> + GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
> + "axi_sel", 3),
> + GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
> + "scp_sel", 4),
> + GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
> + "f_f26m_ck", 5),
> + GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
> + "axi_sel", 6),
> + GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
> + "axi_sel", 8),
> + GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
> + "axi_sel", 9),
> + GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
> + "axi_sel", 10),
> + GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
> + "i2c_sel", 11),
> + GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
> + "i2c_sel", 12),
> + GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
> + "i2c_sel", 13),
> + GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
> + "i2c_sel", 14),
> + GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
> + "axi_sel", 15),
> + GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
> + "i2c_sel", 16),
> + GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
> + "i2c_sel", 17),
> + GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
> + "i2c_sel", 18),
> + GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
> + "i2c_sel", 19),
> + GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> + "i2c_sel", 21),
> + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> + "uart_sel", 22),
> + GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> + "uart_sel", 23),
> + GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
> + "uart_sel", 24),
> + GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
> + "uart_sel", 25),
> + GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
> + "axi_sel", 27),
> + GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
> + "axi_sel", 28),
> + GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
> + "axi_sel", 31),
> + /* INFRA1 */
> + GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
> + "spi_sel", 1),
> + GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
> + "msdc50_hclk_sel", 2),
> + GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
> + "axi_sel", 4),
> + GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
> + "axi_sel", 5),
> + GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
> + "msdc50_0_sel", 6),
> + GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
> + "f_f26m_ck", 7),
> + GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
> + "axi_sel", 8),
> + GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
> + "axi_sel", 9),
> + GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
> + "f_f26m_ck", 10),
> + GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
> + "axi_sel", 11),
> + GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
> + "axi_sel", 12),
> + GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
> + "axi_sel", 13),
> + GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
> + "f_f26m_ck", 14),
> + GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
> + "msdc30_1_sel", 16),
> + GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
> + "msdc30_2_sel", 17),
> + GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
> + "axi_sel", 18),
> + GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
> + "axi_sel", 19),
> + GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
> + "axi_sel", 20),
> + GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
> + "axi_sel", 23),
> + GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
> + "axi_sel", 24),
> + GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio",
> + "axi_sel", 25),
> + GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
> + "axi_sel", 26),
> + GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
> + "dxcc_sel", 27),
> + GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
> + "dxcc_sel", 28),
> + GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
> + "axi_sel", 30),
> + GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
> + "f_f26m_ck", 31),
> + /* INFRA2 */
> + GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
> + "f_f26m_ck", 0),
> + GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
> + "usb_top_sel", 1),
> + GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
> + "axi_sel", 2),
> + GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk",
> + "axi_sel", 3),
> + GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk",
> + "f_f26m_ck", 4),
> + GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
> + "spi_sel", 6),
> + GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
> + "i2c_sel", 7),
> + GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
> + "f_f26m_ck", 8),
> + GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
> + "spi_sel", 9),
> + GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
> + "spi_sel", 10),
> + GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
> + "ssusb_top_xhci_sel", 11),
> + GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
> + "fufs_sel", 12),
> + GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
> + "fufs_sel", 13),
> + GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
> + "axi_sel", 14),
> + GATE_INFRA2(CLK_INFRA_SSPM, "infra_sspm",
> + "sspm_sel", 15),
> + GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
> + "axi_sel", 16),
> + GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
> + "axi_sel", 17),
> + GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
> + "i2c_sel", 18),
> + GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
> + "i2c_sel", 19),
> + GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
> + "i2c_sel", 20),
> + GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
> + "i2c_sel", 21),
> + GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
> + "i2c_sel", 22),
> + GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
> + "i2c_sel", 23),
> + GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
> + "i2c_sel", 24),
> + GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
> + "spi_sel", 25),
> + GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
> + "spi_sel", 26),
> + GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
> + "axi_sel", 27),
> + GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
> + "fufs_sel", 28),
> + GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
> + "faes_ufsfde_sel", 29),
> + GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
> + "fufs_sel", 30),
> + /* INFRA3 */
> + GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
> + "msdc50_0_sel", 0),
> + GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
> + "msdc50_0_sel", 1),
> + GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
> + "msdc50_0_sel", 2),
> + GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
> + "f_f26m_ck", 3),
> + GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
> + "f_f26m_ck", 4),
> + GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
> + "axi_sel", 5),
> + GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
> + "i2c_sel", 6),
> + GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
> + "msdc50_hclk_sel", 7),
> + GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
> + "msdc50_hclk_sel", 8),
> + GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
> + "axi_sel", 16),
> + GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
> + "axi_sel", 17),
> + GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
> + "axi_sel", 18),
> + GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
> + "axi_sel", 19),
> + GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
> + "f_f26m_ck", 20),
> + GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
> + "axi_sel", 21),
> + GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
> + "i2c_sel", 22),
> + GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
> + "i2c_sel", 23),
> + GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
> + "msdc50_0_sel", 24),
> +};
> +
> +static const struct mtk_gate_regs apmixed_cg_regs = {
> + .set_ofs = 0x20,
> + .clr_ofs = 0x20,
> + .sta_ofs = 0x20,
> +};
> +
> +#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
> + _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
> +
> +#define GATE_APMIXED(_id, _name, _parent, _shift) \
> + GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
> +
> +/*
> + * CRITICAL CLOCK:
> + * apmixed_appll26m is the toppest clock gate of all PLLs.
> + */
> +static const struct mtk_gate apmixed_clks[] = {
> + /* AUDIO0 */
> + GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
> + "f_f26m_ck", 4),
> + GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
> + "f_f26m_ck", 5, CLK_IS_CRITICAL),
> + GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
> + "f_f26m_ck", 6),
> + GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
> + "f_f26m_ck", 7),
> + GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
> + "f_f26m_ck", 8),
> + GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
> + "f_f26m_ck", 9),
> + GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
> + "f_f26m_ck", 11),
> + GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
> + "f_f26m_ck", 13),
> + GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
> + "f_f26m_ck", 14),
> + GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
> + "f_f26m_ck", 16),
> + GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
> + "f_f26m_ck", 17),
> +};
> +
> +#define MT8183_PLL_FMAX (3800UL * MHZ)
> +#define MT8183_PLL_FMIN (1500UL * MHZ)
> +
> +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
> + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
> + _pd_shift, _tuner_reg, _tuner_en_reg, \
> + _tuner_en_bit, _pcw_reg, _pcw_shift, \
> + _pcw_chg_reg, _div_table) { \
> + .id = _id, \
> + .name = _name, \
> + .reg = _reg, \
> + .pwr_reg = _pwr_reg, \
> + .en_mask = _en_mask, \
> + .flags = _flags, \
> + .rst_bar_mask = _rst_bar_mask, \
> + .fmax = MT8183_PLL_FMAX, \
> + .fmin = MT8183_PLL_FMIN, \
> + .pcwbits = _pcwbits, \
> + .pcwibits = _pcwibits, \
> + .pd_reg = _pd_reg, \
> + .pd_shift = _pd_shift, \
> + .tuner_reg = _tuner_reg, \
> + .tuner_en_reg = _tuner_en_reg, \
> + .tuner_en_bit = _tuner_en_bit, \
> + .pcw_reg = _pcw_reg, \
> + .pcw_shift = _pcw_shift, \
> + .pcw_chg_reg = _pcw_chg_reg, \
> + .div_table = _div_table, \
> + }
> +
> +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
> + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
> + _pd_shift, _tuner_reg, _tuner_en_reg, \
> + _tuner_en_bit, _pcw_reg, _pcw_shift, \
> + _pcw_chg_reg) \
> + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
> + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
> + _pd_shift, _tuner_reg, _tuner_en_reg, \
> + _tuner_en_bit, _pcw_reg, _pcw_shift, \
> + _pcw_chg_reg, NULL)
> +
> +static const struct mtk_pll_div_table armpll_div_table[] = {
> + { .div = 0, .freq = MT8183_PLL_FMAX },
> + { .div = 1, .freq = 1500 * MHZ },
> + { .div = 2, .freq = 750 * MHZ },
> + { .div = 3, .freq = 375 * MHZ },
> + { .div = 4, .freq = 187500000 },
> + { } /* sentinel */
> +};
> +
> +static const struct mtk_pll_div_table mfgpll_div_table[] = {
> + { .div = 0, .freq = MT8183_PLL_FMAX },
> + { .div = 1, .freq = 1600 * MHZ },
> + { .div = 2, .freq = 800 * MHZ },
> + { .div = 3, .freq = 400 * MHZ },
> + { .div = 4, .freq = 200 * MHZ },
> + { } /* sentinel */
> +};
> +
> +static const struct mtk_pll_data plls[] = {
> + PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
> + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
> + 0x0204, 0, 0, armpll_div_table),
> + PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
> + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
> + 0x0214, 0, 0, armpll_div_table),
> + PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
> + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
> + 0x0294, 0, 0),
> + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
> + HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
> + 0x0224, 0, 0),
> + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
> + HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
> + 0x0234, 0, 0),
> + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
> + 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
> + mfgpll_div_table),
> + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
> + 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
> + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
> + 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
> + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
> + HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
> + 0x0274, 0, 0),
> + PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
> + 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
> + PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
> + 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
> +};
> +
> +static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> +
> + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
> +
> + mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static int clk_mt8183_top_probe(struct platform_device *pdev)
> +{
> + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + void __iomem *base;
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
> +
> + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
> + clk_data);
> +
> + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
> +
> + mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
> + node, &mt8183_clk_lock, clk_data);
> +
> + mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
> + base, &mt8183_clk_lock, clk_data);
> +
> + mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
> + base, &mt8183_clk_lock, clk_data);
> +
> + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static int clk_mt8183_infra_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
> +
> + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static int clk_mt8183_mcu_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> + void __iomem *base;
> + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
> +
> + mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
> + &mt8183_clk_lock, clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8183[] = {
> + {
> + .compatible = "mediatek,mt8183-apmixedsys",
> + .data = clk_mt8183_apmixed_probe,
> + }, {
> + .compatible = "mediatek,mt8183-topckgen",
> + .data = clk_mt8183_top_probe,
> + }, {
> + .compatible = "mediatek,mt8183-infracfg",
> + .data = clk_mt8183_infra_probe,
> + }, {
> + .compatible = "mediatek,mt8183-mcucfg",
> + .data = clk_mt8183_mcu_probe,
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static int clk_mt8183_probe(struct platform_device *pdev)
> +{
> + int (*clk_probe)(struct platform_device *pdev);
> + int r;
> +
> + clk_probe = of_device_get_match_data(&pdev->dev);
> + if (!clk_probe)
> + return -EINVAL;
> +
> + r = clk_probe(pdev);
> + if (r)
> + dev_err(&pdev->dev,
> + "could not register clock provider: %s: %d\n",
> + pdev->name, r);
> +
> + return r;
> +}
> +
> +static struct platform_driver clk_mt8183_drv = {
> + .probe = clk_mt8183_probe,
> + .driver = {
> + .name = "clk-mt8183",
> + .of_match_table = of_match_clk_mt8183,
> + },
> +};
> +
> +static int __init clk_mt8183_init(void)
> +{
> + return platform_driver_register(&clk_mt8183_drv);
> +}
> +
> +arch_initcall(clk_mt8183_init);
> --
> 2.18.0
>
On Fri, Mar 8, 2019 at 2:42 PM Nicolas Boichat <[email protected]> wrote:
>
> )
> On Tue, Mar 5, 2019 at 1:05 PM Weiyi Lu <[email protected]> wrote:
> >
> > Add MT8183 clock support, include topckgen, apmixedsys,
> > infracfg, mcucfg and subsystem clocks.
> >
> > Signed-off-by: Weiyi Lu <[email protected]>
>
> In v1 a while back (https://patchwork.kernel.org/patch/10669765/) I
> was complaining about code duplication between these many files, and
> wondering if we can make simplify a lot of this code.
Okay, we had a discussion on this gerrit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1510921,
and I didn't know the history that having separate clock domains that
we can enable/disable with config options. And the same pattern
already exists on clk-mt2712-*.c, for example.
So, for now:
Reviewed-by: Nicolas Boichat <[email protected]>
Some comment below about how this could be improved, potentially:
> Apart from that:
> Tested-by: Nicolas Boichat <[email protected]>
>
[snip]
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8183-audio.c
> > @@ -0,0 +1,105 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2018 MediaTek Inc.
> > +// Author: Weiyi Lu <[email protected]>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt8183-clk.h>
> > +
> > +static const struct mtk_gate_regs audio0_cg_regs = {
> > + .set_ofs = 0x0,
> > + .clr_ofs = 0x0,
> > + .sta_ofs = 0x0,
> > +};
> > +
> > +static const struct mtk_gate_regs audio1_cg_regs = {
> > + .set_ofs = 0x4,
> > + .clr_ofs = 0x4,
> > + .sta_ofs = 0x4,
> > +};
> > +
> > +#define GATE_AUDIO0(_id, _name, _parent, _shift) \
> > + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
> > + &mtk_clk_gate_ops_no_setclr)
This macro (or variants that end up being equivalent) is repeated 103
times in drivers/clk/mediatek/*. We can probably do better. My
suggestion is to do something like this:
#define GATE_MTK_CLK(reg, _id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, ®##_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr_inv)
and use GATE_MTK_CLK(audio0, ...) in the gate clock arrays.
> > +static int clk_mt8183_audio_probe(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
> > +
> > + mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > + if (r)
> > + return r;
> > +
> > + r = devm_of_platform_populate(&pdev->dev);
> > + if (r)
> > + of_clk_del_provider(node);
> > +
> > + return r;
> > +}
This (almost exact) function is now repeated 33 times in
drivers/clk/mediatek, I think it's really time for a cleanup... Maybe
there should be a common helper in clk-gate.c (or another file, not
sure), that fetches the clocks (and number of clocks from .data field
in the structure below).
> > +static const struct of_device_id of_match_clk_mt8183_audio[] = {
> > + { .compatible = "mediatek,mt8183-audiosys", },
> > + {}
> > +};
[snip]
On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <[email protected]> wrote:
>
> From: Owen Chen <[email protected]>
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new API to handle this hw change with
> a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
> drivers/clk/mediatek/Makefile | 3 +-
> drivers/clk/mediatek/clk-mux.c | 223 +++++++++++++++++++++++++++++++++
> drivers/clk/mediatek/clk-mux.h | 89 +++++++++++++
> 3 files changed, 314 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mux.c
> create mode 100644 drivers/clk/mediatek/clk-mux.h
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index ee4410ff43ab..20cf9eea4171 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
> +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
> +
> obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
> obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
> obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
> diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
> new file mode 100644
> index 000000000000..877a883fa616
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mux.c
> @@ -0,0 +1,223 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <[email protected]>
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/mfd/syscon.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-mux.h"
> +
> +static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
> +{
> + return container_of(hw, struct mtk_clk_mux, hw);
> +}
> +
> +static int mtk_clk_mux_enable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
> + mask, ~mask);
> +}
> +
> +static void mtk_clk_mux_disable(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = BIT(mux->data->gate_shift);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
> +}
> +
> +static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + return regmap_write(mux->regmap, mux->data->clr_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> +
> + regmap_write(mux->regmap, mux->data->set_ofs,
> + BIT(mux->data->gate_shift));
> +}
> +
> +static int mtk_clk_mux_is_enabled(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &val);
> +
> + return (val & BIT(mux->data->gate_shift)) == 0;
> +}
> +
> +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + u32 val;
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &val);
> + val = (val >> mux->data->mux_shift) & mask;
> +
> + return val;
> +}
> +
> +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + unsigned long flags;
Guenter reported the following issue
(https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1524422):
""
The construct conditionally acquiring a spinlock is too complex for
gcc to understand. This results in the following build warning.
drivers/clk/mediatek/clk-mux.c: In function
'mtk_clk_mux_set_parent_lock': ./include/linux/spinlock.h:279:3:
warning: 'flags' may be used uninitialized in this function
Other clock drivers avoid the problem by initializing flags with 0.
Lets do that here as well.
"""
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
> + index << mux->data->mux_shift);
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return 0;
> +}
> +
> +static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
> +{
> + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> + u32 val, orig;
> + unsigned long flags;
Same here.
> +
> + if (mux->lock)
> + spin_lock_irqsave(mux->lock, flags);
> + else
> + __acquire(mux->lock);
> +
> + regmap_read(mux->regmap, mux->data->mux_ofs, &orig);
> + val = (orig & ~(mask << mux->data->mux_shift))
> + | (index << mux->data->mux_shift);
> +
> + if (val != orig) {
> + regmap_write(mux->regmap, mux->data->clr_ofs,
> + mask << mux->data->mux_shift);
> + regmap_write(mux->regmap, mux->data->set_ofs,
> + index << mux->data->mux_shift);
> +
> + if (mux->data->upd_shift >= 0)
> + regmap_write(mux->regmap, mux->data->upd_ofs,
> + BIT(mux->data->upd_shift));
> + }
> +
> + if (mux->lock)
> + spin_unlock_irqrestore(mux->lock, flags);
> + else
> + __release(mux->lock);
> +
> + return 0;
> +}
> +
> +const struct clk_ops mtk_mux_ops = {
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_lock,
> +};
> +
> +const struct clk_ops mtk_mux_clr_set_upd_ops = {
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> +};
> +
> +const struct clk_ops mtk_mux_gate_ops = {
> + .enable = mtk_clk_mux_enable,
> + .disable = mtk_clk_mux_disable,
> + .is_enabled = mtk_clk_mux_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_lock,
> +};
> +
> +const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
> + .enable = mtk_clk_mux_enable_setclr,
> + .disable = mtk_clk_mux_disable_setclr,
> + .is_enabled = mtk_clk_mux_is_enabled,
> + .get_parent = mtk_clk_mux_get_parent,
> + .set_parent = mtk_clk_mux_set_parent_setclr_lock,
> +};
> +
> +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> + struct regmap *regmap,
> + spinlock_t *lock)
> +{
> + struct mtk_clk_mux *clk_mux;
> + struct clk_init_data init;
> + struct clk *clk;
> +
> + clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL);
> + if (!clk_mux)
> + return ERR_PTR(-ENOMEM);
> +
> + init.name = mux->name;
> + init.flags = mux->flags | CLK_SET_RATE_PARENT;
> + init.parent_names = mux->parent_names;
> + init.num_parents = mux->num_parents;
> + init.ops = mux->ops;
> +
> + clk_mux->regmap = regmap;
> + clk_mux->data = mux;
> + clk_mux->lock = lock;
> + clk_mux->hw.init = &init;
> +
> + clk = clk_register(NULL, &clk_mux->hw);
> + if (IS_ERR(clk)) {
> + kfree(clk_mux);
> + return clk;
> + }
> +
> + return clk;
> +}
> +
> +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> + int num, struct device_node *node,
> + spinlock_t *lock,
> + struct clk_onecell_data *clk_data)
> +{
> + struct regmap *regmap;
> + struct clk *clk;
> + int i;
> +
> + regmap = syscon_node_to_regmap(node);
> + if (IS_ERR(regmap)) {
> + pr_err("Cannot find regmap for %pOF: %ld\n", node,
> + PTR_ERR(regmap));
> + return PTR_ERR(regmap);
> + }
> +
> + for (i = 0; i < num; i++) {
> + const struct mtk_mux *mux = &muxes[i];
> +
> + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
> + clk = mtk_clk_register_mux(mux, regmap, lock);
> +
> + if (IS_ERR(clk)) {
> + pr_err("Failed to register clk %s: %ld\n",
> + mux->name, PTR_ERR(clk));
> + continue;
> + }
> +
> + clk_data->clks[mux->id] = clk;
> + }
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> new file mode 100644
> index 000000000000..f5625f4d9e6c
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mux.h
> @@ -0,0 +1,89 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Owen Chen <[email protected]>
> + */
> +
> +#ifndef __DRV_CLK_MTK_MUX_H
> +#define __DRV_CLK_MTK_MUX_H
> +
> +#include <linux/clk-provider.h>
> +
> +struct mtk_clk_mux {
> + struct clk_hw hw;
> + struct regmap *regmap;
> + const struct mtk_mux *data;
> + spinlock_t *lock;
> +};
> +
> +struct mtk_mux {
> + int id;
> + const char *name;
> + const char * const *parent_names;
> + unsigned int flags;
> +
> + u32 mux_ofs;
> + u32 set_ofs;
> + u32 clr_ofs;
> + u32 upd_ofs;
> +
> + u8 mux_shift;
> + u8 mux_width;
> + u8 gate_shift;
> + s8 upd_shift;
> +
> + const struct clk_ops *ops;
> +
> + signed char num_parents;
> +};
> +
> +extern const struct clk_ops mtk_mux_ops;
> +extern const struct clk_ops mtk_mux_clr_set_upd_ops;
> +extern const struct clk_ops mtk_mux_gate_ops;
> +extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
> +
> +#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags, _ops) { \
> + .id = _id, \
> + .name = _name, \
> + .mux_ofs = _mux_ofs, \
> + .set_ofs = _mux_set_ofs, \
> + .clr_ofs = _mux_clr_ofs, \
> + .upd_ofs = _upd_ofs, \
> + .mux_shift = _shift, \
> + .mux_width = _width, \
> + .gate_shift = _gate, \
> + .upd_shift = _upd, \
> + .parent_names = _parents, \
> + .num_parents = ARRAY_SIZE(_parents), \
> + .flags = _flags, \
> + .ops = &_ops, \
> + }
> +
> +#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags) \
> + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd, _flags, \
> + mtk_mux_gate_clr_set_upd_ops)
> +
> +#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _gate, _upd_ofs, _upd) \
> + MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
> + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
> + _width, _gate, _upd_ofs, _upd, \
> + CLK_SET_RATE_PARENT)
> +
> +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> + struct regmap *regmap,
> + spinlock_t *lock);
> +
> +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> + int num, struct device_node *node,
> + spinlock_t *lock,
> + struct clk_onecell_data *clk_data);
> +
> +#endif /* __DRV_CLK_MTK_MUX_H */
> --
> 2.18.0
>
On Tue, 2019-03-05 at 13:05 +0800, Weiyi Lu wrote:
Hi Stephen,
Just gentle ping. Many thanks.
> Resend clock patches from v4 based on v5.0-rc1.
>
> The whole series now is composed of
> a fix for PLL tuner (PATCH 1),
> clock common changes for both MT8183 & MT6765 (PATCH 2-3),
> clock support of MT8183 (PATCH 4-8) and
> resend a clock patch long time ago(PTACH 9).
>
> changes since v4:
> - refine for the fix of PLL tuner(PATCH 1).
> - add configurable pcw_chg_reg for MT8183 and the following IC(PATCH 7).
>
> changes sinve v3:
> - add fix tag.
> - small change of mtk_clk_mux data structure.
> - use of_property_for_each_string to iterate dependent subsys clock of power domain.
> - document critical clocks.
> - reduce some clock register error log.
> - few coding style fix.
>
> changes sinve v2:
> - refine for implementation consistency of mtk clk mux.
> - separate the onoff API into enable/disable API for mtk scpsys.
> - resend a patch about PLL rate changing.
>
> changes since v1:
> - refine for better code quality.
> - some minor bug fix of clock part, like incorrect control address
> and missing clocks.
>
>
(Please trim replies to save me time)
Quoting Nicolas Boichat (2019-03-14 16:21:26)
> On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <[email protected]> wrote:
> > +static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> > + u32 val;
> > +
> > + regmap_read(mux->regmap, mux->data->mux_ofs, &val);
> > + val = (val >> mux->data->mux_shift) & mask;
> > +
> > + return val;
> > +}
> > +
> > +static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 mask = GENMASK(mux->data->mux_width - 1, 0);
> > + unsigned long flags;
>
> Guenter reported the following issue
> (https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1524422):
> ""
> The construct conditionally acquiring a spinlock is too complex for
> gcc to understand. This results in the following build warning.
>
> drivers/clk/mediatek/clk-mux.c: In function
> 'mtk_clk_mux_set_parent_lock': ./include/linux/spinlock.h:279:3:
> warning: 'flags' may be used uninitialized in this function
>
> Other clock drivers avoid the problem by initializing flags with 0.
> Lets do that here as well.
> """
Ok. I'll squash in this fix.
diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
index 877a883fa616..76f9cd039195 100644
--- a/drivers/clk/mediatek/clk-mux.c
+++ b/drivers/clk/mediatek/clk-mux.c
@@ -76,7 +76,7 @@ static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
{
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 mask = GENMASK(mux->data->mux_width - 1, 0);
- unsigned long flags;
+ unsigned long flags = 0;
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
@@ -99,7 +99,7 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
u32 mask = GENMASK(mux->data->mux_width - 1, 0);
u32 val, orig;
- unsigned long flags;
+ unsigned long flags = 0;
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
Quoting Nicolas Boichat (2019-03-07 22:20:27)
> On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <[email protected]> wrote:
> >
> > From: Owen Chen <[email protected]>
> >
> > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> > add a variable to indicate this change and
> > backward-compatible.
> > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
>
> Minor nit: frequency (Stephen I guess you could fix that when applying...)
What's a 1GMhz? Anyway, fixed the typo.
Quoting Weiyi Lu (2019-03-04 21:05:38)
> From: Owen Chen <[email protected]>
>
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
>
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <[email protected]>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
Applied to clk-next
Quoting Weiyi Lu (2019-03-04 21:05:39)
> From: Owen Chen <[email protected]>
>
> On both MT8183 & MT6765, there add "set/clr" register for
> each clkmux setting, and one update register to trigger value change.
> It is designed to prevent read-modify-write racing issue.
> The sw design need to add a new API to handle this hw change with
> a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
Applied to clk-next
Quoting Weiyi Lu (2019-03-04 21:05:40)
> From: Owen Chen <[email protected]>
>
> 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> add a variable to indicate this change and
> backward-compatible.
> 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
> 1.5Ghz, add a variable to indicate platform-dependent.
>
> Signed-off-by: Owen Chen <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
> Acked-by: Sean Wang <[email protected]>
> ---
Applied to clk-next
Quoting Weiyi Lu (2019-03-04 21:05:42)
> Add MT8183 clock dt-bindings, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
Applied to clk-next
Quoting Weiyi Lu (2019-03-04 21:05:43)
> On some Mediatek platforms, there are critical clocks of
> clock gate type.
> To register clock gate with flags CLK_IS_CRITICAL,
> we need to add the flags field in mtk_gate data and register APIs.
>
> Signed-off-by: Weiyi Lu <[email protected]>
This patch doesn't apply, because it's already there via commit
5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate").
Quoting Weiyi Lu (2019-03-04 21:05:44)
> In previous MediaTek PLL design, it assumes the pcw change control
> is always on the CON1 register.
> However, the pcw change bit on MT8183 was moved onto CON0 because
> the the PCW length of audio PLLs are extended to 32-bit.
> Add configurable pcw_chg_reg to set the pcw change control register
> address or using the default control register CON1 if without
> setting in pll data.
>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
Applied to clk-next
Quoting Nicolas Boichat (2019-03-08 06:46:01)
>
> > > +
> > > +#define GATE_AUDIO0(_id, _name, _parent, _shift) \
> > > + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
> > > + &mtk_clk_gate_ops_no_setclr)
>
> This macro (or variants that end up being equivalent) is repeated 103
> times in drivers/clk/mediatek/*. We can probably do better. My
> suggestion is to do something like this:
> #define GATE_MTK_CLK(reg, _id, _name, _parent, _shift) \
> GATE_MTK(_id, _name, _parent, ®##_cg_regs, _shift, \
> &mtk_clk_gate_ops_setclr_inv)
>
> and use GATE_MTK_CLK(audio0, ...) in the gate clock arrays.
Feel free to send patches.
>
> > > +static int clk_mt8183_audio_probe(struct platform_device *pdev)
> > > +{
> > > + struct clk_onecell_data *clk_data;
> > > + int r;
> > > + struct device_node *node = pdev->dev.of_node;
> > > +
> > > + clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
> > > +
> > > + mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
> > > + clk_data);
> > > +
> > > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > > + if (r)
> > > + return r;
> > > +
> > > + r = devm_of_platform_populate(&pdev->dev);
> > > + if (r)
> > > + of_clk_del_provider(node);
> > > +
> > > + return r;
> > > +}
>
> This (almost exact) function is now repeated 33 times in
> drivers/clk/mediatek, I think it's really time for a cleanup... Maybe
> there should be a common helper in clk-gate.c (or another file, not
> sure), that fetches the clocks (and number of clocks from .data field
> in the structure below).
>
Yeah that would be great. I only tried to fix the problem where mtk
has this duplicate code that probes platform drivers and finds things
from it. See my branch on clk.git
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-mtk-of-plat-probe
Quoting Weiyi Lu (2019-03-04 21:05:46)
> From: James Liao <[email protected]>
>
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
>
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
>
> Signed-off-by: James Liao <[email protected]>
> Acked-by: Michael Turquette <[email protected]>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
Applied to clk-next
Quoting Weiyi Lu (2019-03-04 21:05:45)
> Add MT8183 clock support, include topckgen, apmixedsys,
> infracfg, mcucfg and subsystem clocks.
>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
Applied to clk-next
On Thu, 2019-04-11 at 13:19 -0700, Stephen Boyd wrote:
> Quoting Weiyi Lu (2019-03-04 21:05:43)
> > On some Mediatek platforms, there are critical clocks of
> > clock gate type.
> > To register clock gate with flags CLK_IS_CRITICAL,
> > we need to add the flags field in mtk_gate data and register APIs.
> >
> > Signed-off-by: Weiyi Lu <[email protected]>
>
> This patch doesn't apply, because it's already there via commit
> 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate").
>
Got it, but just catch a minor defect by 5a1cc4c27ad2 ("clk: mediatek:
Add flags to mtk_gate").
init.flags = CLK_SET_RATE_PARENT;
...
init.flags = flags;
I'll send a fix later.
Thanks for the help on the MT8183 clk series.
>
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