2019-08-26 14:51:04

by Christoph Hellwig

Subject: cleanup the dma_pgprot handling v2

Hi all,

this series replaces the arch_dma_mmap_pgprot hooks with the
simpler pgprot_dmacoherent as used by the arm code already and
cleans up various bits around that area.

Changes since v1:
- improve the new arm64 comment
- keep the special DMA_ATTR_WRITE_COMBINE handling for mips and
document it

2019-08-26 14:51:08

by Christoph Hellwig

Subject: [PATCH 1/6] unicore32: remove the unused pgprot_dmacoherent define

Signed-off-by: Christoph Hellwig <[email protected]>
---
arch/unicore32/include/asm/pgtable.h | 2 --
1 file changed, 2 deletions(-)

diff --git a/arch/unicore32/include/asm/pgtable.h b/arch/unicore32/include/asm/pgtable.h
index 9492aa304f03..126e961a8cb0 100644
--- a/arch/unicore32/include/asm/pgtable.h
+++ b/arch/unicore32/include/asm/pgtable.h
@@ -198,8 +198,6 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
__pgprot(pgprot_val(prot) & ~PTE_CACHEABLE)
#define pgprot_writecombine(prot) \
__pgprot(pgprot_val(prot) & ~PTE_CACHEABLE)
-#define pgprot_dmacoherent(prot) \
- __pgprot(pgprot_val(prot) & ~PTE_CACHEABLE)

#define pmd_none(pmd) (!pmd_val(pmd))
#define pmd_present(pmd) (pmd_val(pmd) & PMD_PRESENT)
--
2.20.1

2019-08-26 14:51:18

by Christoph Hellwig

Subject: [PATCH 6/6] MIPS: document mixing "slightly different CCAs"

Based on an email from Paul Burton, quoting section 4.8 "Cacheability and
Coherency Attributes and Access Types" of "MIPS Architecture Volume 1:
Introduction to the MIPS32 Architecture" (MD00080, revision 6.01).

Signed-off-by: Christoph Hellwig <[email protected]>
---
arch/mips/Kconfig | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fc88f68ea1ee..aff1cadeea43 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1119,6 +1119,13 @@ config DMA_PERDEV_COHERENT

config DMA_NONCOHERENT
bool
+ #
+ # MIPS allows mixing "slightly different" Cacheability and Coherency
+ # Attribute bits. It is believed that the uncached access through
+ # KSEG1 and the implementation specific "uncached accelerated" used
+ # by pgprot_writcombine can be mixed, and the latter sometimes provides
+ # significant advantages.
+ #
select ARCH_HAS_DMA_WRITE_COMBINE
select ARCH_HAS_SYNC_DMA_FOR_DEVICE
select ARCH_HAS_UNCACHED_SEGMENT
--
2.20.1

2019-08-27 10:04:52

by Paul Burton

Subject: Re: [PATCH 6/6] MIPS: document mixing "slightly different CCAs"

Hi Christoph,

On Mon, Aug 26, 2019 at 03:25:53PM +0200, Christoph Hellwig wrote:
> Based on an email from Paul Burton, quoting section 4.8 "Cacheability and
> Coherency Attributes and Access Types" of "MIPS Architecture Volume 1:
> Introduction to the MIPS32 Architecture" (MD00080, revision 6.01).
>
> Signed-off-by: Christoph Hellwig <[email protected]>

Acked-by: Paul Burton <[email protected]>

Thanks,
Paul

> ---
> arch/mips/Kconfig | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index fc88f68ea1ee..aff1cadeea43 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -1119,6 +1119,13 @@ config DMA_PERDEV_COHERENT
>
> config DMA_NONCOHERENT
> bool
> + #
> + # MIPS allows mixing "slightly different" Cacheability and Coherency
> + # Attribute bits. It is believed that the uncached access through
> + # KSEG1 and the implementation specific "uncached accelerated" used
> + # by pgprot_writcombine can be mixed, and the latter sometimes provides
> + # significant advantages.
> + #
> select ARCH_HAS_DMA_WRITE_COMBINE
> select ARCH_HAS_SYNC_DMA_FOR_DEVICE
> select ARCH_HAS_UNCACHED_SEGMENT
> --
> 2.20.1
>

2019-08-29 15:29:35

by Christoph Hellwig

Subject: Re: cleanup the dma_pgprot handling v2

I've pulled this into the dma-mapping for-next tree now.