2021-03-26 15:00:25

by Bartosz Dudziak

[permalink] [raw]
Subject: [PATCH 0/5] Samsung Galaxy S III Neo Initial DTS

This series of patches enables to boot MSM8226 SoC in Samsung Galaxy S III Neo
mobile phone. Implemented clocks are on top of MSM8974 GCC driver because there
is really little difference between them. UART serial communication is working.
I have working patches for the regulators, EMMC, multithreading and Wifi for
this device but they are not clean and ready to submit.

Bartosz Dudziak (5):
dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings
clk: qcom: gcc: Add support for Global Clock controller found on
MSM8226
arm: dts: qcom: Add support for MSM8226 SoC
dt-bindings: arm: qcom: Document MSM8226 SoC binding
arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo
phone

.../devicetree/bindings/arm/qcom.yaml | 6 +
.../devicetree/bindings/clock/qcom,gcc.yaml | 13 +-
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/qcom-msm8226-samsung-s3ve3g.dts | 25 +++
arch/arm/boot/dts/qcom-msm8226.dtsi | 152 ++++++++++++++
drivers/clk/qcom/gcc-msm8974.c | 185 ++++++++++++++++--
6 files changed, 364 insertions(+), 18 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi

--
2.25.1


2021-03-26 15:00:25

by Bartosz Dudziak

[permalink] [raw]
Subject: [PATCH 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226

Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies
which are different in this older chip. Register all the clocks to the
framework for the clients to be able to request for them.

Signed-off-by: Bartosz Dudziak <[email protected]>
---
drivers/clk/qcom/gcc-msm8974.c | 185 ++++++++++++++++++++++++++++++---
1 file changed, 171 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 740d3c44c0..06cd669e10 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -3,16 +3,13 @@
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*/

-#include <linux/kernel.h>
-#include <linux/bitops.h>
+#include <linux/clk-provider.h>
#include <linux/err.h>
-#include <linux/platform_device.h>
+#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/of.h>
#include <linux/of_device.h>
-#include <linux/clk-provider.h>
+#include <linux/of.h>
#include <linux/regmap.h>
-#include <linux/reset-controller.h>

#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
@@ -719,6 +716,12 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
},
};

+static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = {
+ F(50000000, P_GPLL0, 12, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ { }
+};
+
static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
F(50000000, P_GPLL0, 12, 0, 0),
F(75000000, P_GPLL0, 8, 0, 0),
@@ -761,6 +764,11 @@ static struct clk_rcg2 ce2_clk_src = {
},
};

+static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
static const struct freq_tbl ftbl_gcc_gp_clk[] = {
F(4800000, P_XO, 4, 0, 0),
F(6000000, P_GPLL0, 10, 1, 10),
@@ -1955,6 +1963,10 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mss_q6_bimc_axi_clk",
+ .parent_names = (const char *[]){
+ "system_noc_clk_src",
+ },
+ .num_parents = 1,
.ops = &clk_branch2_ops,
},
},
@@ -1993,6 +2005,20 @@ static struct clk_branch gcc_pdm_ahb_clk = {
},
};

+static struct clk_branch gcc_pdm_xo4_clk = {
+ .halt_reg = 0x0cc8,
+ .clkr = {
+ .enable_reg = 0x0cc8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_xo4_clk",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x0d04,
.halt_check = BRANCH_HALT_VOTED,
@@ -2430,6 +2456,121 @@ static struct gdsc usb_hs_hsic_gdsc = {
.pwrsts = PWRSTS_OFF_ON,
};

+static struct clk_regmap *gcc_msm8226_clocks[] = {
+ [GPLL0] = &gpll0.clkr,
+ [GPLL0_VOTE] = &gpll0_vote,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL1_VOTE] = &gpll1_vote,
+ [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
+ [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
+ [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+ [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+ [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
+ [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
+ [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+ [CE1_CLK_SRC] = &ce1_clk_src.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
+ [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
+ [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
+ [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
+ [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
+ [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+ [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
+ [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
+ [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
+ [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
+ [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+ [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
+ [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
+ [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
+ [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
+ [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
+ [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
+ [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
+ [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
+ [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
+};
+
+static const struct qcom_reset_map gcc_msm8226_resets[] = {
+ [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
+ [GCC_USB_HS_BCR] = { 0x0480 },
+ [GCC_USB2A_PHY_BCR] = { 0x04a8 },
+};
+
+static struct gdsc *gcc_msm8226_gdscs[] = {
+ [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
+};
+
+static const struct regmap_config gcc_msm8226_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1a80,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_msm8226_desc = {
+ .config = &gcc_msm8226_regmap_config,
+ .clks = gcc_msm8226_clocks,
+ .num_clks = ARRAY_SIZE(gcc_msm8226_clocks),
+ .resets = gcc_msm8226_resets,
+ .num_resets = ARRAY_SIZE(gcc_msm8226_resets),
+ .gdscs = gcc_msm8226_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs),
+};
+
static struct clk_regmap *gcc_msm8974_clocks[] = {
[GPLL0] = &gpll0.clkr,
[GPLL0_VOTE] = &gpll0_vote,
@@ -2682,13 +2823,22 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
};

static const struct of_device_id gcc_msm8974_match_table[] = {
- { .compatible = "qcom,gcc-msm8974" },
- { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL },
- { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL },
+ { .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc },
+ { .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc },
+ { .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc },
+ { .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);

+static void msm8226_clock_override(void)
+{
+ ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226;
+ gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
+ gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
+ gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
+}
+
static void msm8974_pro_clock_override(void)
{
sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
@@ -2708,16 +2858,19 @@ static int gcc_msm8974_probe(struct platform_device *pdev)
{
int ret;
struct device *dev = &pdev->dev;
- bool pro;
+ struct regmap *regmap;
const struct of_device_id *id;

id = of_match_device(gcc_msm8974_match_table, dev);
if (!id)
return -ENODEV;
- pro = !!(id->data);

- if (pro)
- msm8974_pro_clock_override();
+ if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) {
+ if (id->data == &gcc_msm8226_desc)
+ msm8226_clock_override();
+ else
+ msm8974_pro_clock_override();
+ }

ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
if (ret)
@@ -2727,7 +2880,11 @@ static int gcc_msm8974_probe(struct platform_device *pdev)
if (ret)
return ret;

- return qcom_cc_probe(pdev, &gcc_msm8974_desc);
+ regmap = qcom_cc_map(pdev, id->data);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ return qcom_cc_really_probe(pdev, id->data, regmap);
}

static struct platform_driver gcc_msm8974_driver = {
--
2.25.1

2021-03-26 15:00:34

by Bartosz Dudziak

[permalink] [raw]
Subject: [PATCH 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding

Document the MSM8226 SoC device-tree binding.

Signed-off-by: Bartosz Dudziak <[email protected]>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 11ec349d56..73902ce46f 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -31,6 +31,7 @@ description: |
ipq6018
ipq8074
mdm9615
+ msm8226
msm8916
msm8974
msm8992
@@ -111,6 +112,11 @@ properties:
- qcom,apq8084-sbc
- const: qcom,apq8084

+ - items:
+ - enum:
+ - samsung,s3ve3g
+ - const: qcom,msm8226
+
- items:
- enum:
- qcom,msm8960-cdp
--
2.25.1

2021-03-26 15:02:35

by Bartosz Dudziak

[permalink] [raw]
Subject: [PATCH 3/5] arm: dts: qcom: Add support for MSM8226 SoC

This patch adds basic device tree support for MSM8226 SoC which belongs
to the Snapdragon 400 family. For now, this file adds the basic nodes
like gcc, pinctrl and other required configuration for booting up to
the serial console.

Signed-off-by: Bartosz Dudziak <[email protected]>
---
arch/arm/boot/dts/qcom-msm8226.dtsi | 152 ++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi

diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
new file mode 100644
index 0000000000..81bb19398e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8974.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Qualcomm Technologies, Inc. MSM8226";
+ compatible = "qcom,msm8226";
+ interrupt-parent = <&intc>;
+
+ chosen { };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x0>;
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
+
+ intc: [email protected] {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xF9000000 0x1000>,
+ <0xF9002000 0x1000>;
+ };
+
+ gcc: [email protected] {
+ compatible = "qcom,gcc-msm8226";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0xfc400000 0x4000>;
+ };
+
+ msmgpio: [email protected] {
+ compatible = "qcom,msm8226-pinctrl";
+ reg = <0xfd510000 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&msmgpio 0 0 117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ blsp1_uart3: [email protected] {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991f000 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ [email protected] {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
+
+ [email protected] {
+ compatible = "qcom,prng";
+ reg = <0xf9bff000 0x200>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
+ [email protected] {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xf9020000 0x1000>;
+ clock-frequency = <19200000>;
+
+ [email protected] {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9021000 0x1000>,
+ <0xf9022000 0x1000>;
+ };
+
+ [email protected] {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9023000 0x1000>;
+ status = "disabled";
+ };
+
+ [email protected] {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9024000 0x1000>;
+ status = "disabled";
+ };
+
+ [email protected] {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9025000 0x1000>;
+ status = "disabled";
+ };
+
+ [email protected] {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9026000 0x1000>;
+ status = "disabled";
+ };
+
+ [email protected] {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9027000 0x1000>;
+ status = "disabled";
+ };
+
+ [email protected] {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf9028000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 2
+ (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3
+ (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4
+ (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1
+ (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+};
--
2.25.1

2021-03-26 15:02:36

by Bartosz Dudziak

[permalink] [raw]
Subject: [PATCH 5/5] arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone

This DTS has support for the Samsung Galaxy S III Neo (codenamed s3ve3g)
phone. Initial version have just a working serial console.

Signed-off-by: Bartosz Dudziak <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/qcom-msm8226-samsung-s3ve3g.dts | 25 +++++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8e5d4ab4e7..080ff37fdb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -920,6 +920,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-ipq8064-rb3011.dtb \
+ qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
new file mode 100644
index 0000000000..4790077962
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include "qcom-msm8226.dtsi"
+
+/ {
+ model = "Samsung Galaxy S III Neo";
+ compatible = "samsung,s3ve3g", "qcom,msm8226";
+
+ aliases {
+ serial0 = &blsp1_uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&soc {
+ [email protected] {
+ status = "ok";
+ };
+};
--
2.25.1

2021-03-26 18:22:53

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH 3/5] arm: dts: qcom: Add support for MSM8226 SoC

Quoting Bartosz Dudziak (2021-03-26 07:58:14)
> This patch adds basic device tree support for MSM8226 SoC which belongs

git grep "This patch" -- Documentation/process/submitting-patches.rst

> to the Snapdragon 400 family. For now, this file adds the basic nodes
> like gcc, pinctrl and other required configuration for booting up to
> the serial console.
>
> Signed-off-by: Bartosz Dudziak <[email protected]>
> ---
> arch/arm/boot/dts/qcom-msm8226.dtsi | 152 ++++++++++++++++++++++++++++
> 1 file changed, 152 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi
>
> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
> new file mode 100644
> index 0000000000..81bb19398e
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8974.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "Qualcomm Technologies, Inc. MSM8226";
> + compatible = "qcom,msm8226";
> + interrupt-parent = <&intc>;
> +
> + chosen { };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0x0>;
> + };
> +
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "simple-bus";
> +
> + intc: [email protected] {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0xF9000000 0x1000>,

lowercase hex please.

> + <0xF9002000 0x1000>;
> + };
> +
> + gcc: [email protected] {
> + compatible = "qcom,gcc-msm8226";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0xfc400000 0x4000>;
> + };
> +
> + msmgpio: [email protected] {
> + compatible = "qcom,msm8226-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&msmgpio 0 0 117>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + blsp1_uart3: [email protected] {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0xf991f000 0x1000>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + [email protected] {
> + compatible = "qcom,pshold";
> + reg = <0xfc4ab000 0x4>;
> + };
> +
> + [email protected] {
> + compatible = "qcom,prng";
> + reg = <0xf9bff000 0x200>;
> + clocks = <&gcc GCC_PRNG_AHB_CLK>;
> + clock-names = "core";
> + };
> +
> + [email protected] {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0xf9020000 0x1000>;
> + clock-frequency = <19200000>;

Can you remove this clock-frequency property? Hopefully the firmware is
setting this frequency properly so the driver can read it out of the
registers instead of DT.

> +
> + [email protected] {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9021000 0x1000>,
> + <0xf9022000 0x1000>;
> + };
> +
> + [email protected] {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9023000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9024000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9025000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9026000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9027000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9028000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 2
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;

Same frequency comment.

> + };
> +};

2021-03-26 18:25:47

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226

Quoting Bartosz Dudziak (2021-03-26 07:58:13)
> Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies
> which are different in this older chip. Register all the clocks to the
> framework for the clients to be able to request for them.

Alphabet sort includes? Preferably do that in a different patch.

>
> Signed-off-by: Bartosz Dudziak <[email protected]>
> ---
> drivers/clk/qcom/gcc-msm8974.c | 185 ++++++++++++++++++++++++++++++---
> 1 file changed, 171 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
> index 740d3c44c0..06cd669e10 100644
> --- a/drivers/clk/qcom/gcc-msm8974.c
> +++ b/drivers/clk/qcom/gcc-msm8974.c
> @@ -3,16 +3,13 @@
> * Copyright (c) 2013, The Linux Foundation. All rights reserved.
> */
>
> -#include <linux/kernel.h>
> -#include <linux/bitops.h>
> +#include <linux/clk-provider.h>
> #include <linux/err.h>
> -#include <linux/platform_device.h>
> +#include <linux/kernel.h>
> #include <linux/module.h>
> -#include <linux/of.h>
> #include <linux/of_device.h>
> -#include <linux/clk-provider.h>
> +#include <linux/of.h>
> #include <linux/regmap.h>
> -#include <linux/reset-controller.h>
>
> #include <dt-bindings/clock/qcom,gcc-msm8974.h>
> #include <dt-bindings/reset/qcom,gcc-msm8974.h>
> @@ -2727,7 +2880,11 @@ static int gcc_msm8974_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> - return qcom_cc_probe(pdev, &gcc_msm8974_desc);
> + regmap = qcom_cc_map(pdev, id->data);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + return qcom_cc_really_probe(pdev, id->data, regmap);

Is this doing anything? I think qcom_cc_probe(pdev, id->data) should
work?

2021-03-27 18:42:29

by Rob Herring

[permalink] [raw]
Subject: Re: [PATCH 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding

On Fri, 26 Mar 2021 15:58:15 +0100, Bartosz Dudziak wrote:
> Document the MSM8226 SoC device-tree binding.
>
> Signed-off-by: Bartosz Dudziak <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>

Acked-by: Rob Herring <[email protected]>

2021-03-29 00:53:41

by Rong Chen

[permalink] [raw]
Subject: Re: [PATCH 5/5] arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone

Hi Bartosz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next v5.12-rc4 next-20210326]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Bartosz-Dudziak/Samsung-Galaxy-S-III-Neo-Initial-DTS/20210326-230134
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
:::::: branch date: 24 hours ago
:::::: commit date: 24 hours ago
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce: make ARCH=arm dtbs_check

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>


dtcheck warnings: (new ones prefixed by >>)
>> arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0]]}
From schema: /usr/local/lib/python3.9/dist-packages/dtschema/schemas/root-node.yaml

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]

2021-03-30 03:42:59

by Bjorn Andersson

[permalink] [raw]
Subject: Re: [PATCH 3/5] arm: dts: qcom: Add support for MSM8226 SoC

On Fri 26 Mar 09:58 CDT 2021, Bartosz Dudziak wrote:

> This patch adds basic device tree support for MSM8226 SoC which belongs
> to the Snapdragon 400 family. For now, this file adds the basic nodes
> like gcc, pinctrl and other required configuration for booting up to
> the serial console.
>
> Signed-off-by: Bartosz Dudziak <[email protected]>
> ---
> arch/arm/boot/dts/qcom-msm8226.dtsi | 152 ++++++++++++++++++++++++++++
> 1 file changed, 152 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi
>
> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
> new file mode 100644
> index 0000000000..81bb19398e
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0

Can you please make this BSD license?

> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-msm8974.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "Qualcomm Technologies, Inc. MSM8226";
> + compatible = "qcom,msm8226";

model and compatible should always be specified in the .dts, so the ones
specified here would be overwritten. So drop them here.

> + interrupt-parent = <&intc>;
> +
> + chosen { };
> +
> + memory {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0x0>;
> + };
> +
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "simple-bus";
> +
> + intc: [email protected] {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0xF9000000 0x1000>,
> + <0xF9002000 0x1000>;
> + };
> +
> + gcc: [email protected] {
> + compatible = "qcom,gcc-msm8226";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + reg = <0xfc400000 0x4000>;
> + };
> +
> + msmgpio: [email protected] {

Rename the label "tlmm"

> + compatible = "qcom,msm8226-pinctrl";
> + reg = <0xfd510000 0x4000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&msmgpio 0 0 117>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + blsp1_uart3: [email protected] {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0xf991f000 0x1000>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + [email protected] {
> + compatible = "qcom,pshold";
> + reg = <0xfc4ab000 0x4>;
> + };
> +
> + [email protected] {
> + compatible = "qcom,prng";
> + reg = <0xf9bff000 0x200>;
> + clocks = <&gcc GCC_PRNG_AHB_CLK>;
> + clock-names = "core";
> + };
> +
> + [email protected] {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";

It's nice to have compatible & reg first in the nodes.

Regards,
Bjorn

> + reg = <0xf9020000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + [email protected] {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9021000 0x1000>,
> + <0xf9022000 0x1000>;
> + };
> +
> + [email protected] {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9023000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9024000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9025000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9026000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9027000 0x1000>;
> + status = "disabled";
> + };
> +
> + [email protected] {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xf9028000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 2
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1
> + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
> + };
> +};
> --
> 2.25.1
>