2021-06-11 11:49:57

by Jianjun Wang

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Subject: [PATCH v2 0/2] PCI: mediatek-gen3: Add support for disable dvfsrc

These series patches add support for disable dvfsrc voltage request.

Changes in v2:
Fix typo.

Jianjun Wang (2):
dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc
voltage request
PCI: mediatek-gen3: Add support for disable dvfsrc voltage request

.../bindings/pci/mediatek-pcie-gen3.yaml | 8 +++++
drivers/pci/controller/pcie-mediatek-gen3.c | 31 +++++++++++++++++++
2 files changed, 39 insertions(+)

--
2.25.1


2021-06-11 11:52:23

by Jianjun Wang

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Subject: [PATCH v2 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request

Add property to disable dvfsrc voltage request, if this property
is presented, we assume that the requested voltage is always
higher enough to keep the PCIe controller active.

Signed-off-by: Jianjun Wang <[email protected]>
Reviewed-by: Qizhong Cheng <[email protected]>
Tested-by: Qizhong Cheng <[email protected]>
---
.../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index e7b1f9892da4..3e26c032cea9 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -96,6 +96,12 @@ properties:
phys:
maxItems: 1

+ disable-dvfsrc-vlt-req:
+ description: Disable dvfsrc voltage request, if this property is presented,
+ we assume that the requested voltage is always higher enough to keep
+ the PCIe controller active.
+ type: boolean
+
'#interrupt-cells':
const: 1

@@ -166,6 +172,8 @@ examples:
<&infracfg_rst 3>;
reset-names = "phy", "mac";

+ disable-dvfsrc-vlt-req;
+
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
--
2.25.1

2021-06-11 11:53:02

by Jianjun Wang

[permalink] [raw]
Subject: [PATCH v2 2/2] PCI: mediatek-gen3: Add support for disable dvfsrc voltage request

PCIe Gen3 PHY layer cannot work properly when the requested voltage
is lower than a specific level(e.g. 0.55V, it's depends on
the chip manufacturing process).

When the dvfsrc feature is implemented, the requested voltage
may be reduced to a lower level in suspend mode, hence that
the MAC layer will assert a HW signal to request the dvfsrc
to raise voltage to normal mode, and it will wait the voltage
ready signal from dvfsrc to decide if the LTSSM can start normally.

When the dvfsrc feature is not implemented, the MAC layer still
assert the voltage request to dvfsrc when exit suspend mode,
but will not receive the voltage ready signal, in this case,
the LTSSM cannot start normally, and the PCIe link will be failed.

Add support for disable dvfsrc voltage request, if the property of
"disable-dvfsrc-vlt-req" is presented in device node, we assume that
the requested voltage is always higher enough to keep the PCIe Gen3
PHY active, and the voltage request to dvfsrc should be disabled.

Signed-off-by: Jianjun Wang <[email protected]>
Reviewed-by: Qizhong Cheng <[email protected]>
Tested-by: Qizhong Cheng <[email protected]>
---
drivers/pci/controller/pcie-mediatek-gen3.c | 31 +++++++++++++++++++++
1 file changed, 31 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 3c5b97716d40..b3e442bc4c8f 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -68,6 +68,9 @@
#define PCIE_MSI_SET_ENABLE_REG 0x190
#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)

+#define PCIE_MISC_CTRL_REG 0x348
+#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1)
+
#define PCIE_MSI_SET_BASE_REG 0xc00
#define PCIE_MSI_SET_OFFSET 0x10
#define PCIE_MSI_SET_STATUS_OFFSET 0x04
@@ -297,6 +300,34 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
val &= ~PCIE_INTX_ENABLE;
writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);

+ /*
+ * PCIe Gen3 PHY layer can not work properly when the requested voltage
+ * is lower than a specific level(e.g. 0.55V, it's depends on
+ * the chip manufacturing process).
+ *
+ * When the dvfsrc feature is implemented, the requested voltage
+ * may be reduced to a lower level in suspend mode, hence that
+ * the MAC layer will assert a HW signal to request the dvfsrc
+ * to raise voltage to normal mode, and it will wait the voltage
+ * ready signal from dvfsrc to decide if the LTSSM can start normally.
+ *
+ * When the dvfsrc feature is not implemented, the MAC layer still
+ * assert the voltage request to dvfsrc when exit suspend mode,
+ * but will not get the voltage ready signal, in this case, the LTSSM
+ * cannot start normally, and the PCIe link will be failed.
+ *
+ * If the property of "disable-dvfsrc-vlt-req" is presented
+ * in device node, we assume that the requested voltage is always
+ * higher enough to keep the PCIe Gen3 PHY active, and the voltage
+ * request to dvfsrc should be disabled.
+ */
+ val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG);
+ val &= ~PCIE_DISABLE_DVFSRC_VLT_REQ;
+ if (of_property_read_bool(port->dev->of_node, "disable-dvfsrc-vlt-req"))
+ val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
+
+ writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG);
+
/* Assert all reset signals */
val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
--
2.25.1