2022-03-28 22:46:05

by Serge Semin

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Subject: [PATCH 0/4] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes

This patchset is an initial one in the series created in the framework
of my Baikal-T1 PCIe/eDMA-related work:

[1: In-progress] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
Link: --you are looking at it--
[2: Stalling] PCI: dwc: Various fixes and cleanups
Link: --being submitted afterwards--
[3: Stalling] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
Link: --being submitted afterwards--
[4: Stalling] dmaengine: dw-edma: Add RP/EP local DMA controllers support
Link: --being submitted afterwards--

Since some of the patches in the later patchsets depend on modifications
introduced here @Bjorn could you please merge this series through your
PCIe subsystem repo? After getting all the required ack'es of course.

Short summary regarding this patchset. A few more modifications are
introduced here to finally finish the Baikal-T1 CCU unit support up and
prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
all it turned out I specified wrong DW xGMAC PTP reference clock divider
in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
joint xGMAC Ref and PTP clock instead of having them separately defined.
The SoC manual describes these clocks as separate fixed clock wrappers.
Finally in order to close the SoC clock/reset support up we need to add
the DDR and PCIe interfaces reset controls support. It's done in two
steps. First I've moved the reset-controls-related code into a dedicated
module. Then the DDR/PCIe reset-control functionality is added.

Signed-off-by: Serge Semin <[email protected]>
Cc: Alexey Malahov <[email protected]>
Cc: Pavel Parkhomenko <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: "Krzysztof WilczyƄski" <[email protected]>
Cc: Thomas Bogendoerfer <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]

Serge Semin (4):
clk: baikal-t1: Fix invalid xGMAC PTP clock divider
clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
clk: baikal-t1: Move reset-controls code into a dedicated module
clk: baikal-t1: Add DDR/PCIe directly controlled resets support

drivers/clk/baikal-t1/Kconfig | 12 +-
drivers/clk/baikal-t1/Makefile | 1 +
drivers/clk/baikal-t1/ccu-div.c | 1 +
drivers/clk/baikal-t1/ccu-div.h | 6 +
drivers/clk/baikal-t1/ccu-rst.c | 373 ++++++++++++++++++++++++++++
drivers/clk/baikal-t1/ccu-rst.h | 64 +++++
drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
include/dt-bindings/reset/bt1-ccu.h | 9 +
8 files changed, 482 insertions(+), 86 deletions(-)
create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
create mode 100644 drivers/clk/baikal-t1/ccu-rst.h


2022-03-28 22:58:10

by Serge Semin

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Subject: [PATCH 2/4] clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent

Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC
PTP clocks are generated by two different wrappers with the same constant
divider thus each producing a 156.25 MHz signal. But for some reason both
of these clock sources are gated by a single switch-flag in the CCU
registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks
handled independently we need to define a shared parental gate so the base
clock signal would be switched off only if both of the child-clocks are

Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <[email protected]>
drivers/clk/baikal-t1/ccu-div.c | 1 +
drivers/clk/baikal-t1/ccu-div.h | 6 ++++++
drivers/clk/baikal-t1/clk-ccu-div.c | 8 +++++---
3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c
index 4062092d67f9..bbfa3526ee10 100644
--- a/drivers/clk/baikal-t1/ccu-div.c
+++ b/drivers/clk/baikal-t1/ccu-div.c
@@ -579,6 +579,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
goto err_free_div;
parent_data.fw_name = div_init->parent_name;
+ parent_data.name = div_init->parent_name;
hw_init.parent_data = &parent_data;
hw_init.num_parents = 1;

diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h
index 795665caefbd..81fc26be6e75 100644
--- a/drivers/clk/baikal-t1/ccu-div.h
+++ b/drivers/clk/baikal-t1/ccu-div.h
@@ -13,6 +13,12 @@
#include <linux/bits.h>
#include <linux/of.h>

+ * CCU Divider private clock IDs
+ * @CCU_SYS_INT_CLK: Internal CCU system clock
+ */
+#define CCU_SYS_INT_CLK -1
* CCU Divider private flags
* @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index ea77eec40ddd..e544129a7543 100644
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -204,10 +204,12 @@ static const struct ccu_div_info sys_info[] = {
"eth_clk", CCU_SYS_GMAC1_BASE, 5),
CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
"eth_clk", 10),
- CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
- "eth_clk", CCU_SYS_XGMAC_BASE, 8),
+ CCU_DIV_GATE_INFO(CCU_SYS_INT_CLK, "sys_xgmac_clk",
+ "eth_clk", CCU_SYS_XGMAC_BASE, 1),
+ CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
+ "sys_xgmac_clk", 8),
- "eth_clk", 8),
+ "sys_xgmac_clk", 8),
"eth_clk", CCU_SYS_USB_BASE, 10),