Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.
Changelog:
v1 -> v2: fix printk formating
v2 -> v3:
* replace "microsemi" with "microchip"
* replace prefix "microsemi_fpga_" with "mpf_"
* more sensible .compatible and .name strings
* remove unused defines STATUS_SPI_VIOLATION and STATUS_SPI_ERROR
v3 -> v4: fix unused variable warning
Put 'mpf_of_ids' definition under conditional compilation, so it
would not hang unused if CONFIG_OF is not enabled.
v4 -> v5:
* prefix defines with MPF_
* mdelay() -> usleep_range()
* formatting fixes
* add DT bindings doc
* rework fpga_manager_ops.write() to fpga_manager_ops.write_sg()
We can't parse image header in write_init() because image header
size is not known beforehand. Thus parsing need to be done in
fpga_manager_ops.write() callback, but fpga_manager_ops.write()
also need to be reenterable. On the other hand,
fpga_manager_ops.write_sg() is called once. Thus, rework usage of
write() callback to write_sg().
v5 -> v6: fix patch applying
I forgot to clean up unrelated local changes which lead to error on
patch 0001-fpga-microchip-spi-add-Microchip-MPF-FPGA-manager.patch
applying on vanilla kernel.
v6 -> v7: fix binding doc to pass dt_binding_check
v7 -> v8: another fix for dt_binding_check warning
v8 -> v9:
* add another patch to support bitstream offset in FPGA image buffer
* rework fpga_manager_ops.write_sg() back to fpga_manager_ops.write()
* move image header parsing from write() to write_init()
v9 -> v10:
* add parse_header() callback to fpga_manager_ops
* adjust fpga_mgr_write_init[_buf|_sg]() for parse_header() usage
* implement parse_header() in microchip-spi driver
v10 -> v11: include missing unaligned.h to microchip-spi
fix error: implicit declaration of function 'get_unaligned_le[16|32]'
v11 -> v12:
* microchip-spi: double read hw status, ignore first read, because it
can be unreliable.
* microchip-spi: remove sleep between status readings in
poll_status_not_busy() to save a few seconds. Status is polled on
every 16 byte writes - that is quite often, therefore
usleep_range() accumulate to a considerable number of seconds.
v12 -> v13:
* fpga-mgr: separate fpga_mgr_parse_header_buf() from
fpga_mgr_write_init_buf()
* fpga-mgr: introduce FPGA_MGR_STATE_PARSE_HEADER and
FPGA_MGR_STATE_PARSE_HEADER_ERR fpga_mgr_states
* fpga-mgr: rename fpga_mgr_write_init_sg() to fpga_mgr_prepare_sg()
and rework with respect to a new fpga_mgr_parse_header_buf()
* fpga-mgr: rework write accounting in fpga_mgr_buf_load_sg() for
better clarity
* microchip-spi: rename MPF_STATUS_POLL_TIMEOUT to
MPF_STATUS_POLL_RETRIES
* microchip-spi: add comment about status reading quirk to
mpf_read_status()
* microchip-spi: rename poll_status_not_busy() to mpf_poll_status()
and add comment.
* microchip-spi: make if statement in mpf_poll_status() easier to
read.
v13 -> v14:
* fpga-mgr: improvements from Xu Yilun in
- fpga_mgr_parse_header_buf()
- fpga_mgr_write_init_buf()
- fpga_mgr_prepare_sg()
- fpga_mgr_buf_load_sg()
* fpga-mgr: add check for -EAGAIN from fpga_mgr_parse_header_buf()
when called from fpga_mgr_buf_load_mapped()
* microchip-spi: remove excessive cs_change from second spi_transfer
in mpf_read_status()
* microchip-spi: change type of components_size_start,
bitstream_start, i from size_t to u32 in mpf_ops_parse_header()
v14 -> v15: eliminate memcpy() in mpf_ops_write()
Eliminate excessive memcpy() in mpf_ops_write() by using
spi_sync_transfer() instead of spi_write().
v15 -> v16:
* microchip-spi: change back components_size_start and
bitstream_start variables types to size_t, i - to u16 in
mpf_ops_parse_header()
* fpga-mgr: rename fpga_parse_header_buf() to
fpga_parse_header_mapped(). It serves only mapped FPGA image now,
adjust it accordingly.
* fpga-mgr: separate fpga_mgr_parse_header_sg_first() and
fpga_mgr_parse_header_sg() from fpga_mgr_prepare_sg()
v16 -> v17:
* fpga-mgr: return size of allocated header from
fpga_mgr_parse_header_sg(), add `char **ret_buf` to function args
to save pointer to allocated header. This allow us to call
fpga_mgr_write_init_buf() with exact size of allocated header.
* document parse_header() callback in fpga-mgr.rst
v17 -> v18:
* fpga-mgr: change back fpga_mgr_parse_header_sg() to return
allocated buffer but set buffer size into output parameter
* fpga-mgr: check returned pointer from krealloc for ZERO_OR_NULL_PTR
in fpga_mgr_paese_header_sg() as krealloc may return ZERO_SIZE_PTR.
* fpga-mgr: in fpga_mgr_prepare_sg() return fpga_mgr_write_init() on
fast path only when both initial_header_size and parse_header() are
not defined.
* docs: fpga-mgr: a few rewords from Xu Yilun
v18 -> v19:
* microchip-spi: split multiple assignments on a single line in
functions mpf_read_status() and mpf_ops_parse_header()
* fpga-mgr: add braces {} around "else if" arm in
fpga_mgr_prepare_sg()
* fpga-mgr: don't reuse krealloc() arg in fpga_mgr_parse_header_sg().
If krealloc() returns NULL, it doesn't free the original.
v19 -> v20:
* fpga-mgr: initialize info->header_size with
mops->initial_header_size at fpga_mgr_load().
* fpga-mgr: add mops->skip_header boolean flag. Adjust skipping
header before write to check against skip_header flag instead of
mere presence of info->header_size.
* fpga-mgr: split check for ZERO_OR_NULL_PTR() after realloc() in
fpga_mgr_parse_header_sg() function to check against zero header +
check against NULL returned from realloc().
* docs: fpga-mgr: adjust for skip_header flag.
* microchip-spi: add skip_header to mpf_ops.
v20 -> v21:
* fpga-mgr: in function fpga_mgr_parse_header_sg(), after
reallocation of a buffer for a new header, copy only exceeding
part, since realloc preserve old buffer content.
* fpga-mgr: in function fpga_mgr_buf_load_sg() instead of manually
counting fragments with header that should be skipped, use
sg_miter_skip().
* fpga-mgr: add tag "Suggested-by: Xu Yilun <[email protected]>"
since all changes in fpga-mgr was his ideas.
* MAINTAINERS: add entry for Microchip PolarFire FPGA drivers as
Conor Dooley suggested.
v21 -> v22:
* fpga-mgr: in function fpga_mgr_buf_load_sg() drop excessive
sg_miter_stop() when sg_miter_skip() reaches end of sg_mapping_iter
Ivan Bornyakov (5):
fpga: fpga-mgr: support bitstream offset in image buffer
docs: fpga: mgr: document parse_header() callback
fpga: microchip-spi: add Microchip MPF FPGA manager
dt-bindings: fpga: add binding doc for microchip-spi fpga mgr
MAINTAINERS: add Microchip PolarFire FPGA drivers entry
.../fpga/microchip,mpf-spi-fpga-mgr.yaml | 44 ++
Documentation/driver-api/fpga/fpga-mgr.rst | 27 +-
MAINTAINERS | 8 +
drivers/fpga/Kconfig | 8 +
drivers/fpga/Makefile | 1 +
drivers/fpga/fpga-mgr.c | 223 ++++++++--
drivers/fpga/microchip-spi.c | 398 ++++++++++++++++++
include/linux/fpga/fpga-mgr.h | 24 +-
8 files changed, 700 insertions(+), 33 deletions(-)
create mode 100644 Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
create mode 100644 drivers/fpga/microchip-spi.c
--
2.36.1
Add MAINTAINERS entry for the newly added Microchip PolarFire (MPF) FPGA
manager. Add myself as a reviewer and Conor Dooley as a maintainer.
Suggested-by: Conor Dooley <[email protected]>
Signed-off-by: Ivan Bornyakov <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Acked-by: Xu Yilun <[email protected]>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cd7a70782aaa..74df3812b37f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7895,6 +7895,14 @@ S: Maintained
F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
F: drivers/fpga/intel-m10-bmc-sec-update.c
+MICROCHIP POLARFIRE FPGA DRIVERS
+M: Conor Dooley <[email protected]>
+R: Ivan Bornyakov <[email protected]>
+L: [email protected]
+S: Supported
+F: Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
+F: drivers/fpga/microchip-spi.c
+
FPU EMULATOR
M: Bill Metzenthen <[email protected]>
S: Maintained
--
2.36.1
Add Device Tree Binding doc for Microchip Polarfire FPGA Manager using
slave SPI to load .dat formatted bitstream image.
Signed-off-by: Ivan Bornyakov <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Acked-by: Xu Yilun <[email protected]>
---
.../fpga/microchip,mpf-spi-fpga-mgr.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
diff --git a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
new file mode 100644
index 000000000000..aee45cb15592
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Polarfire FPGA manager.
+
+maintainers:
+ - Ivan Bornyakov <[email protected]>
+
+description:
+ Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
+ load the bitstream in .dat format.
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpf-spi-fpga-mgr
+
+ reg:
+ description: SPI chip select
+ maxItems: 1
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga_mgr@0 {
+ compatible = "microchip,mpf-spi-fpga-mgr";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+ };
--
2.36.1
At the moment FPGA manager core loads to the device entire image
provided to fpga_mgr_load(). But it is not always whole FPGA image
buffer meant to be written to the device. In particular, .dat formatted
image for Microchip MPF contains meta info in the header that is not
meant to be written to the device. This is issue for those low level
drivers that loads data to the device with write() fpga_manager_ops
callback, since write() can be called in iterator over scatter-gather
table, not only linear image buffer. On the other hand, write_sg()
callback is provided with whole image in scatter-gather form and can
decide itself which part should be sent to the device.
Add header_size and data_size to the fpga_image_info struct, add
skip_header to the fpga_manager_ops struct and adjust fpga_mgr_write()
callers with respect to them.
* info->header_size indicates part at the beginning of image buffer
that contains some meta info. It is optional and can be 0,
initialized with mops->initial_header_size.
* mops->skip_header tells fpga-mgr core whether write should start
from the beginning of image buffer or at the offset of header_size.
* info->data_size is the size of bitstream data that is meant to be
written to the device. It is also optional and can be 0, which
means bitstream data is up to the end of image buffer.
Also add parse_header() callback to fpga_manager_ops, which purpose is
to set info->header_size and info->data_size. At least
initial_header_size bytes of image buffer will be passed into
parse_header() first time. If it is not enough, parse_header() should
set desired size into info->header_size and return -EAGAIN, then it will
be called again with greater part of image buffer on the input.
Suggested-by: Xu Yilun <[email protected]>
Signed-off-by: Ivan Bornyakov <[email protected]>
---
drivers/fpga/fpga-mgr.c | 223 ++++++++++++++++++++++++++++++----
include/linux/fpga/fpga-mgr.h | 24 +++-
2 files changed, 220 insertions(+), 27 deletions(-)
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index 08dc85fcd511..a0fa0a2cb8af 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -74,6 +74,15 @@ static inline int fpga_mgr_write_complete(struct fpga_manager *mgr,
return 0;
}
+static inline int fpga_mgr_parse_header(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count)
+{
+ if (mgr->mops->parse_header)
+ return mgr->mops->parse_header(mgr, info, buf, count);
+ return 0;
+}
+
static inline int fpga_mgr_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
@@ -136,24 +145,141 @@ void fpga_image_info_free(struct fpga_image_info *info)
EXPORT_SYMBOL_GPL(fpga_image_info_free);
/*
- * Call the low level driver's write_init function. This will do the
+ * Call the low level driver's parse_header function with entire FPGA image
+ * buffer on the input. This will set info->header_size and info->data_size.
+ */
+static int fpga_mgr_parse_header_mapped(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count)
+{
+ int ret;
+
+ mgr->state = FPGA_MGR_STATE_PARSE_HEADER;
+ ret = fpga_mgr_parse_header(mgr, info, buf, count);
+
+ if (info->header_size + info->data_size > count) {
+ dev_err(&mgr->dev, "Bitsream data outruns FPGA image\n");
+ ret = -EINVAL;
+ }
+
+ if (ret) {
+ dev_err(&mgr->dev, "Error while parsing FPGA image header\n");
+ mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR;
+ }
+
+ return ret;
+}
+
+/*
+ * Call the low level driver's parse_header function with first fragment of
+ * scattered FPGA image on the input. If header fits first fragment,
+ * parse_header will set info->header_size and info->data_size. If it is not,
+ * parse_header will set desired size to info->header_size and -EAGAIN will be
+ * returned.
+ */
+static int fpga_mgr_parse_header_sg_first(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ struct sg_table *sgt)
+{
+ struct sg_mapping_iter miter;
+ int ret;
+
+ mgr->state = FPGA_MGR_STATE_PARSE_HEADER;
+
+ sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
+ if (sg_miter_next(&miter) &&
+ miter.length >= info->header_size)
+ ret = fpga_mgr_parse_header(mgr, info, miter.addr, miter.length);
+ else
+ ret = -EAGAIN;
+ sg_miter_stop(&miter);
+
+ if (ret && ret != -EAGAIN) {
+ dev_err(&mgr->dev, "Error while parsing FPGA image header\n");
+ mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR;
+ }
+
+ return ret;
+}
+
+/*
+ * Copy scattered FPGA image fragments to temporary buffer and call the
+ * low level driver's parse_header function. This should be called after
+ * fpga_mgr_parse_header_sg_first() returned -EAGAIN. In case of success,
+ * pointer to the newly allocated image header copy will be returned and
+ * its size will be set into *ret_size. Returned buffer needs to be freed.
+ */
+static void *fpga_mgr_parse_header_sg(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ struct sg_table *sgt, size_t *ret_size)
+{
+ size_t len, new_header_size, header_size = 0;
+ char *new_buf, *buf = NULL;
+ int ret;
+
+ do {
+ new_header_size = info->header_size;
+ if (new_header_size <= header_size) {
+ dev_err(&mgr->dev, "Requested invalid header size\n");
+ ret = -EFAULT;
+ break;
+ }
+
+ new_buf = krealloc(buf, new_header_size, GFP_KERNEL);
+ if (!new_buf) {
+ ret = -ENOMEM;
+ break;
+ }
+
+ buf = new_buf;
+
+ len = sg_pcopy_to_buffer(sgt->sgl, sgt->nents,
+ buf + header_size,
+ new_header_size - header_size,
+ header_size);
+ if (len != new_header_size - header_size) {
+ ret = -EFAULT;
+ break;
+ }
+
+ header_size = new_header_size;
+ ret = fpga_mgr_parse_header(mgr, info, buf, header_size);
+ } while (ret == -EAGAIN);
+
+ if (ret) {
+ dev_err(&mgr->dev, "Error while parsing FPGA image header\n");
+ mgr->state = FPGA_MGR_STATE_PARSE_HEADER_ERR;
+ kfree(buf);
+ buf = ERR_PTR(ret);
+ }
+
+ *ret_size = header_size;
+
+ return buf;
+}
+
+/*
+ * Call the low level driver's write_init function. This will do the
* device-specific things to get the FPGA into the state where it is ready to
- * receive an FPGA image. The low level driver only gets to see the first
- * initial_header_size bytes in the buffer.
+ * receive an FPGA image. The low level driver gets to see at least first
+ * info->header_size bytes in the buffer. If info->header_size is 0,
+ * write_init will not get any bytes of image buffer.
*/
static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
+ size_t header_size = info->header_size;
int ret;
mgr->state = FPGA_MGR_STATE_WRITE_INIT;
- if (!mgr->mops->initial_header_size) {
+
+ if (header_size > count)
+ ret = -EINVAL;
+ else if (!header_size)
ret = fpga_mgr_write_init(mgr, info, NULL, 0);
- } else {
- count = min(mgr->mops->initial_header_size, count);
+ else
ret = fpga_mgr_write_init(mgr, info, buf, count);
- }
if (ret) {
dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
@@ -164,39 +290,50 @@ static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
return 0;
}
-static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
- struct fpga_image_info *info,
- struct sg_table *sgt)
+static int fpga_mgr_prepare_sg(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ struct sg_table *sgt)
{
struct sg_mapping_iter miter;
size_t len;
char *buf;
int ret;
- if (!mgr->mops->initial_header_size)
+ /* Short path. Low level driver don't care about image header. */
+ if (!mgr->mops->initial_header_size && !mgr->mops->parse_header)
return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
/*
* First try to use miter to map the first fragment to access the
* header, this is the typical path.
*/
- sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
- if (sg_miter_next(&miter) &&
- miter.length >= mgr->mops->initial_header_size) {
- ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
- miter.length);
+ ret = fpga_mgr_parse_header_sg_first(mgr, info, sgt);
+ /* If 0, header fits first fragment, call write_init on it */
+ if (!ret) {
+ sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
+ if (sg_miter_next(&miter)) {
+ ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
+ miter.length);
+ sg_miter_stop(&miter);
+ return ret;
+ }
sg_miter_stop(&miter);
+ /*
+ * If -EAGAIN, more sg buffer is needed,
+ * otherwise an error has occurred.
+ */
+ } else if (ret != -EAGAIN) {
return ret;
}
- sg_miter_stop(&miter);
- /* Otherwise copy the fragments into temporary memory. */
- buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
- if (!buf)
- return -ENOMEM;
+ /*
+ * Copy the fragments into temporary memory.
+ * Copying is done inside fpga_mgr_parse_header_sg().
+ */
+ buf = fpga_mgr_parse_header_sg(mgr, info, sgt, &len);
+ if (IS_ERR(buf))
+ return PTR_ERR(buf);
- len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
- mgr->mops->initial_header_size);
ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
kfree(buf);
@@ -227,7 +364,7 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
{
int ret;
- ret = fpga_mgr_write_init_sg(mgr, info, sgt);
+ ret = fpga_mgr_prepare_sg(mgr, info, sgt);
if (ret)
return ret;
@@ -236,17 +373,35 @@ static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
if (mgr->mops->write_sg) {
ret = fpga_mgr_write_sg(mgr, sgt);
} else {
+ size_t length, count = 0, data_size = info->data_size;
struct sg_mapping_iter miter;
sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
+
+ if (mgr->mops->skip_header &&
+ !sg_miter_skip(&miter, info->header_size)) {
+ ret = -EINVAL;
+ goto out;
+ }
+
while (sg_miter_next(&miter)) {
- ret = fpga_mgr_write(mgr, miter.addr, miter.length);
+ if (data_size)
+ length = min(miter.length, data_size - count);
+ else
+ length = miter.length;
+
+ ret = fpga_mgr_write(mgr, miter.addr, length);
if (ret)
break;
+
+ count += length;
+ if (data_size && count >= data_size)
+ break;
}
sg_miter_stop(&miter);
}
+out:
if (ret) {
dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
mgr->state = FPGA_MGR_STATE_WRITE_ERR;
@@ -262,10 +417,22 @@ static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
{
int ret;
+ ret = fpga_mgr_parse_header_mapped(mgr, info, buf, count);
+ if (ret)
+ return ret;
+
ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
if (ret)
return ret;
+ if (mgr->mops->skip_header) {
+ buf += info->header_size;
+ count -= info->header_size;
+ }
+
+ if (info->data_size)
+ count = info->data_size;
+
/*
* Write the FPGA image to the FPGA.
*/
@@ -404,6 +571,8 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
*/
int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
{
+ info->header_size = mgr->mops->initial_header_size;
+
if (info->sgt)
return fpga_mgr_buf_load_sg(mgr, info, info->sgt);
if (info->buf && info->count)
@@ -424,6 +593,10 @@ static const char * const state_str[] = {
[FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request",
[FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error",
+ /* Parse FPGA image header */
+ [FPGA_MGR_STATE_PARSE_HEADER] = "parse header",
+ [FPGA_MGR_STATE_PARSE_HEADER_ERR] = "parse header error",
+
/* Preparing FPGA to receive image */
[FPGA_MGR_STATE_WRITE_INIT] = "write init",
[FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error",
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 0f9468771bb9..54f63459efd6 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -22,6 +22,8 @@ struct sg_table;
* @FPGA_MGR_STATE_RESET: FPGA in reset state
* @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress
* @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed
+ * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
+ * @FPGA_MGR_STATE_PARSE_HEADER_ERR: Error during PARSE_HEADER stage
* @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
* @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
* @FPGA_MGR_STATE_WRITE: writing image to FPGA
@@ -41,7 +43,9 @@ enum fpga_mgr_states {
FPGA_MGR_STATE_FIRMWARE_REQ,
FPGA_MGR_STATE_FIRMWARE_REQ_ERR,
- /* write sequence: init, write, complete */
+ /* write sequence: parse header, init, write, complete */
+ FPGA_MGR_STATE_PARSE_HEADER,
+ FPGA_MGR_STATE_PARSE_HEADER_ERR,
FPGA_MGR_STATE_WRITE_INIT,
FPGA_MGR_STATE_WRITE_INIT_ERR,
FPGA_MGR_STATE_WRITE,
@@ -85,6 +89,9 @@ enum fpga_mgr_states {
* @sgt: scatter/gather table containing FPGA image
* @buf: contiguous buffer containing FPGA image
* @count: size of buf
+ * @header_size: size of image header.
+ * @data_size: size of image data to be sent to the device. If not specified,
+ * whole image will be used. Header may be skipped in either case.
* @region_id: id of target region
* @dev: device that owns this
* @overlay: Device Tree overlay
@@ -98,6 +105,8 @@ struct fpga_image_info {
struct sg_table *sgt;
const char *buf;
size_t count;
+ size_t header_size;
+ size_t data_size;
int region_id;
struct device *dev;
#ifdef CONFIG_OF
@@ -137,9 +146,16 @@ struct fpga_manager_info {
/**
* struct fpga_manager_ops - ops for low level fpga manager drivers
- * @initial_header_size: Maximum number of bytes that should be passed into write_init
+ * @initial_header_size: minimum number of bytes that should be passed into
+ * parse_header and write_init.
+ * @skip_header: bool flag to tell fpga-mgr core whether it should skip
+ * info->header_size part at the beginning of the image when invoking
+ * write callback.
* @state: returns an enum value of the FPGA's state
* @status: returns status of the FPGA, including reconfiguration error code
+ * @parse_header: parse FPGA image header to set info->header_size and
+ * info->data_size. In case the input buffer is not large enough, set
+ * required size to info->header_size and return -EAGAIN.
* @write_init: prepare the FPGA to receive configuration data
* @write: write count bytes of configuration data to the FPGA
* @write_sg: write the scatter list of configuration data to the FPGA
@@ -153,8 +169,12 @@ struct fpga_manager_info {
*/
struct fpga_manager_ops {
size_t initial_header_size;
+ bool skip_header;
enum fpga_mgr_states (*state)(struct fpga_manager *mgr);
u64 (*status)(struct fpga_manager *mgr);
+ int (*parse_header)(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count);
int (*write_init)(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count);
--
2.36.1
On Thu, Jun 23, 2022 at 07:32:43PM +0300, Ivan Bornyakov wrote:
> Add support to the FPGA manager for programming Microchip Polarfire
> FPGAs over slave SPI interface with .dat formatted bitsream image.
>
> Changelog:
> v1 -> v2: fix printk formating
> v2 -> v3:
> * replace "microsemi" with "microchip"
> * replace prefix "microsemi_fpga_" with "mpf_"
> * more sensible .compatible and .name strings
> * remove unused defines STATUS_SPI_VIOLATION and STATUS_SPI_ERROR
> v3 -> v4: fix unused variable warning
> Put 'mpf_of_ids' definition under conditional compilation, so it
> would not hang unused if CONFIG_OF is not enabled.
> v4 -> v5:
> * prefix defines with MPF_
> * mdelay() -> usleep_range()
> * formatting fixes
> * add DT bindings doc
> * rework fpga_manager_ops.write() to fpga_manager_ops.write_sg()
> We can't parse image header in write_init() because image header
> size is not known beforehand. Thus parsing need to be done in
> fpga_manager_ops.write() callback, but fpga_manager_ops.write()
> also need to be reenterable. On the other hand,
> fpga_manager_ops.write_sg() is called once. Thus, rework usage of
> write() callback to write_sg().
> v5 -> v6: fix patch applying
> I forgot to clean up unrelated local changes which lead to error on
> patch 0001-fpga-microchip-spi-add-Microchip-MPF-FPGA-manager.patch
> applying on vanilla kernel.
> v6 -> v7: fix binding doc to pass dt_binding_check
> v7 -> v8: another fix for dt_binding_check warning
> v8 -> v9:
> * add another patch to support bitstream offset in FPGA image buffer
> * rework fpga_manager_ops.write_sg() back to fpga_manager_ops.write()
> * move image header parsing from write() to write_init()
> v9 -> v10:
> * add parse_header() callback to fpga_manager_ops
> * adjust fpga_mgr_write_init[_buf|_sg]() for parse_header() usage
> * implement parse_header() in microchip-spi driver
> v10 -> v11: include missing unaligned.h to microchip-spi
> fix error: implicit declaration of function 'get_unaligned_le[16|32]'
> v11 -> v12:
> * microchip-spi: double read hw status, ignore first read, because it
> can be unreliable.
> * microchip-spi: remove sleep between status readings in
> poll_status_not_busy() to save a few seconds. Status is polled on
> every 16 byte writes - that is quite often, therefore
> usleep_range() accumulate to a considerable number of seconds.
> v12 -> v13:
> * fpga-mgr: separate fpga_mgr_parse_header_buf() from
> fpga_mgr_write_init_buf()
> * fpga-mgr: introduce FPGA_MGR_STATE_PARSE_HEADER and
> FPGA_MGR_STATE_PARSE_HEADER_ERR fpga_mgr_states
> * fpga-mgr: rename fpga_mgr_write_init_sg() to fpga_mgr_prepare_sg()
> and rework with respect to a new fpga_mgr_parse_header_buf()
> * fpga-mgr: rework write accounting in fpga_mgr_buf_load_sg() for
> better clarity
> * microchip-spi: rename MPF_STATUS_POLL_TIMEOUT to
> MPF_STATUS_POLL_RETRIES
> * microchip-spi: add comment about status reading quirk to
> mpf_read_status()
> * microchip-spi: rename poll_status_not_busy() to mpf_poll_status()
> and add comment.
> * microchip-spi: make if statement in mpf_poll_status() easier to
> read.
> v13 -> v14:
> * fpga-mgr: improvements from Xu Yilun in
> - fpga_mgr_parse_header_buf()
> - fpga_mgr_write_init_buf()
> - fpga_mgr_prepare_sg()
> - fpga_mgr_buf_load_sg()
> * fpga-mgr: add check for -EAGAIN from fpga_mgr_parse_header_buf()
> when called from fpga_mgr_buf_load_mapped()
> * microchip-spi: remove excessive cs_change from second spi_transfer
> in mpf_read_status()
> * microchip-spi: change type of components_size_start,
> bitstream_start, i from size_t to u32 in mpf_ops_parse_header()
> v14 -> v15: eliminate memcpy() in mpf_ops_write()
> Eliminate excessive memcpy() in mpf_ops_write() by using
> spi_sync_transfer() instead of spi_write().
> v15 -> v16:
> * microchip-spi: change back components_size_start and
> bitstream_start variables types to size_t, i - to u16 in
> mpf_ops_parse_header()
> * fpga-mgr: rename fpga_parse_header_buf() to
> fpga_parse_header_mapped(). It serves only mapped FPGA image now,
> adjust it accordingly.
> * fpga-mgr: separate fpga_mgr_parse_header_sg_first() and
> fpga_mgr_parse_header_sg() from fpga_mgr_prepare_sg()
> v16 -> v17:
> * fpga-mgr: return size of allocated header from
> fpga_mgr_parse_header_sg(), add `char **ret_buf` to function args
> to save pointer to allocated header. This allow us to call
> fpga_mgr_write_init_buf() with exact size of allocated header.
> * document parse_header() callback in fpga-mgr.rst
> v17 -> v18:
> * fpga-mgr: change back fpga_mgr_parse_header_sg() to return
> allocated buffer but set buffer size into output parameter
> * fpga-mgr: check returned pointer from krealloc for ZERO_OR_NULL_PTR
> in fpga_mgr_paese_header_sg() as krealloc may return ZERO_SIZE_PTR.
> * fpga-mgr: in fpga_mgr_prepare_sg() return fpga_mgr_write_init() on
> fast path only when both initial_header_size and parse_header() are
> not defined.
> * docs: fpga-mgr: a few rewords from Xu Yilun
> v18 -> v19:
> * microchip-spi: split multiple assignments on a single line in
> functions mpf_read_status() and mpf_ops_parse_header()
> * fpga-mgr: add braces {} around "else if" arm in
> fpga_mgr_prepare_sg()
> * fpga-mgr: don't reuse krealloc() arg in fpga_mgr_parse_header_sg().
> If krealloc() returns NULL, it doesn't free the original.
> v19 -> v20:
> * fpga-mgr: initialize info->header_size with
> mops->initial_header_size at fpga_mgr_load().
> * fpga-mgr: add mops->skip_header boolean flag. Adjust skipping
> header before write to check against skip_header flag instead of
> mere presence of info->header_size.
> * fpga-mgr: split check for ZERO_OR_NULL_PTR() after realloc() in
> fpga_mgr_parse_header_sg() function to check against zero header +
> check against NULL returned from realloc().
> * docs: fpga-mgr: adjust for skip_header flag.
> * microchip-spi: add skip_header to mpf_ops.
> v20 -> v21:
> * fpga-mgr: in function fpga_mgr_parse_header_sg(), after
> reallocation of a buffer for a new header, copy only exceeding
> part, since realloc preserve old buffer content.
> * fpga-mgr: in function fpga_mgr_buf_load_sg() instead of manually
> counting fragments with header that should be skipped, use
> sg_miter_skip().
> * fpga-mgr: add tag "Suggested-by: Xu Yilun <[email protected]>"
> since all changes in fpga-mgr was his ideas.
> * MAINTAINERS: add entry for Microchip PolarFire FPGA drivers as
> Conor Dooley suggested.
> v21 -> v22:
> * fpga-mgr: in function fpga_mgr_buf_load_sg() drop excessive
> sg_miter_stop() when sg_miter_skip() reaches end of sg_mapping_iter
>
> Ivan Bornyakov (5):
> fpga: fpga-mgr: support bitstream offset in image buffer
> docs: fpga: mgr: document parse_header() callback
> fpga: microchip-spi: add Microchip MPF FPGA manager
> dt-bindings: fpga: add binding doc for microchip-spi fpga mgr
> MAINTAINERS: add Microchip PolarFire FPGA drivers entry
>
> .../fpga/microchip,mpf-spi-fpga-mgr.yaml | 44 ++
> Documentation/driver-api/fpga/fpga-mgr.rst | 27 +-
> MAINTAINERS | 8 +
> drivers/fpga/Kconfig | 8 +
> drivers/fpga/Makefile | 1 +
> drivers/fpga/fpga-mgr.c | 223 ++++++++--
> drivers/fpga/microchip-spi.c | 398 ++++++++++++++++++
> include/linux/fpga/fpga-mgr.h | 24 +-
> 8 files changed, 700 insertions(+), 33 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
> create mode 100644 drivers/fpga/microchip-spi.c
Applied the series to for-next
Thanks for the improvement to FPGA core.
Yilun
>
> --
> 2.36.1
>