2022-09-09 14:28:54

by Palmer Dabbelt

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Subject: [GIT PULL] RISC-V Fixes for 6.0-rc5

The following changes since commit 1709c70c31e05e6e87b2ffa0a2b4cc0da4b2c513:

Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes (2022-08-25 16:38:01 -0700)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.0-rc5

for you to fetch changes up to 20e0fbab16003ae23a9e86a64bcb93e3121587ca:

perf: RISC-V: fix access beyond allocated array (2022-09-08 13:50:25 -0700)

----------------------------------------------------------------
RISC-V Fixes for 6.0-rc5

* A pair of device tree fixes for the Polarfire SOC.
* A fix to avoid overflowing the PMU counter array when firmware
incorrectly reports the number of supported counters, which manifests
on OpenSBI versions prior to 1.1.

----------------------------------------------------------------
Conor Dooley (2):
dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
riscv: dts: microchip: use an mpfs specific l2 compatible

Palmer Dabbelt (1):
Merge tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes

Sergey Matyukevich (1):
perf: RISC-V: fix access beyond allocated array

.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++++--------
arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +-
drivers/perf/riscv_pmu_sbi.c | 2 +-
3 files changed, 51 insertions(+), 32 deletions(-)


2022-09-09 18:36:41

by pr-tracker-bot

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Subject: Re: [GIT PULL] RISC-V Fixes for 6.0-rc5

The pull request you sent on Fri, 09 Sep 2022 07:20:17 -0700 (PDT):

> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.0-rc5

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/22b2e2d6ab35fdef4439e27da2df208014d52eda

Thank you!

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