2022-09-22 19:59:36

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 00/12] pinctrl/arm64: qcom: continued - fix Qualcomm LPASS pinctrl schema warnings

Hi,

Set of fixes for LPASS (audio) pin controller bindings and DTS.

Dependencies
============
1. dt-bindings are independent of DTS patches.

Best regards,
Krzysztof

Krzysztof Kozlowski (12):
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix gpio pattern
dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: fix gpio pattern
dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: fix matching pin config
dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix matching pin config
dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: fix matching pin config
dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: fix matching pin config
dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: add bias-bus-hold
dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: add bias-bus-hold and
input-enable
arm64: dts: qcom: sc7280: drop clock-cells from LPASS TLMM
arm64: dts: qcom: sc7280: align LPASS pin configuration with DT schema
arm64: dts: qcom: sm8250: correct LPASS pin pull down
arm64: dts: qcom: sm8250: align LPASS pin configuration with DT schema

.../qcom,sc7280-lpass-lpi-pinctrl.yaml | 34 +++++++++++---
.../qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 31 +++++++++++--
.../qcom,sm8250-lpass-lpi-pinctrl.yaml | 42 ++++++++++++++---
.../qcom,sm8450-lpass-lpi-pinctrl.yaml | 38 +++++++++++++--
arch/arm64/boot/dts/qcom/sc7280.dtsi | 34 +++++++-------
arch/arm64/boot/dts/qcom/sm8250.dtsi | 46 +++++++++----------
6 files changed, 166 insertions(+), 59 deletions(-)

--
2.34.1


2022-09-22 19:59:41

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 03/12] dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: fix matching pin config

The LPASS pin controller follows generic pin-controller bindings, so
just like TLMM, should have subnodes with '-state' and '-pins'.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../qcom,sc7280-lpass-lpi-pinctrl.yaml | 29 +++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
index 624e14f00790..1daeca62625d 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
@@ -37,9 +37,17 @@ properties:
gpio-ranges:
maxItems: 1

-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sc7280-lpass-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sc7280-lpass-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sc7280-lpass-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -116,4 +124,21 @@ examples:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+ dmic01-state {
+ dmic01-clk-pins {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ };
+
+ dmic01-clk-sleep-pins {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ };
+ };
+
+ tx-swr-data-sleep-state {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ };
};
--
2.34.1

2022-09-22 20:00:21

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 04/12] dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix matching pin config

The LPASS pin controller follows generic pin-controller bindings, so
just like TLMM, should have subnodes with '-state' and '-pins'.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 29 +++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
index fb3ad6c0d80e..26e93e2c8c42 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
@@ -43,9 +43,17 @@ properties:
gpio-ranges:
maxItems: 1

-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sc8280xp-lpass-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sc8280xp-lpass-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sc8280xp-lpass-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -130,4 +138,21 @@ examples:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 18>;
+
+ dmic01-state {
+ dmic01-clk-pins {
+ pins = "gpio16";
+ function = "dmic1_clk";
+ };
+
+ dmic01-clk-sleep-pins {
+ pins = "gpio16";
+ function = "dmic1_clk";
+ };
+ };
+
+ tx-swr-data-sleep-state {
+ pins = "gpio0", "gpio1";
+ function = "swr_tx_data";
+ };
};
--
2.34.1

2022-09-22 20:00:27

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 07/12] dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: add bias-bus-hold

The existing SC7280 LPASS pin controller nodes use bias-bus-hold, so
allow it. Squash also blank lines for readability.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
index 1daeca62625d..c8c8fb927a65 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
@@ -91,13 +91,10 @@ $defs:
3: Reserved (No adjustments)

bias-pull-down: true
-
bias-pull-up: true
-
+ bias-bus-hold: true
bias-disable: true
-
output-high: true
-
output-low: true

required:
--
2.34.1

2022-09-22 20:00:42

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 09/12] arm64: dts: qcom: sc7280: drop clock-cells from LPASS TLMM

The LPASS pin-controller is not a clock provider:

qcom/sc7280-herobrine-herobrine-r1.dtb: [email protected]: '#clock-cells' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 --
1 file changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8d807b7bf66a..8823b75a6f1b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2432,8 +2432,6 @@ lpass_tlmm: [email protected] {
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;

- #clock-cells = <1>;
-
lpass_dmic01_clk: dmic01-clk {
pins = "gpio6";
function = "dmic1_clk";
--
2.34.1

2022-09-22 20:00:45

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 06/12] dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: fix matching pin config

The LPASS pin controller follows generic pin-controller bindings, so
just like TLMM, should have subnodes with '-state' and '-pins'.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../qcom,sm8450-lpass-lpi-pinctrl.yaml | 36 +++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
index c17cdff6174f..0e0769a7751c 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
@@ -43,9 +43,17 @@ properties:
gpio-ranges:
maxItems: 1

-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm8450-lpass-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm8450-lpass-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm8450-lpass-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -132,4 +140,28 @@ examples:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 23>;
+
+ wsa-swr-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ };
+ };
+
+ tx-swr-sleep-clk-state {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
};
--
2.34.1

2022-09-22 20:01:19

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 10/12] arm64: dts: qcom: sc7280: align LPASS pin configuration with DT schema

DT schema expects LPASS pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 32 ++++++++++++++--------------
1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8823b75a6f1b..28e3fb9992d9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2432,82 +2432,82 @@ lpass_tlmm: [email protected] {
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 15>;

- lpass_dmic01_clk: dmic01-clk {
+ lpass_dmic01_clk: dmic01-clk-state {
pins = "gpio6";
function = "dmic1_clk";
};

- lpass_dmic01_clk_sleep: dmic01-clk-sleep {
+ lpass_dmic01_clk_sleep: dmic01-clk-sleep-state {
pins = "gpio6";
function = "dmic1_clk";
};

- lpass_dmic01_data: dmic01-data {
+ lpass_dmic01_data: dmic01-data-state {
pins = "gpio7";
function = "dmic1_data";
};

- lpass_dmic01_data_sleep: dmic01-data-sleep {
+ lpass_dmic01_data_sleep: dmic01-data-sleep-state {
pins = "gpio7";
function = "dmic1_data";
};

- lpass_dmic23_clk: dmic23-clk {
+ lpass_dmic23_clk: dmic23-clk-state {
pins = "gpio8";
function = "dmic2_clk";
};

- lpass_dmic23_clk_sleep: dmic23-clk-sleep {
+ lpass_dmic23_clk_sleep: dmic23-clk-sleep-state {
pins = "gpio8";
function = "dmic2_clk";
};

- lpass_dmic23_data: dmic23-data {
+ lpass_dmic23_data: dmic23-data-state {
pins = "gpio9";
function = "dmic2_data";
};

- lpass_dmic23_data_sleep: dmic23-data-sleep {
+ lpass_dmic23_data_sleep: dmic23-data-sleep-state {
pins = "gpio9";
function = "dmic2_data";
};

- lpass_rx_swr_clk: rx-swr-clk {
+ lpass_rx_swr_clk: rx-swr-clk-state {
pins = "gpio3";
function = "swr_rx_clk";
};

- lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
+ lpass_rx_swr_clk_sleep: rx-swr-clk-sleep-state {
pins = "gpio3";
function = "swr_rx_clk";
};

- lpass_rx_swr_data: rx-swr-data {
+ lpass_rx_swr_data: rx-swr-data-state {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
};

- lpass_rx_swr_data_sleep: rx-swr-data-sleep {
+ lpass_rx_swr_data_sleep: rx-swr-data-sleep-state {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
};

- lpass_tx_swr_clk: tx-swr-clk {
+ lpass_tx_swr_clk: tx-swr-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
};

- lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
+ lpass_tx_swr_clk_sleep: tx-swr-clk-sleep-state {
pins = "gpio0";
function = "swr_tx_clk";
};

- lpass_tx_swr_data: tx-swr-data {
+ lpass_tx_swr_data: tx-swr-data-state {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
};

- lpass_tx_swr_data_sleep: tx-swr-data-sleep {
+ lpass_tx_swr_data_sleep: tx-swr-data-sleep-state {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
};
--
2.34.1

2022-09-22 20:01:41

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 12/12] arm64: dts: qcom: sm8250: align LPASS pin configuration with DT schema

DT schema expects LPASS pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 44 ++++++++++++++--------------
1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 8f402b912c62..e0416d611b66 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2388,8 +2388,8 @@ lpass_tlmm: [email protected]{
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";

- wsa_swr_active: wsa-swr-active-pins {
- clk {
+ wsa_swr_active: wsa-swr-active-state {
+ clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
@@ -2397,7 +2397,7 @@ clk {
bias-disable;
};

- data {
+ data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
@@ -2407,8 +2407,8 @@ data {
};
};

- wsa_swr_sleep: wsa-swr-sleep-pins {
- clk {
+ wsa_swr_sleep: wsa-swr-sleep-state {
+ clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
@@ -2416,7 +2416,7 @@ clk {
bias-pull-down;
};

- data {
+ data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
@@ -2426,14 +2426,14 @@ data {
};
};

- dmic01_active: dmic01-active-pins {
- clk {
+ dmic01_active: dmic01-active-state {
+ clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
- data {
+ data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
@@ -2441,8 +2441,8 @@ data {
};
};

- dmic01_sleep: dmic01-sleep-pins {
- clk {
+ dmic01_sleep: dmic01-sleep-state {
+ clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <2>;
@@ -2450,7 +2450,7 @@ clk {
output-low;
};

- data {
+ data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <2>;
@@ -2459,8 +2459,8 @@ data {
};
};

- rx_swr_active: rx_swr-active-pins {
- clk {
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
@@ -2468,7 +2468,7 @@ clk {
bias-disable;
};

- data {
+ data-pins {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
@@ -2477,8 +2477,8 @@ data {
};
};

- tx_swr_active: tx_swr-active-pins {
- clk {
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
@@ -2486,7 +2486,7 @@ clk {
bias-disable;
};

- data {
+ data-pins {
pins = "gpio1", "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
@@ -2495,8 +2495,8 @@ data {
};
};

- tx_swr_sleep: tx_swr-sleep-pins {
- clk {
+ tx_swr_sleep: tx-swr-sleep-state {
+ clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
@@ -2504,7 +2504,7 @@ clk {
bias-pull-down;
};

- data1 {
+ data1-pins {
pins = "gpio1";
function = "swr_tx_data";
drive-strength = <2>;
@@ -2512,7 +2512,7 @@ data1 {
bias-bus-hold;
};

- data2 {
+ data2-pins {
pins = "gpio2";
function = "swr_tx_data";
drive-strength = <2>;
--
2.34.1

2022-09-22 20:34:49

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 11/12] arm64: dts: qcom: sm8250: correct LPASS pin pull down

The pull-down property is actually bias-pull-down.

Fixes: 3160c1b894d9 ("arm64: dts: qcom: sm8250: add lpass lpi pin controller node")
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a5b62cadb129..8f402b912c62 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2454,7 +2454,7 @@ data {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <2>;
- pull-down;
+ bias-pull-down;
input-enable;
};
};
--
2.34.1

2022-09-22 20:40:41

by Krzysztof Kozlowski

[permalink] [raw]
Subject: [PATCH 05/12] dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: fix matching pin config

The LPASS pin controller follows generic pin-controller bindings, so
just like TLMM, should have subnodes with '-state' and '-pins'.

qcom/qrb5165-rb5.dtb: [email protected]: wsa-swr-active-pins: 'pins' is a required property

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../qcom,sm8250-lpass-lpi-pinctrl.yaml | 36 +++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
index 06efb1382876..9640d1110fdd 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
@@ -42,9 +42,17 @@ properties:
gpio-ranges:
maxItems: 1

-#PIN CONFIGURATION NODES
patternProperties:
- '-pins$':
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm8250-lpass-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm8250-lpass-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm8250-lpass-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -130,4 +138,28 @@ examples:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 14>;
+
+ wsa-swr-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ };
+ };
+
+ tx-swr-sleep-clk-state {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
};
--
2.34.1

2022-09-22 20:41:44

by Krzysztof Kozlowski

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Subject: [PATCH 01/12] dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix gpio pattern

Fix double ']' in GPIO pattern to properly match "pins" property.
Otherwise schema for pins state is not applied.

Fixes: 958bb025f5b3 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings")
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
index 1f468303bb08..fb3ad6c0d80e 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
@@ -58,7 +58,7 @@ patternProperties:
List of gpio pins affected by the properties specified in this
subnode.
items:
- pattern: "^gpio([0-1]|1[0-8]])$"
+ pattern: "^gpio([0-1]|1[0-8])$"

function:
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
--
2.34.1

2022-09-22 20:47:12

by Krzysztof Kozlowski

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Subject: [PATCH 08/12] dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: add bias-bus-hold and input-enable

The existing SC7280 LPASS pin controller nodes use bias-bus-hold and
input-enable, so allow them. Squash also blank lines for readability.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
index 9640d1110fdd..2427da7c20d3 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
@@ -96,13 +96,11 @@ $defs:
3: Reserved (No adjustments)

bias-pull-down: true
-
bias-pull-up: true
-
+ bias-bus-hold: true
bias-disable: true
-
+ input-enable: true
output-high: true
-
output-low: true

required:
--
2.34.1

2022-09-23 10:23:09

by Krzysztof Kozlowski

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Subject: Re: [PATCH 08/12] dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: add bias-bus-hold and input-enable

On Thu, 22 Sep 2022 21:56:47 +0200, Krzysztof Kozlowski wrote:
> The existing SC7280 LPASS pin controller nodes use bias-bus-hold and
> input-enable, so allow them. Squash also blank lines for readability.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1681325


[email protected]: 'dmic01-active-pins', 'dmic01-sleep-pins', 'rx_swr-active-pins', 'tx_swr-active-pins', 'tx_swr-sleep-pins', 'wsa-swr-active-pins', 'wsa-swr-sleep-pins' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/qrb5165-rb5.dtb
arch/arm64/boot/dts/qcom/sm8250-hdk.dtb
arch/arm64/boot/dts/qcom/sm8250-mtp.dtb
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dtb
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dtb

2022-09-23 10:53:38

by Krzysztof Kozlowski

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Subject: Re: [PATCH 08/12] dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: add bias-bus-hold and input-enable

On 23/09/2022 11:31, Krzysztof Kozlowski wrote:
> On Thu, 22 Sep 2022 21:56:47 +0200, Krzysztof Kozlowski wrote:
>> The existing SC7280 LPASS pin controller nodes use bias-bus-hold and
>> input-enable, so allow them. Squash also blank lines for readability.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 6 ++----
>> 1 file changed, 2 insertions(+), 4 deletions(-)
>>
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1681325
>
>
> [email protected]: 'dmic01-active-pins', 'dmic01-sleep-pins', 'rx_swr-active-pins', 'tx_swr-active-pins', 'tx_swr-sleep-pins', 'wsa-swr-active-pins', 'wsa-swr-sleep-pins' do not match any of the regexes: '-state$', 'pinctrl-[0-9]+'

This is being fixed in next DTS patches. I'll reorganize them if there
is going to be a resubmit.

Best regards,
Krzysztof