2022-09-23 13:28:15

by Allen-KH Cheng

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Subject: [PATCH 0/5] Add some driver nodes for MT8186 SoC

This series are based on linux next, tag: next-20220923.

Allen-KH Cheng (5):
dt-bindings: mfd: mediatek: Add scpsys compatible for mt8186
arm64: dts: mt8186: Add power domains controller
arm64: dts: mt8186: Add IOMMU and SMI nodes
arm64: dts: mt8186: Add dpi node
arm64: dts: mt8186: Add xhci nodes

.../bindings/mfd/mediatek,mt8195-scpsys.yaml | 1 +
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 421 ++++++++++++++++++
2 files changed, 422 insertions(+)

--
2.18.0


2022-09-23 13:29:07

by Allen-KH Cheng

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Subject: [PATCH 1/5] dt-bindings: mfd: mediatek: Add scpsys compatible for mt8186

Add a new scpsys compatible for mt8186 SoC.

Signed-off-by: Allen-KH Cheng <[email protected]>
---
.../devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
index 3737207d8504..c8c4812fffe2 100644
--- a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
@@ -21,6 +21,7 @@ properties:
- mediatek,mt8167-scpsys
- mediatek,mt8173-scpsys
- mediatek,mt8183-scpsys
+ - mediatek,mt8186-scpsys
- mediatek,mt8192-scpsys
- mediatek,mt8195-scpsys
- const: syscon
--
2.18.0

2022-09-23 13:29:33

by Allen-KH Cheng

[permalink] [raw]
Subject: [PATCH 2/5] arm64: dts: mt8186: Add power domains controller

Add power domains controller for mt8186 SoC.

Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++
1 file changed, 188 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 64693c17af9e..833e7037fe22 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -329,6 +329,194 @@
#interrupt-cells = <2>;
};

+ scpsys: [email protected] {
+ compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8186-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ mfg0: [email protected]_POWER_DOMAIN_MFG0 {
+ reg = <MT8186_POWER_DOMAIN_MFG0>;
+ clocks = <&topckgen CLK_TOP_MFG>;
+ clock-names = "mfg00";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ [email protected]_POWER_DOMAIN_MFG1 {
+ reg = <MT8186_POWER_DOMAIN_MFG1>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ [email protected]_POWER_DOMAIN_MFG2 {
+ reg = <MT8186_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_MFG3 {
+ reg = <MT8186_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ [email protected]_POWER_DOMAIN_CSIRX_TOP {
+ reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
+ clocks = <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF1>;
+ clock-names = "csirx_top0", "csirx_top1";
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_SSUSB {
+ reg = <MT8186_POWER_DOMAIN_SSUSB>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_SSUSB_P1 {
+ reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_ADSP_AO {
+ reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
+ clocks = <&topckgen CLK_TOP_AUDIODSP>,
+ <&topckgen CLK_TOP_ADSP_BUS>;
+ clock-names = "adsp_ao0", "adsp_ao1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ [email protected]_POWER_DOMAIN_ADSP_INFRA {
+ reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ [email protected]_POWER_DOMAIN_ADSP_TOP {
+ reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ [email protected]_POWER_DOMAIN_CONN_ON {
+ reg = <MT8186_POWER_DOMAIN_CONN_ON>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_DIS {
+ reg = <MT8186_POWER_DOMAIN_DIS>;
+ clocks = <&topckgen CLK_TOP_DISP>,
+ <&topckgen CLK_TOP_MDP>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "dis0", "dis1", "dis-0", "dis-1",
+ "dis-2", "dis-3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ [email protected]_POWER_DOMAIN_VDEC {
+ reg = <MT8186_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys CLK_VDEC_LARB1_CKEN>;
+ clock-names = "vdec0", "vdec-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_CAM {
+ reg = <MT8186_POWER_DOMAIN_CAM>;
+ clocks = <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF1>,
+ <&topckgen CLK_TOP_SENINF2>,
+ <&topckgen CLK_TOP_SENINF3>,
+ <&topckgen CLK_TOP_CAMTM>,
+ <&camsys CLK_CAM2MM_GALS>;
+ clock-names = "cam0", "cam1", "cam2", "cam3",
+ "cam4", "cam5", "cam-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ [email protected]_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ [email protected]_POWER_DOMAIN_IMG {
+ reg = <MT8186_POWER_DOMAIN_IMG>;
+ clocks = <&topckgen CLK_TOP_IMG1>,
+ <&imgsys1 CLK_IMG1_GALS_IMG1>;
+ clock-names = "img0", "img-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ [email protected]_POWER_DOMAIN_IMG2 {
+ reg = <MT8186_POWER_DOMAIN_IMG2>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ [email protected]_POWER_DOMAIN_IPE {
+ reg = <MT8186_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE>,
+ <&ipesys CLK_IPE_LARB19>,
+ <&ipesys CLK_IPE_LARB20>,
+ <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_GALS_IPE>;
+ clock-names = "ipe0", "ipe-0", "ipe-1", "ipe-2",
+ "ipe-3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_VENC {
+ reg = <MT8186_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_VENC>,
+ <&vencsys CLK_VENC_CKE1_VENC>;
+ clock-names = "venc0", "venc-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ [email protected]_POWER_DOMAIN_WPE {
+ reg = <MT8186_POWER_DOMAIN_WPE>;
+ clocks = <&topckgen CLK_TOP_WPE>,
+ <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
+ <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
+ clock-names = "wpe0", "wpe-0", "wpe-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
watchdog: [email protected] {
compatible = "mediatek,mt8186-wdt",
"mediatek,mt6589-wdt";
--
2.18.0

2022-09-23 13:29:41

by Allen-KH Cheng

[permalink] [raw]
Subject: [PATCH 4/5] arm64: dts: mt8186: Add dpi node

Add dpi node for mt8186 SoC.

Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 68f06bef88f3..c6809fdc7d15 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -976,6 +976,25 @@
power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
};

+ dsi0: [email protected] {
+ compatible = "mediatek,mt8186-dsi";
+ reg = <0 0x14013000 0 0x1000>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+ interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DSI0>,
+ <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+
+ port {
+ dsi_out: endpoint { };
+ };
+ };
+
iommu_mm: [email protected] {
compatible = "mediatek,mt8186-iommu-mm";
reg = <0 0x14016000 0 0x1000>;
--
2.18.0

2022-09-23 18:24:11

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 1/5] dt-bindings: mfd: mediatek: Add scpsys compatible for mt8186

On 23/09/2022 15:11, Allen-KH Cheng wrote:
> Add a new scpsys compatible for mt8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>


Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2022-09-26 08:01:07

by Lee Jones

[permalink] [raw]
Subject: Re: [PATCH 1/5] dt-bindings: mfd: mediatek: Add scpsys compatible for mt8186

On Fri, 23 Sep 2022, Allen-KH Cheng wrote:

> Add a new scpsys compatible for mt8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> .../devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml | 1 +
> 1 file changed, 1 insertion(+)

Applied, thanks.

--
Lee Jones [李琼斯]

Subject: Re: [PATCH 2/5] arm64: dts: mt8186: Add power domains controller

Il 23/09/22 15:11, Allen-KH Cheng ha scritto:
> Add power domains controller for mt8186 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++
> 1 file changed, 188 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 64693c17af9e..833e7037fe22 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -329,6 +329,194 @@
> #interrupt-cells = <2>;
> };
>
> + scpsys: [email protected] {
> + compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
> + reg = <0 0x10006000 0 0x1000>;
> +
> + /* System Power Manager */
> + spm: power-controller {
> + compatible = "mediatek,mt8186-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +

..snip..

> + [email protected]_POWER_DOMAIN_DIS {
> + reg = <MT8186_POWER_DOMAIN_DIS>;
> + clocks = <&topckgen CLK_TOP_DISP>,
> + <&topckgen CLK_TOP_MDP>,
> + <&mmsys CLK_MM_SMI_INFRA>,
> + <&mmsys CLK_MM_SMI_COMMON>,
> + <&mmsys CLK_MM_SMI_GALS>,
> + <&mmsys CLK_MM_SMI_IOMMU>;
> + clock-names = "dis0", "dis1", "dis-0", "dis-1",
> + "dis-2", "dis-3";

What about using more descriptive names for clock-names?
disp, mdp, smi_infra, smi_common, smi_gals, smi_iommu

> + mediatek,infracfg = <&infracfg_ao>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + [email protected]_POWER_DOMAIN_VDEC {
> + reg = <MT8186_POWER_DOMAIN_VDEC>;
> + clocks = <&topckgen CLK_TOP_VDEC>,
> + <&vdecsys CLK_VDEC_LARB1_CKEN>;
> + clock-names = "vdec0", "vdec-0";

vdec0, larb

> + mediatek,infracfg = <&infracfg_ao>;
> + #power-domain-cells = <0>;
> + };
> +
> + [email protected]_POWER_DOMAIN_CAM {
> + reg = <MT8186_POWER_DOMAIN_CAM>;
> + clocks = <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_SENINF>,
> + <&topckgen CLK_TOP_SENINF1>,
> + <&topckgen CLK_TOP_SENINF2>,
> + <&topckgen CLK_TOP_SENINF3>,
> + <&topckgen CLK_TOP_CAMTM>,
> + <&camsys CLK_CAM2MM_GALS>;
> + clock-names = "cam0", "cam1", "cam2", "cam3",
> + "cam4", "cam5", "cam-0";

cam-top, cam0, cam1, cam2, cam3, cam-tm, gals

> + mediatek,infracfg = <&infracfg_ao>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + [email protected]_POWER_DOMAIN_CAM_RAWB {
> + reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
> + #power-domain-cells = <0>;
> + };
> +
> + [email protected]_POWER_DOMAIN_CAM_RAWA {
> + reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
> + #power-domain-cells = <0>;
> + };
> + };
> +
> + [email protected]_POWER_DOMAIN_IMG {
> + reg = <MT8186_POWER_DOMAIN_IMG>;
> + clocks = <&topckgen CLK_TOP_IMG1>,
> + <&imgsys1 CLK_IMG1_GALS_IMG1>;
> + clock-names = "img0", "img-0";

img-top, gals

> + mediatek,infracfg = <&infracfg_ao>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + [email protected]_POWER_DOMAIN_IMG2 {
> + reg = <MT8186_POWER_DOMAIN_IMG2>;
> + #power-domain-cells = <0>;
> + };
> + };
> +
> + [email protected]_POWER_DOMAIN_IPE {
> + reg = <MT8186_POWER_DOMAIN_IPE>;
> + clocks = <&topckgen CLK_TOP_IPE>,
> + <&ipesys CLK_IPE_LARB19>,
> + <&ipesys CLK_IPE_LARB20>,
> + <&ipesys CLK_IPE_SMI_SUBCOM>,
> + <&ipesys CLK_IPE_GALS_IPE>;
> + clock-names = "ipe0", "ipe-0", "ipe-1", "ipe-2",
> + "ipe-3";

ipe-top, ipe-larb0, ipe-larb1, ipe-smi, ipe-gals

> + mediatek,infracfg = <&infracfg_ao>;
> + #power-domain-cells = <0>;
> + };
> +
> + [email protected]_POWER_DOMAIN_VENC {
> + reg = <MT8186_POWER_DOMAIN_VENC>;
> + clocks = <&topckgen CLK_TOP_VENC>,
> + <&vencsys CLK_VENC_CKE1_VENC>;
> + clock-names = "venc0", "venc-0";

venc0, larb

> + mediatek,infracfg = <&infracfg_ao>;
> + #power-domain-cells = <0>;
> + };
> +
> + [email protected]_POWER_DOMAIN_WPE {
> + reg = <MT8186_POWER_DOMAIN_WPE>;
> + clocks = <&topckgen CLK_TOP_WPE>,
> + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
> + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
> + clock-names = "wpe0", "wpe-0", "wpe-1";

wpe0, larb-ck, larb-pclk

Regards,
Angelo