The StarFive JH7110 SoC has four RISC-V cores,
and it supports up to 4 cpu frequency loads.
This patchset adds the compatible strings into the allowlist
for supporting the generic cpufreq driver on JH7110 SoC.
Also, it enables the axp15060 pmic for the cpu power source.
The series has been tested on the VisionFive 2 boards which
are equipped with JH7110 SoC and axp15060 pmic.
This patchset is based on v6.3-rc4 with these patches applied:
[1] ("Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC")
https://lore.kernel.org/all/[email protected]/
[2] ("Add X-Powers AXP15060 PMIC support")
https://lore.kernel.org/all/TY3P286MB2611A814E580C96DC6F187B798969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
Changes since v2:
- Fix the new blank line at EOF issue in dtsi.
Changes since v1:
- Fix dts node naming issues.
- Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
- Follow the alphabetical order to place the cpufreq dt allowlist.
---
v1: https://lore.kernel.org/all/[email protected]/
v2: https://lore.kernel.org/lkml/[email protected]/
Mason Huo (3):
riscv: dts: starfive: Enable axp15060 pmic for cpufreq
cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
riscv: dts: starfive: Add cpu scaling for JH7110 SoC
.../jh7110-starfive-visionfive-2.dtsi | 30 +++++++++++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
3 files changed, 65 insertions(+)
base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
--
2.39.2
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
It supports up to 4 cpu frequency loads.
Signed-off-by: Mason Huo <[email protected]>
---
.../jh7110-starfive-visionfive-2.dtsi | 16 +++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index cca1c8040801..43a9dbb839d2 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -227,3 +227,19 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&U74_1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+ cpu-supply = <&vdd_cpu>;
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7eef88d2cedb 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -53,6 +53,9 @@ U74_1: cpu@1 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -79,6 +82,9 @@ U74_2: cpu@2 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -105,6 +111,9 @@ U74_3: cpu@3 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -131,6 +140,9 @@ U74_4: cpu@4 {
next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc_zba_zbb";
tlb-split;
+ operating-points-v2 = <&cpu_opp>;
+ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
+ clock-names = "cpu";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@@ -164,6 +176,27 @@ core4 {
};
};
+ cpu_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1040000>;
+ };
+ };
+
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
--
2.39.2
Hi Conor & Shengyu,
Thanks for your review, and is there any comments about these v3 patches?
Thanks
Mason
On 2023/4/21 11:14, Mason Huo wrote:
> The StarFive JH7110 SoC has four RISC-V cores,
> and it supports up to 4 cpu frequency loads.
>
> This patchset adds the compatible strings into the allowlist
> for supporting the generic cpufreq driver on JH7110 SoC.
> Also, it enables the axp15060 pmic for the cpu power source.
>
> The series has been tested on the VisionFive 2 boards which
> are equipped with JH7110 SoC and axp15060 pmic.
>
>
> This patchset is based on v6.3-rc4 with these patches applied:
> [1] ("Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC")
> https://lore.kernel.org/all/[email protected]/
> [2] ("Add X-Powers AXP15060 PMIC support")
> https://lore.kernel.org/all/TY3P286MB2611A814E580C96DC6F187B798969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
>
> Changes since v2:
> - Fix the new blank line at EOF issue in dtsi.
>
> Changes since v1:
> - Fix dts node naming issues.
> - Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
> - Follow the alphabetical order to place the cpufreq dt allowlist.
>
> ---
> v1: https://lore.kernel.org/all/[email protected]/
> v2: https://lore.kernel.org/lkml/[email protected]/
>
> Mason Huo (3):
> riscv: dts: starfive: Enable axp15060 pmic for cpufreq
> cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
> riscv: dts: starfive: Add cpu scaling for JH7110 SoC
>
> .../jh7110-starfive-visionfive-2.dtsi | 30 +++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
> drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
> 3 files changed, 65 insertions(+)
>
> base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
On Fri, May 05, 2023 at 09:38:38AM +0800, Mason Huo wrote:
> Hi Conor & Shengyu,
>
> Thanks for your review, and is there any comments about these v3 patches?
Firstly there appears to have been some mess-up with the driver/bindings
for 1/3, so I am waiting to see if the binding gets reverted before
doing anything and secondly it's the merge window so I can't do anything
about 3/3 until next week.
Cheers,
Conor.
Hi Conor,
> On Fri, May 05, 2023 at 09:38:38AM +0800, Mason Huo wrote:
>> Hi Conor & Shengyu,
>>
>> Thanks for your review, and is there any comments about these v3 patches?
> Firstly there appears to have been some mess-up with the driver/bindings for 1/3, so I am waiting to see if the binding gets reverted before doing anything and secondly it's the merge window so I can't do anything about 3/3 until next week.
>
> Cheers,
> Conor.
Could you help to check if this patch can be moved on?
Thanks
Mason
On Mon, Jun 05, 2023 at 09:36:51AM +0000, Mason Huo wrote:
> > On Fri, May 05, 2023 at 09:38:38AM +0800, Mason Huo wrote:
> >> Thanks for your review, and is there any comments about these v3 patches?
>
> > Firstly there appears to have been some mess-up with the driver/bindings
> > for 1/3, so I am waiting to see if the binding gets reverted before
> > doing anything and secondly it's the merge window so I can't do anything
> > about 3/3 until next week.
> Could you help to check if this patch can be moved on?
The dependencies are in, I guess when I went checking through things on
patchwork after the merge window I spotted some issue & didn't reply to
the patch. So sorry about that.
The issue that I must've spotted is that patch 1/3 doesn't pass
dtbs_check:
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: pmic@36: 'interrupts' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: pmic@36: '#interrupt-cells' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: pmic@36: 'interrupt-controller' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: pmic@36: 'interrupts' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: pmic@36: '#interrupt-cells' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: pmic@36: 'interrupt-controller' is a required property
From schema: Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
Could you please fix that up & resend the 2 unapplied patches?
Cheers,
Conor.