This series adds support for running IGT (Intel GPU Tool) tests
with MediaTek display driver. The following changes will be
applied:
1. Add a new API for creating GCE thread loop to retrieve CRCs
from the hardware component
2. Support hardware CRC calculation in both VDOSYS0 and VDOSYS1
3. Support alpha blending in both VDOSYS0 and VDOSYS1
Changes in v2:
- Simplify CMDQ by adding commands that are currently used only
- Integrate CRC related codes into new APIs for Mixer and OVL to reuse
- Add CPU version CRC retrieval when CMDQ is disabled
Hsiao Chien Sung (11):
soc: mediatek: Add register definitions for GCE
soc: mediatek: Support GCE jump to absolute
soc: mediatek: Disable 9-bit alpha in ETHDR
drm/mediatek: Add OVL compatible name for MT8195
drm/mediatek: Adjust DRM mode configs for IGT
drm/mediatek: Support alpha blending in display driver
drm/mediatek: Support alpha blending in VDOSYS0
drm/mediatek: Support alpha blending in VDOSYS1
drm/mediatek: Support CRC in display driver
drm/mediatek: Support CRC in VDOSYS0
drm/mediatek: Support CRC in VDOSYS1
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 309 ++++++++++++++++--
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 21 ++
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 258 ++++++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 39 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 35 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 12 +-
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 11 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 121 ++++++-
drivers/gpu/drm/mediatek/mtk_ethdr.h | 5 +
drivers/soc/mediatek/mtk-cmdq-helper.c | 16 +
drivers/soc/mediatek/mtk-mmsys.c | 1 +
include/linux/soc/mediatek/mtk-cmdq.h | 12 +
14 files changed, 806 insertions(+), 46 deletions(-)
--
2.18.0
We choose Mixer as CRC generator in VDOSYS1 since
its frame done event will trigger vblanks, we can know
when is safe to retrieve CRC of the frame.
In VDOSYS1, there's no image procession after Mixer,
unlike OVL in VDOSYS0, Mixer's CRC will include all the
effects that are applied to the frame.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 21 ++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 73 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 5 ++
5 files changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 3e2f8084913c..ac8468917a2e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -129,6 +129,9 @@ unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev);
const u32 *mtk_ovl_adaptor_get_formats(struct device *dev);
size_t mtk_ovl_adaptor_get_num_formats(struct device *dev);
+size_t mtk_ovl_adaptor_crc_cnt(struct device *dev);
+u32 *mtk_ovl_adaptor_crc_entry(struct device *dev);
+void mtk_ovl_adaptor_crc_read(struct device *dev);
void mtk_rdma_bypass_shadow(struct device *dev);
int mtk_rdma_clk_enable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 6bf6367853fb..8fe706ccee72 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -160,6 +160,27 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
}
+size_t mtk_ovl_adaptor_crc_cnt(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ return mtk_ethdr_crc_cnt(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+u32 *mtk_ovl_adaptor_crc_entry(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ return mtk_ethdr_crc_entry(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+void mtk_ovl_adaptor_crc_read(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_crc_read(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b8b3884dfa63..7dfb37ae2c80 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -400,6 +400,9 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
.clk_enable = mtk_ovl_adaptor_clk_enable,
.clk_disable = mtk_ovl_adaptor_clk_disable,
.config = mtk_ovl_adaptor_config,
+ .crc_cnt = mtk_ovl_adaptor_crc_cnt,
+ .crc_entry = mtk_ovl_adaptor_crc_entry,
+ .crc_read = mtk_ovl_adaptor_crc_read,
.start = mtk_ovl_adaptor_start,
.stop = mtk_ovl_adaptor_stop,
.layer_nr = mtk_ovl_adaptor_layer_nr,
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index a41b3950e081..693b9a438a3d 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -24,6 +24,9 @@
#define MIX_FME_CPL_INTEN BIT(1)
#define MIX_INTSTA 0x8
#define MIX_EN 0xc
+#define MIX_TRIG 0x10
+#define MIX_TRIG_CRC_EN BIT(8)
+#define MIX_TRIG_CRC_RST BIT(9)
#define MIX_RST 0x14
#define MIX_ROI_SIZE 0x18
#define MIX_DATAPATH_CON 0x1c
@@ -39,6 +42,11 @@
#define PREMULTI_SOURCE (3 << 12)
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+
+/* CRC register offsets for odd and even lines */
+#define MIX_CRC_ODD 0x110
+#define MIX_CRC_EVEN 0x114
+
#define MIX_FUNC_DCM0 0x120
#define MIX_FUNC_DCM1 0x124
#define MIX_FUNC_DCM_ENABLE 0xffffffff
@@ -74,6 +82,17 @@ struct mtk_ethdr_comp {
struct cmdq_client_reg cmdq_base;
};
+/**
+ * struct mtk_ethdr - ethdr driver data
+ * @ethdr_comp: components of ethdr(mixer)
+ * @ethdr_clk: clocks of ethdr components
+ * @mmsys_dev: mmsys device that ethdr binds to
+ * @vblank_cb: callback function when vblank irq occurs
+ * @vblank_cb_data: data fo vblank callback
+ * @irq: irq that triggers irq handler
+ * @reset_ctl: reset control of ethdr
+ * @crc: crc information
+ */
struct mtk_ethdr {
struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
@@ -82,6 +101,7 @@ struct mtk_ethdr {
void *vblank_cb_data;
int irq;
struct reset_control *reset_ctl;
+ struct mtk_drm_crc crc;
};
static const char * const ethdr_clk_str[] = {
@@ -100,6 +120,32 @@ static const char * const ethdr_clk_str[] = {
"vdo_be_async",
};
+static const u32 ethdr_crc_ofs[] = {
+ MIX_CRC_ODD,
+ MIX_CRC_EVEN,
+};
+
+size_t mtk_ethdr_crc_cnt(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ return priv->crc.cnt;
+}
+
+u32 *mtk_ethdr_crc_entry(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ return priv->crc.va;
+}
+
+void mtk_ethdr_crc_read(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_drm_crc_read(&priv->crc, priv->ethdr_comp[ETHDR_MIXER].regs);
+}
+
void mtk_ethdr_register_vblank_cb(struct device *dev,
void (*vblank_cb)(void *),
void *vblank_cb_data)
@@ -267,6 +313,13 @@ void mtk_ethdr_start(struct device *dev)
struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
writel(1, mixer->regs + MIX_EN);
+
+ if (priv->crc.cnt) {
+ writel(MIX_TRIG_CRC_EN, mixer->regs + MIX_TRIG);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ mtk_drm_crc_cmdq_start(&priv->crc);
+#endif
+ }
}
void mtk_ethdr_stop(struct device *dev)
@@ -274,6 +327,9 @@ void mtk_ethdr_stop(struct device *dev)
struct mtk_ethdr *priv = dev_get_drvdata(dev);
struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ mtk_drm_crc_cmdq_stop(&priv->crc);
+#endif
writel(0, mixer->regs + MIX_EN);
writel(1, mixer->regs + MIX_RST);
reset_control_reset(priv->reset_ctl);
@@ -328,6 +384,10 @@ static int mtk_ethdr_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
+ mtk_drm_crc_init(&priv->crc,
+ ethdr_crc_ofs, ARRAY_SIZE(ethdr_crc_ofs),
+ MIX_TRIG, MIX_TRIG_CRC_RST);
+
for (i = 0; i < ETHDR_ID_MAX; i++) {
priv->ethdr_comp[i].dev = dev;
priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
@@ -336,6 +396,16 @@ static int mtk_ethdr_probe(struct platform_device *pdev)
&priv->ethdr_comp[i].cmdq_base, i);
if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+
+ if (i == ETHDR_MIXER) {
+ if (of_property_read_u32_index(dev->of_node,
+ "mediatek,gce-events", i,
+ &priv->crc.cmdq_event)) {
+ dev_warn(dev, "failed to get gce-events for crc\n");
+ }
+ priv->crc.cmdq_reg = &priv->ethdr_comp[i].cmdq_base;
+ mtk_drm_crc_cmdq_create(dev, &priv->crc);
+ }
#endif
dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i);
}
@@ -376,6 +446,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev)
static int mtk_ethdr_remove(struct platform_device *pdev)
{
+ struct mtk_ethdr *priv = dev_get_drvdata(&pdev->dev);
+
+ mtk_drm_crc_destroy(&priv->crc);
component_del(&pdev->dev, &mtk_ethdr_component_ops);
return 0;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
index 81af9edea3f7..d17d7256bd12 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.h
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -22,4 +22,9 @@ void mtk_ethdr_register_vblank_cb(struct device *dev,
void mtk_ethdr_unregister_vblank_cb(struct device *dev);
void mtk_ethdr_enable_vblank(struct device *dev);
void mtk_ethdr_disable_vblank(struct device *dev);
+
+size_t mtk_ethdr_crc_cnt(struct device *dev);
+u32 *mtk_ethdr_crc_entry(struct device *dev);
+void mtk_ethdr_crc_read(struct device *dev);
+
#endif
--
2.18.0
Support alpha blending by adding correct blend mode and
alpha property in plane initialization.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index db2f70ae060d..f87cf56fb846 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -301,6 +301,9 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
size_t num_formats)
{
int err;
+ u32 blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE);
if (!formats || !num_formats) {
DRM_ERROR("no formats for plane\n");
@@ -323,6 +326,14 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
DRM_INFO("Create rotation property failed\n");
}
+ err = drm_plane_create_alpha_property(plane);
+ if (err)
+ DRM_ERROR("failed to create property: alpha\n");
+
+ err = drm_plane_create_blend_mode_property(plane, blend_mode);
+ if (err)
+ DRM_ERROR("failed to create property: blend_mode\n");
+
drm_plane_helper_add(plane, &mtk_plane_helper_funcs);
return 0;
--
2.18.0
Support premultiply and coverage alpha blending modes.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_ethdr.c | 48 ++++++++++++++++++++++------
1 file changed, 38 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index db7ac666ec5e..a41b3950e081 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -5,6 +5,7 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_framebuffer.h>
+#include <drm/drm_blend.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/of.h>
@@ -35,6 +36,7 @@
#define MIX_SRC_L0_EN BIT(0)
#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
#define NON_PREMULTI_SOURCE (2 << 12)
+#define PREMULTI_SOURCE (3 << 12)
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
#define MIX_FUNC_DCM0 0x120
@@ -153,33 +155,59 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
struct mtk_plane_pending_state *pending = &state->pending;
unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
unsigned int align_width = ALIGN_DOWN(pending->width, 2);
- unsigned int alpha_con = 0;
+ unsigned int mix_con = NON_PREMULTI_SOURCE;
+ bool replace_src_a = false;
+
+ union format {
+ u32 raw;
+ u8 str[5];
+ } format;
dev_dbg(dev, "%s+ idx:%d", __func__, idx);
if (idx >= 4)
return;
- if (!pending->enable) {
+ if (!pending->enable || !pending->width || !pending->height) {
+ /*
+ * instead of disabling layer with MIX_SRC_CON directly
+ * set the size to 0 to avoid screen shift due to mode switch
+ */
mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
return;
}
- if (state->base.fb && state->base.fb->format->has_alpha)
- alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ mix_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA);
+
+ if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE)
+ mix_con |= PREMULTI_SOURCE;
+
+ if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
+ (state->base.fb && !state->base.fb->format->has_alpha)) {
+ /*
+ * Mixer doesn't support CONST_BLD mode,
+ * use a trick to make the output equivalent
+ */
+ replace_src_a = true;
+ }
+
+ format.raw = pending->format;
+
+ dev_dbg(dev, "L%d: %ux%u(%u,%u)%s: SCA=0x%x(%u), MIX=0x%x\n", idx,
+ pending->width, pending->height, pending->x, pending->y,
+ format.str, (state->base.alpha & MIXER_ALPHA),
+ state->base.pixel_blend_mode, mix_con);
- mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true,
- DEFAULT_9BIT_ALPHA,
+ mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA,
pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :
MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);
mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
mixer->regs, MIX_L_SRC_SIZE(idx));
mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
- mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
- 0x1ff);
- mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
- BIT(idx));
+ mtk_ddp_write(cmdq_pkt, mix_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs,
+ MIX_SRC_CON, BIT(idx));
}
void mtk_ethdr_config(struct device *dev, unsigned int w,
--
2.18.0
Add OVL compatible name for MT8195.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 93552d76b6e7..7759a06e5c0e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -715,6 +715,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8192-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8195-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt8192-disp-ovl-2l",
--
2.18.0
Add register definitions for GCE so users can use them
as a buffer to store data.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
include/linux/soc/mediatek/mtk-cmdq.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 649955d2cf5c..a253c001c861 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -14,6 +14,16 @@
#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0)))
#define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1))
+/*
+ * Every cmdq thread has its own SPRs (Specific Purpose Registers),
+ * so there are 4 * 24 (threads) = 96 SPRs in GCE that shares the
+ * same indexes below
+ */
+#define CMDQ_THR_SPR_IDX0 (0)
+#define CMDQ_THR_SPR_IDX1 (1)
+#define CMDQ_THR_SPR_IDX2 (2)
+#define CMDQ_THR_SPR_IDX3 (3)
+
struct cmdq_pkt;
struct cmdq_client_reg {
--
2.18.0
Hi, Hsiao-chien:
On Mon, 2023-09-18 at 16:42 +0800, Hsiao Chien Sung wrote:
> Support alpha blending by adding correct blend mode and
> alpha property in plane initialization.
>
> Reviewed-by: AngeloGioacchino Del Regno <
> [email protected]>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_plane.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> index db2f70ae060d..f87cf56fb846 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> @@ -301,6 +301,9 @@ int mtk_plane_init(struct drm_device *dev, struct
> drm_plane *plane,
> size_t num_formats)
> {
> int err;
> + u32 blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
> + BIT(DRM_MODE_BLEND_PREMULTI) |
> + BIT(DRM_MODE_BLEND_COVERAGE);
>
> if (!formats || !num_formats) {
> DRM_ERROR("no formats for plane\n");
> @@ -323,6 +326,14 @@ int mtk_plane_init(struct drm_device *dev,
> struct drm_plane *plane,
> DRM_INFO("Create rotation property failed\n");
> }
>
> + err = drm_plane_create_alpha_property(plane);
> + if (err)
> + DRM_ERROR("failed to create property: alpha\n");
> +
> + err = drm_plane_create_blend_mode_property(plane, blend_mode);
> + if (err)
> + DRM_ERROR("failed to create property: blend_mode\n");
Do not always enable alpha function. Enable it depend on hardware
capability.
Regards,
CK
> +
> drm_plane_helper_add(plane, &mtk_plane_helper_funcs);
>
> return 0;
Il 18/09/23 10:41, Hsiao Chien Sung ha scritto:
> Add register definitions for GCE so users can use them
> as a buffer to store data.
>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>