From: Lad Prabhakar <[email protected]>
RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrupts,
reflect the same in the DT binding doc.
RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
we just use the below to represent them:
- ec7tie1-0
- ec7tie2-0
- ec7tiovf-0
Additionally mark 'interrupt-names' property as required for all the SoCs
and update the example node in the binding doc.
Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
Signed-off-by: Lad Prabhakar <[email protected]>
---
.../renesas,rzg2l-irqc.yaml | 44 +++++++++++++++----
1 file changed, 35 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index d3b5aec0a3f7..0bc9c604a2d7 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -44,7 +44,7 @@ properties:
maxItems: 1
interrupts:
- minItems: 41
+ minItems: 45
items:
- description: NMI interrupt
- description: IRQ0 interrupt
@@ -88,9 +88,15 @@ properties:
- description: GPIO interrupt, TINT30
- description: GPIO interrupt, TINT31
- description: Bus error interrupt
+ - description: ECCRAM0 1bit error interrupt
+ - description: ECCRAM0 2bit error interrupt
+ - description: ECCRAM0 error overflow interrupt
+ - description: ECCRAM1 1bit error interrupt
+ - description: ECCRAM1 2bit error interrupt
+ - description: ECCRAM1 error overflow interrupt
interrupt-names:
- minItems: 41
+ minItems: 45
items:
- const: nmi
- const: irq0
@@ -134,6 +140,12 @@ properties:
- const: tint30
- const: tint31
- const: bus-err
+ - const: ec7tie1-0
+ - const: ec7tie2-0
+ - const: ec7tiovf-0
+ - const: ec7tie1-1
+ - const: ec7tie2-1
+ - const: ec7tiovf-1
clocks:
maxItems: 2
@@ -156,6 +168,7 @@ required:
- interrupt-controller
- reg
- interrupts
+ - interrupt-names
- clocks
- clock-names
- power-domains
@@ -169,16 +182,19 @@ allOf:
compatible:
contains:
enum:
- - renesas,r9a07g043u-irqc
- renesas,r9a08g045-irqc
then:
properties:
interrupts:
- minItems: 42
+ maxItems: 45
interrupt-names:
- minItems: 42
- required:
- - interrupt-names
+ maxItems: 45
+ else:
+ properties:
+ interrupts:
+ minItems: 48
+ interrupt-names:
+ minItems: 48
unevaluatedProperties: false
@@ -233,7 +249,14 @@ examples:
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
@@ -244,7 +267,10 @@ examples:
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
- "tint28", "tint29", "tint30", "tint31";
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err", "ec7tie1-0", "ec7tie2-0",
+ "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+ "ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";
--
2.34.1
On Fri, Feb 02, 2024 at 09:39:05AM +0000, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrupts,
> reflect the same in the DT binding doc.
Renesas' naming scheme really does not help here, but using the
shorthands in the commit message when the diff uses the long form names
is not the easiest thing to follow. (:
>
> RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
> we just use the below to represent them:
> - ec7tie1-0
> - ec7tie2-0
> - ec7tiovf-0
I think this information would be good in the itemised description,
since that claims these interrupt are only for ECCRAM0.
> Additionally mark 'interrupt-names' property as required for all the SoCs
> and update the example node in the binding doc.
Why? You've not given a reason for doing this, so it just seems
gratuitous.
Thanks,
Conor.
>
> Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
> Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> .../renesas,rzg2l-irqc.yaml | 44 +++++++++++++++----
> 1 file changed, 35 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> index d3b5aec0a3f7..0bc9c604a2d7 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -44,7 +44,7 @@ properties:
> maxItems: 1
>
> interrupts:
> - minItems: 41
> + minItems: 45
> items:
> - description: NMI interrupt
> - description: IRQ0 interrupt
> @@ -88,9 +88,15 @@ properties:
> - description: GPIO interrupt, TINT30
> - description: GPIO interrupt, TINT31
> - description: Bus error interrupt
> + - description: ECCRAM0 1bit error interrupt
> + - description: ECCRAM0 2bit error interrupt
> + - description: ECCRAM0 error overflow interrupt
> + - description: ECCRAM1 1bit error interrupt
> + - description: ECCRAM1 2bit error interrupt
> + - description: ECCRAM1 error overflow interrupt
>
> interrupt-names:
> - minItems: 41
> + minItems: 45
> items:
> - const: nmi
> - const: irq0
> @@ -134,6 +140,12 @@ properties:
> - const: tint30
> - const: tint31
> - const: bus-err
> + - const: ec7tie1-0
> + - const: ec7tie2-0
> + - const: ec7tiovf-0
> + - const: ec7tie1-1
> + - const: ec7tie2-1
> + - const: ec7tiovf-1
>
> clocks:
> maxItems: 2
> @@ -156,6 +168,7 @@ required:
> - interrupt-controller
> - reg
> - interrupts
> + - interrupt-names
> - clocks
> - clock-names
> - power-domains
> @@ -169,16 +182,19 @@ allOf:
> compatible:
> contains:
> enum:
> - - renesas,r9a07g043u-irqc
> - renesas,r9a08g045-irqc
> then:
> properties:
> interrupts:
> - minItems: 42
> + maxItems: 45
> interrupt-names:
> - minItems: 42
> - required:
> - - interrupt-names
> + maxItems: 45
> + else:
> + properties:
> + interrupts:
> + minItems: 48
> + interrupt-names:
> + minItems: 48
>
> unevaluatedProperties: false
>
> @@ -233,7 +249,14 @@ examples:
> <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
> interrupt-names = "nmi",
> "irq0", "irq1", "irq2", "irq3",
> "irq4", "irq5", "irq6", "irq7",
> @@ -244,7 +267,10 @@ examples:
> "tint16", "tint17", "tint18", "tint19",
> "tint20", "tint21", "tint22", "tint23",
> "tint24", "tint25", "tint26", "tint27",
> - "tint28", "tint29", "tint30", "tint31";
> + "tint28", "tint29", "tint30", "tint31",
> + "bus-err", "ec7tie1-0", "ec7tie2-0",
> + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
> + "ec7tiovf-1";
> clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
> <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
> clock-names = "clk", "pclk";
> --
> 2.34.1
>
Hi Conor,
Thank you for the review.
On Fri, Feb 2, 2024 at 5:07 PM Conor Dooley <[email protected]> wrote:
>
> On Fri, Feb 02, 2024 at 09:39:05AM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrupts,
> > reflect the same in the DT binding doc.
>
> Renesas' naming scheme really does not help here, but using the
> shorthands in the commit message when the diff uses the long form names
> is not the easiest thing to follow. (:
>
Sure I'll elabore the SoCs according to the binding doc so that it's more clear.
> >
> > RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
> > we just use the below to represent them:
> > - ec7tie1-0
> > - ec7tie2-0
> > - ec7tiovf-0
>
> I think this information would be good in the itemised description,
> since that claims these interrupt are only for ECCRAM0.
>
Sure 'll update as below:
+ - const: ec7tie1-0 # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+ - const: ec7tie2-0 # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+ - const: ec7tiovf-0 # For RZ/G3S SoC ECCRAM0/1 interrupts combined
>
> > Additionally mark 'interrupt-names' property as required for all the SoCs
> > and update the example node in the binding doc.
>
> Why? You've not given a reason for doing this, so it just seems
> gratuitous.
>
Previous assumption was just the RZ/G2UL and RZ/G3S had the bus-err
and eccram error interrupts, but where as in actual all the above SoCs
have this interrupt so making interrupt-names as required so we can
parse them based on names.
Cheers,
Prabhakar