Hi,
In addition to AES-NI, Intel will provide PCLMULQDQ-NI (carry-less
multiplication) in future CPU to accelerate GCM mode. The document can
be found here:
http://software.intel.com/en-us/articles/carry-less-multiplication-and-its-usage-for-computing-the-gcm-mode/
It follows the same design as that of AES-NI, that is, XMM registers are
used.
To accelerate GCM with it, I make the following design:
1. Implement ghash as an ahash algorithm, Use ghash in gcm
implementation.
2. Provide a new implementation of ghash with PCLMULQDQ-NI.
What do you think about that?
Best Regards,
Huang Ying
On Wed, Mar 18, 2009 at 04:52:12PM +0800, Huang Ying wrote:
>
> To accelerate GCM with it, I make the following design:
>
> 1. Implement ghash as an ahash algorithm, Use ghash in gcm
> implementation.
> 2. Provide a new implementation of ghash with PCLMULQDQ-NI.
>
> What do you think about that?
Sounds OK to me. I presume the choice of ahash instead of shash
is due to the use of XMM registers, just like AES?
Cheers,
--
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On Sun, 2009-03-29 at 15:43 +0800, Herbert Xu wrote:
> On Wed, Mar 18, 2009 at 04:52:12PM +0800, Huang Ying wrote:
> >
> > To accelerate GCM with it, I make the following design:
> >
> > 1. Implement ghash as an ahash algorithm, Use ghash in gcm
> > implementation.
> > 2. Provide a new implementation of ghash with PCLMULQDQ-NI.
> >
> > What do you think about that?
>
> Sounds OK to me. I presume the choice of ahash instead of shash
> is due to the use of XMM registers, just like AES?
Yes, because PCLMULQDQ touches XMMs too. Just like AES, there is a raw
shash: ghash-clmul and an ahash via cryptd(ghash-clmul).
Best Regards,
Huang Ying