This is used by AES-NI accelerated AES implementation and PCLMULQDQ
accelerated GHASH implementation.
Signed-off-by: Huang Ying <[email protected]>
---
arch/x86/crypto/aesni-intel_glue.c | 7 -------
arch/x86/include/asm/i387.h | 7 +++++++
2 files changed, 7 insertions(+), 7 deletions(-)
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -59,13 +59,6 @@ asmlinkage void aesni_cbc_enc(struct cry
asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,
const u8 *in, unsigned int len, u8 *iv);
-static inline int kernel_fpu_using(void)
-{
- if (in_interrupt() && !(read_cr0() & X86_CR0_TS))
- return 1;
- return 0;
-}
* Huang Ying <[email protected]> wrote:
> This is used by AES-NI accelerated AES implementation and PCLMULQDQ
> accelerated GHASH implementation.
>
> Signed-off-by: Huang Ying <[email protected]>
>
> ---
> arch/x86/crypto/aesni-intel_glue.c | 7 -------
> arch/x86/include/asm/i387.h | 7 +++++++
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> --- a/arch/x86/crypto/aesni-intel_glue.c
> +++ b/arch/x86/crypto/aesni-intel_glue.c
> @@ -59,13 +59,6 @@ asmlinkage void aesni_cbc_enc(struct cry
> asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,
> const u8 *in, unsigned int len, u8 *iv);
>
> -static inline int kernel_fpu_using(void)
> -{
> - if (in_interrupt() && !(read_cr0() & X86_CR0_TS))
> - return 1;
> - return 0;
> -}
> -
> static inline struct crypto_aes_ctx *aes_ctx(void *raw_ctx)
> {
> unsigned long addr = (unsigned long)raw_ctx;
> --- a/arch/x86/include/asm/i387.h
> +++ b/arch/x86/include/asm/i387.h
> @@ -302,6 +302,13 @@ static inline void kernel_fpu_end(void)
> preempt_enable();
> }
>
> +static inline int kernel_fpu_using(void)
> +{
> + if (in_interrupt() && !(read_cr0() & X86_CR0_TS))
> + return 1;
> + return 0;
> +}
> +
Looks sane to me. Herbert, do you ack it?
Ingo
Ingo Molnar wrote:
>>
>> +static inline int kernel_fpu_using(void)
>> +{
>> + if (in_interrupt() && !(read_cr0() & X86_CR0_TS))
>> + return 1;
>> + return 0;
>> +}
>> +
>
> Looks sane to me. Herbert, do you ack it?
>
Although I have to say, the structure of:
if (boolean test)
return 1;
return 0;
... truly was hit with the ugly stick. It really should be:
static inline bool kernel_fpu_using(void)
{
return in_interrupt() && !(read_cr0() && C86_CR0_TS);
}
Huang: if I recall correctly, these functions were originally designed
to deal with the fact that VIA processors generate spurious #TS faults
due to broken design of the Padlock instructions. The AES and PCLMUL
instructions actually use SSE registers and so will require different
structure.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
On Wed, Jun 17, 2009 at 10:06:44AM -0700, H. Peter Anvin wrote:
> Ingo Molnar wrote:
> >>
> >> +static inline int kernel_fpu_using(void)
> >> +{
> >> + if (in_interrupt() && !(read_cr0() & X86_CR0_TS))
> >> + return 1;
> >> + return 0;
> >> +}
> >> +
> >
> > Looks sane to me. Herbert, do you ack it?
Ack. Please pick it up in your tree. Thanks!
> Huang: if I recall correctly, these functions were originally designed
> to deal with the fact that VIA processors generate spurious #TS faults
> due to broken design of the Padlock instructions. The AES and PCLMUL
> instructions actually use SSE registers and so will require different
> structure.
No irq_ts_save was the one designed for the VIA, the Intel stuff
does save the FPU state.
Cheers,
--
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Thu, 2009-06-18 at 01:06 +0800, H. Peter Anvin wrote:
> Ingo Molnar wrote:
> >>
> >> +static inline int kernel_fpu_using(void)
> >> +{
> >> + if (in_interrupt() && !(read_cr0() & X86_CR0_TS))
> >> + return 1;
> >> + return 0;
> >> +}
> >> +
> >
> > Looks sane to me. Herbert, do you ack it?
> >
>
> Although I have to say, the structure of:
>
> if (boolean test)
> return 1;
> return 0;
>
> ... truly was hit with the ugly stick. It really should be:
>
> static inline bool kernel_fpu_using(void)
> {
> return in_interrupt() && !(read_cr0() && C86_CR0_TS);
> }
Yes. This is better. I will change this.
> Huang: if I recall correctly, these functions were originally designed
> to deal with the fact that VIA processors generate spurious #TS faults
> due to broken design of the Padlock instructions. The AES and PCLMUL
> instructions actually use SSE registers and so will require different
> structure.
They are a little different. VIA want to make sure that they can deal
with spurious #TS faults, while AES and PCLMUL need to check whether
MMX/SSE registers are available.
After some thinking, I think something as follow may be more
appropriate:
/* This may be useful for someone else */
static inline bool fpu_using(void)
{
return !(read_cr0() & X86_CR0_TS);
}
static inline bool irq_fpu_using(void)
{
return in_interrupt() && fpu_using();
}
Best Regards,
Huang Ying
Herbert Xu wrote:
> On Wed, Jun 17, 2009 at 10:06:44AM -0700, H. Peter Anvin wrote:
>
>> Huang: if I recall correctly, these functions were originally designed
>> to deal with the fact that VIA processors generate spurious #TS faults
>> due to broken design of the Padlock instructions. The AES and PCLMUL
>> instructions actually use SSE registers and so will require different
>> structure.
>
> No irq_ts_save was the one designed for the VIA, the Intel stuff
> does save the FPU state.
>
Ah, sorry, misremembered. Great! Will apply.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
Huang Ying wrote:
>
> After some thinking, I think something as follow may be more
> appropriate:
>
> /* This may be useful for someone else */
> static inline bool fpu_using(void)
> {
> return !(read_cr0() & X86_CR0_TS);
> }
>
> static inline bool irq_fpu_using(void)
> {
> return in_interrupt() && fpu_using();
> }
>
Yes, looks good. I'll pull in the patch as soon as I get it.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.