This adds device tree bindings for the ixp4xx crypto engine.
Cc: [email protected]
Signed-off-by: Linus Walleij <[email protected]>
---
Herbert, David: This can be applied separately once we are
happy with the bindings, alternatively it can be merged
with the support code into ARM SoC.
---
.../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
new file mode 100644
index 000000000000..28d75f4f9a76
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2018 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx cryptographic engine
+
+maintainers:
+ - Linus Walleij <[email protected]>
+
+description: |
+ The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
+ (Network Processing Engine). Since it is not a device on its own
+ it is defined as a subnode of the NPE, if crypto support is
+ available on the platform.
+
+properties:
+ compatible:
+ const: intel,ixp4xx-crypto
+
+ intel,npe-handle:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: phandle to the NPE this ethernet instance is using
+ and the instance to use in the second cell
+
+ queue-rx:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: phandle to the RX queue on the NPE
+
+ queue-txready:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: phandle to the TX READY queue on the NPE
+
+required:
+ - compatible
+ - intel,npe-handle
+ - queue-rx
+ - queue-txready
+
+additionalProperties: false
+
+examples:
+ - |
+ npe: npe@c8006000 {
+ compatible = "intel,ixp4xx-network-processing-engine";
+ reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+
+ crypto {
+ compatible = "intel,ixp4xx-crypto";
+ intel,npe-handle = <&npe 2>;
+ queue-rx = <&qmgr 30>;
+ queue-txready = <&qmgr 29>;
+ };
+ };
--
2.30.2
On Mon, 10 May 2021 23:36:33 +0200, Linus Walleij wrote:
> This adds device tree bindings for the ixp4xx crypto engine.
>
> Cc: [email protected]
> Signed-off-by: Linus Walleij <[email protected]>
> ---
> Herbert, David: This can be applied separately once we are
> happy with the bindings, alternatively it can be merged
> with the support code into ARM SoC.
> ---
> .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.example.dt.yaml: npe@c8006000: 'crypto' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
See https://patchwork.ozlabs.org/patch/1476741
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Mon, May 10, 2021 at 11:36:33PM +0200, Linus Walleij wrote:
> This adds device tree bindings for the ixp4xx crypto engine.
>
> Cc: [email protected]
> Signed-off-by: Linus Walleij <[email protected]>
> ---
> Herbert, David: This can be applied separately once we are
> happy with the bindings, alternatively it can be merged
> with the support code into ARM SoC.
> ---
> .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
>
> diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
> new file mode 100644
> index 000000000000..28d75f4f9a76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2018 Linaro Ltd.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Intel IXP4xx cryptographic engine
> +
> +maintainers:
> + - Linus Walleij <[email protected]>
> +
> +description: |
> + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
> + (Network Processing Engine). Since it is not a device on its own
> + it is defined as a subnode of the NPE, if crypto support is
> + available on the platform.
> +
> +properties:
> + compatible:
> + const: intel,ixp4xx-crypto
> +
> + intel,npe-handle:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + maxItems: 1
> + description: phandle to the NPE this ethernet instance is using
> + and the instance to use in the second cell
> +
> + queue-rx:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + maxItems: 1
> + description: phandle to the RX queue on the NPE
> +
> + queue-txready:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + maxItems: 1
> + description: phandle to the TX READY queue on the NPE
> +
> +required:
> + - compatible
> + - intel,npe-handle
> + - queue-rx
> + - queue-txready
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + npe: npe@c8006000 {
> + compatible = "intel,ixp4xx-network-processing-engine";
> + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
> +
> + crypto {
The parent schema needs to define 'crypto' and have a ref to this
schema. I'd put the example there rather than piecemeal.
> + compatible = "intel,ixp4xx-crypto";
> + intel,npe-handle = <&npe 2>;
A bit redundant to have a phandle to the parent.
> + queue-rx = <&qmgr 30>;
> + queue-txready = <&qmgr 29>;
> + };
> + };
> --
> 2.30.2
>