Remove user types across qat code base and replace packed attribute in
etr ring struct which causes a split lock.
These changes are on top of "crypto: qat - fix parameter check in aead
encryption" (https://patchwork.kernel.org/patch/11574001/)
Giovanni Cabiddu (1):
crypto: qat - remove packed attribute in etr structs
Wojciech Ziemba (2):
crypto: qat - replace user types with kernel u types
crypto: qat - replace user types with kernel ABI __u types
.../crypto/qat/qat_common/adf_accel_devices.h | 54 +++---
.../crypto/qat/qat_common/adf_accel_engine.c | 4 +-
drivers/crypto/qat/qat_common/adf_aer.c | 2 +-
.../crypto/qat/qat_common/adf_cfg_common.h | 24 +--
drivers/crypto/qat/qat_common/adf_cfg_user.h | 10 +-
.../crypto/qat/qat_common/adf_common_drv.h | 12 +-
drivers/crypto/qat/qat_common/adf_ctl_drv.c | 4 +-
drivers/crypto/qat/qat_common/adf_dev_mgr.c | 8 +-
drivers/crypto/qat/qat_common/adf_transport.c | 62 +++----
drivers/crypto/qat/qat_common/adf_transport.h | 4 +-
.../qat_common/adf_transport_access_macros.h | 6 +-
.../qat/qat_common/adf_transport_internal.h | 27 ++-
drivers/crypto/qat/qat_common/icp_qat_fw.h | 58 +++----
.../qat/qat_common/icp_qat_fw_init_admin.h | 46 ++---
drivers/crypto/qat/qat_common/icp_qat_fw_la.h | 158 +++++++++---------
.../crypto/qat/qat_common/icp_qat_fw_pke.h | 52 +++---
drivers/crypto/qat/qat_common/icp_qat_hw.h | 16 +-
drivers/crypto/qat/qat_common/icp_qat_uclo.h | 6 +-
drivers/crypto/qat/qat_common/qat_algs.c | 54 +++---
drivers/crypto/qat/qat_common/qat_asym_algs.c | 12 +-
drivers/crypto/qat/qat_common/qat_hal.c | 40 ++---
drivers/crypto/qat/qat_common/qat_uclo.c | 20 +--
.../qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 26 +--
23 files changed, 352 insertions(+), 353 deletions(-)
--
2.26.2
From: Wojciech Ziemba <[email protected]>
Kernel source code should not contain stdint.h types.
This patch replaces uintXX_t types with kernel space ABI types.
Signed-off-by: Wojciech Ziemba <[email protected]>
Signed-off-by: Giovanni Cabiddu <[email protected]>
---
.../crypto/qat/qat_common/adf_cfg_common.h | 24 +--
drivers/crypto/qat/qat_common/adf_cfg_user.h | 10 +-
drivers/crypto/qat/qat_common/icp_qat_fw.h | 58 +++----
.../qat/qat_common/icp_qat_fw_init_admin.h | 46 ++---
drivers/crypto/qat/qat_common/icp_qat_fw_la.h | 158 +++++++++---------
.../crypto/qat/qat_common/icp_qat_fw_pke.h | 52 +++---
drivers/crypto/qat/qat_common/icp_qat_hw.h | 16 +-
7 files changed, 182 insertions(+), 182 deletions(-)
diff --git a/drivers/crypto/qat/qat_common/adf_cfg_common.h b/drivers/crypto/qat/qat_common/adf_cfg_common.h
index e818033c1012..1ef46ccfba47 100644
--- a/drivers/crypto/qat/qat_common/adf_cfg_common.h
+++ b/drivers/crypto/qat/qat_common/adf_cfg_common.h
@@ -37,16 +37,16 @@ enum adf_device_type {
struct adf_dev_status_info {
enum adf_device_type type;
- u32 accel_id;
- u32 instance_id;
- uint8_t num_ae;
- uint8_t num_accel;
- uint8_t num_logical_accel;
- uint8_t banks_per_accel;
- uint8_t state;
- uint8_t bus;
- uint8_t dev;
- uint8_t fun;
+ __u32 accel_id;
+ __u32 instance_id;
+ __u8 num_ae;
+ __u8 num_accel;
+ __u8 num_logical_accel;
+ __u8 banks_per_accel;
+ __u8 state;
+ __u8 bus;
+ __u8 dev;
+ __u8 fun;
char name[MAX_DEVICE_NAME_SIZE];
};
@@ -57,6 +57,6 @@ struct adf_dev_status_info {
struct adf_user_cfg_ctl_data)
#define IOCTL_START_ACCEL_DEV _IOW(ADF_CTL_IOC_MAGIC, 2, \
struct adf_user_cfg_ctl_data)
-#define IOCTL_STATUS_ACCEL_DEV _IOW(ADF_CTL_IOC_MAGIC, 3, uint32_t)
-#define IOCTL_GET_NUM_DEVICES _IOW(ADF_CTL_IOC_MAGIC, 4, int32_t)
+#define IOCTL_STATUS_ACCEL_DEV _IOW(ADF_CTL_IOC_MAGIC, 3, __u32)
+#define IOCTL_GET_NUM_DEVICES _IOW(ADF_CTL_IOC_MAGIC, 4, __s32)
#endif
diff --git a/drivers/crypto/qat/qat_common/adf_cfg_user.h b/drivers/crypto/qat/qat_common/adf_cfg_user.h
index 86b4a3e3f355..421f4fb8b4dd 100644
--- a/drivers/crypto/qat/qat_common/adf_cfg_user.h
+++ b/drivers/crypto/qat/qat_common/adf_cfg_user.h
@@ -11,7 +11,7 @@ struct adf_user_cfg_key_val {
char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
union {
struct adf_user_cfg_key_val *next;
- uint64_t padding3;
+ __u64 padding3;
};
enum adf_cfg_val_type type;
} __packed;
@@ -20,19 +20,19 @@ struct adf_user_cfg_section {
char name[ADF_CFG_MAX_SECTION_LEN_IN_BYTES];
union {
struct adf_user_cfg_key_val *params;
- uint64_t padding1;
+ __u64 padding1;
};
union {
struct adf_user_cfg_section *next;
- uint64_t padding3;
+ __u64 padding3;
};
} __packed;
struct adf_user_cfg_ctl_data {
union {
struct adf_user_cfg_section *config_section;
- uint64_t padding;
+ __u64 padding;
};
- uint8_t device_id;
+ __u8 device_id;
} __packed;
#endif
diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw.h b/drivers/crypto/qat/qat_common/icp_qat_fw.h
index 1b9a11f574ee..6dc09d270082 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_fw.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_fw.h
@@ -45,41 +45,41 @@ enum icp_qat_fw_comn_request_id {
struct icp_qat_fw_comn_req_hdr_cd_pars {
union {
struct {
- uint64_t content_desc_addr;
- uint16_t content_desc_resrvd1;
- uint8_t content_desc_params_sz;
- uint8_t content_desc_hdr_resrvd2;
- uint32_t content_desc_resrvd3;
+ __u64 content_desc_addr;
+ __u16 content_desc_resrvd1;
+ __u8 content_desc_params_sz;
+ __u8 content_desc_hdr_resrvd2;
+ __u32 content_desc_resrvd3;
} s;
struct {
- uint32_t serv_specif_fields[4];
+ __u32 serv_specif_fields[4];
} s1;
} u;
};
struct icp_qat_fw_comn_req_mid {
- uint64_t opaque_data;
- uint64_t src_data_addr;
- uint64_t dest_data_addr;
- uint32_t src_length;
- uint32_t dst_length;
+ __u64 opaque_data;
+ __u64 src_data_addr;
+ __u64 dest_data_addr;
+ __u32 src_length;
+ __u32 dst_length;
};
struct icp_qat_fw_comn_req_cd_ctrl {
- uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
+ __u32 content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
};
struct icp_qat_fw_comn_req_hdr {
- uint8_t resrvd1;
- uint8_t service_cmd_id;
- uint8_t service_type;
- uint8_t hdr_flags;
- uint16_t serv_specif_flags;
- uint16_t comn_req_flags;
+ __u8 resrvd1;
+ __u8 service_cmd_id;
+ __u8 service_type;
+ __u8 hdr_flags;
+ __u16 serv_specif_flags;
+ __u16 comn_req_flags;
};
struct icp_qat_fw_comn_req_rqpars {
- uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
+ __u32 serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
};
struct icp_qat_fw_comn_req {
@@ -91,24 +91,24 @@ struct icp_qat_fw_comn_req {
};
struct icp_qat_fw_comn_error {
- uint8_t xlat_err_code;
- uint8_t cmp_err_code;
+ __u8 xlat_err_code;
+ __u8 cmp_err_code;
};
struct icp_qat_fw_comn_resp_hdr {
- uint8_t resrvd1;
- uint8_t service_id;
- uint8_t response_type;
- uint8_t hdr_flags;
+ __u8 resrvd1;
+ __u8 service_id;
+ __u8 response_type;
+ __u8 hdr_flags;
struct icp_qat_fw_comn_error comn_error;
- uint8_t comn_status;
- uint8_t cmd_id;
+ __u8 comn_status;
+ __u8 cmd_id;
};
struct icp_qat_fw_comn_resp {
struct icp_qat_fw_comn_resp_hdr comn_hdr;
- uint64_t opaque_data;
- uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
+ __u64 opaque_data;
+ __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
};
#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h b/drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h
index 2024babd7fc7..c867e9a0a540 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h
@@ -23,35 +23,35 @@ enum icp_qat_fw_init_admin_resp_status {
};
struct icp_qat_fw_init_admin_req {
- uint16_t init_cfg_sz;
- uint8_t resrvd1;
- uint8_t init_admin_cmd_id;
- uint32_t resrvd2;
- uint64_t opaque_data;
- uint64_t init_cfg_ptr;
- uint64_t resrvd3;
+ __u16 init_cfg_sz;
+ __u8 resrvd1;
+ __u8 init_admin_cmd_id;
+ __u32 resrvd2;
+ __u64 opaque_data;
+ __u64 init_cfg_ptr;
+ __u64 resrvd3;
};
struct icp_qat_fw_init_admin_resp_hdr {
- uint8_t flags;
- uint8_t resrvd1;
- uint8_t status;
- uint8_t init_admin_cmd_id;
+ __u8 flags;
+ __u8 resrvd1;
+ __u8 status;
+ __u8 init_admin_cmd_id;
};
struct icp_qat_fw_init_admin_resp_pars {
union {
- uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_4];
+ __u32 resrvd1[ICP_QAT_FW_NUM_LONGWORDS_4];
struct {
- uint32_t version_patch_num;
- uint8_t context_id;
- uint8_t ae_id;
- uint16_t resrvd1;
- uint64_t resrvd2;
+ __u32 version_patch_num;
+ __u8 context_id;
+ __u8 ae_id;
+ __u16 resrvd1;
+ __u64 resrvd2;
} s1;
struct {
- uint64_t req_rec_count;
- uint64_t resp_sent_count;
+ __u64 req_rec_count;
+ __u64 resp_sent_count;
} s2;
} u;
};
@@ -59,13 +59,13 @@ struct icp_qat_fw_init_admin_resp_pars {
struct icp_qat_fw_init_admin_resp {
struct icp_qat_fw_init_admin_resp_hdr init_resp_hdr;
union {
- uint32_t resrvd2;
+ __u32 resrvd2;
struct {
- uint16_t version_minor_num;
- uint16_t version_major_num;
+ __u16 version_minor_num;
+ __u16 version_major_num;
} s;
} u;
- uint64_t opaque_data;
+ __u64 opaque_data;
struct icp_qat_fw_init_admin_resp_pars init_resp_pars;
};
diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw_la.h b/drivers/crypto/qat/qat_common/icp_qat_fw_la.h
index ee0a0c944b31..6757ec09d81f 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_fw_la.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_fw_la.h
@@ -182,14 +182,14 @@ struct icp_qat_fw_la_bulk_req {
struct icp_qat_fw_cipher_req_hdr_cd_pars {
union {
struct {
- uint64_t content_desc_addr;
- uint16_t content_desc_resrvd1;
- uint8_t content_desc_params_sz;
- uint8_t content_desc_hdr_resrvd2;
- uint32_t content_desc_resrvd3;
+ __u64 content_desc_addr;
+ __u16 content_desc_resrvd1;
+ __u8 content_desc_params_sz;
+ __u8 content_desc_hdr_resrvd2;
+ __u32 content_desc_resrvd3;
} s;
struct {
- uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+ __u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
} s1;
} u;
};
@@ -197,70 +197,70 @@ struct icp_qat_fw_cipher_req_hdr_cd_pars {
struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {
union {
struct {
- uint64_t content_desc_addr;
- uint16_t content_desc_resrvd1;
- uint8_t content_desc_params_sz;
- uint8_t content_desc_hdr_resrvd2;
- uint32_t content_desc_resrvd3;
+ __u64 content_desc_addr;
+ __u16 content_desc_resrvd1;
+ __u8 content_desc_params_sz;
+ __u8 content_desc_hdr_resrvd2;
+ __u32 content_desc_resrvd3;
} s;
struct {
- uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+ __u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
} sl;
} u;
};
struct icp_qat_fw_cipher_cd_ctrl_hdr {
- uint8_t cipher_state_sz;
- uint8_t cipher_key_sz;
- uint8_t cipher_cfg_offset;
- uint8_t next_curr_id;
- uint8_t cipher_padding_sz;
- uint8_t resrvd1;
- uint16_t resrvd2;
- uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
+ __u8 cipher_state_sz;
+ __u8 cipher_key_sz;
+ __u8 cipher_cfg_offset;
+ __u8 next_curr_id;
+ __u8 cipher_padding_sz;
+ __u8 resrvd1;
+ __u16 resrvd2;
+ __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
};
struct icp_qat_fw_auth_cd_ctrl_hdr {
- uint32_t resrvd1;
- uint8_t resrvd2;
- uint8_t hash_flags;
- uint8_t hash_cfg_offset;
- uint8_t next_curr_id;
- uint8_t resrvd3;
- uint8_t outer_prefix_sz;
- uint8_t final_sz;
- uint8_t inner_res_sz;
- uint8_t resrvd4;
- uint8_t inner_state1_sz;
- uint8_t inner_state2_offset;
- uint8_t inner_state2_sz;
- uint8_t outer_config_offset;
- uint8_t outer_state1_sz;
- uint8_t outer_res_sz;
- uint8_t outer_prefix_offset;
+ __u32 resrvd1;
+ __u8 resrvd2;
+ __u8 hash_flags;
+ __u8 hash_cfg_offset;
+ __u8 next_curr_id;
+ __u8 resrvd3;
+ __u8 outer_prefix_sz;
+ __u8 final_sz;
+ __u8 inner_res_sz;
+ __u8 resrvd4;
+ __u8 inner_state1_sz;
+ __u8 inner_state2_offset;
+ __u8 inner_state2_sz;
+ __u8 outer_config_offset;
+ __u8 outer_state1_sz;
+ __u8 outer_res_sz;
+ __u8 outer_prefix_offset;
};
struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
- uint8_t cipher_state_sz;
- uint8_t cipher_key_sz;
- uint8_t cipher_cfg_offset;
- uint8_t next_curr_id_cipher;
- uint8_t cipher_padding_sz;
- uint8_t hash_flags;
- uint8_t hash_cfg_offset;
- uint8_t next_curr_id_auth;
- uint8_t resrvd1;
- uint8_t outer_prefix_sz;
- uint8_t final_sz;
- uint8_t inner_res_sz;
- uint8_t resrvd2;
- uint8_t inner_state1_sz;
- uint8_t inner_state2_offset;
- uint8_t inner_state2_sz;
- uint8_t outer_config_offset;
- uint8_t outer_state1_sz;
- uint8_t outer_res_sz;
- uint8_t outer_prefix_offset;
+ __u8 cipher_state_sz;
+ __u8 cipher_key_sz;
+ __u8 cipher_cfg_offset;
+ __u8 next_curr_id_cipher;
+ __u8 cipher_padding_sz;
+ __u8 hash_flags;
+ __u8 hash_cfg_offset;
+ __u8 next_curr_id_auth;
+ __u8 resrvd1;
+ __u8 outer_prefix_sz;
+ __u8 final_sz;
+ __u8 inner_res_sz;
+ __u8 resrvd2;
+ __u8 inner_state1_sz;
+ __u8 inner_state2_offset;
+ __u8 inner_state2_sz;
+ __u8 outer_config_offset;
+ __u8 outer_state1_sz;
+ __u8 outer_res_sz;
+ __u8 outer_prefix_offset;
};
#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
@@ -271,48 +271,48 @@ struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
struct icp_qat_fw_la_cipher_req_params {
- uint32_t cipher_offset;
- uint32_t cipher_length;
+ __u32 cipher_offset;
+ __u32 cipher_length;
union {
- uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+ __u32 cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
struct {
- uint64_t cipher_IV_ptr;
- uint64_t resrvd1;
+ __u64 cipher_IV_ptr;
+ __u64 resrvd1;
} s;
} u;
};
struct icp_qat_fw_la_auth_req_params {
- uint32_t auth_off;
- uint32_t auth_len;
+ __u32 auth_off;
+ __u32 auth_len;
union {
- uint64_t auth_partial_st_prefix;
- uint64_t aad_adr;
+ __u64 auth_partial_st_prefix;
+ __u64 aad_adr;
} u1;
- uint64_t auth_res_addr;
+ __u64 auth_res_addr;
union {
- uint8_t inner_prefix_sz;
- uint8_t aad_sz;
+ __u8 inner_prefix_sz;
+ __u8 aad_sz;
} u2;
- uint8_t resrvd1;
- uint8_t hash_state_sz;
- uint8_t auth_res_sz;
+ __u8 resrvd1;
+ __u8 hash_state_sz;
+ __u8 auth_res_sz;
} __packed;
struct icp_qat_fw_la_auth_req_params_resrvd_flds {
- uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
+ __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
union {
- uint8_t inner_prefix_sz;
- uint8_t aad_sz;
+ __u8 inner_prefix_sz;
+ __u8 aad_sz;
} u2;
- uint8_t resrvd1;
- uint16_t resrvd2;
+ __u8 resrvd1;
+ __u16 resrvd2;
};
struct icp_qat_fw_la_resp {
struct icp_qat_fw_comn_resp_hdr comn_resp;
- uint64_t opaque_data;
- uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
+ __u64 opaque_data;
+ __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
};
#define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
diff --git a/drivers/crypto/qat/qat_common/icp_qat_fw_pke.h b/drivers/crypto/qat/qat_common/icp_qat_fw_pke.h
index 4354a68de327..9dddae0009fc 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_fw_pke.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_fw_pke.h
@@ -6,51 +6,51 @@
#include "icp_qat_fw.h"
struct icp_qat_fw_req_hdr_pke_cd_pars {
- u64 content_desc_addr;
- u32 content_desc_resrvd;
- u32 func_id;
+ __u64 content_desc_addr;
+ __u32 content_desc_resrvd;
+ __u32 func_id;
};
struct icp_qat_fw_req_pke_mid {
- u64 opaque;
- u64 src_data_addr;
- u64 dest_data_addr;
+ __u64 opaque;
+ __u64 src_data_addr;
+ __u64 dest_data_addr;
};
struct icp_qat_fw_req_pke_hdr {
- u8 resrvd1;
- u8 resrvd2;
- u8 service_type;
- u8 hdr_flags;
- u16 comn_req_flags;
- u16 resrvd4;
+ __u8 resrvd1;
+ __u8 resrvd2;
+ __u8 service_type;
+ __u8 hdr_flags;
+ __u16 comn_req_flags;
+ __u16 resrvd4;
struct icp_qat_fw_req_hdr_pke_cd_pars cd_pars;
};
struct icp_qat_fw_pke_request {
struct icp_qat_fw_req_pke_hdr pke_hdr;
struct icp_qat_fw_req_pke_mid pke_mid;
- u8 output_param_count;
- u8 input_param_count;
- u16 resrvd1;
- u32 resrvd2;
- u64 next_req_adr;
+ __u8 output_param_count;
+ __u8 input_param_count;
+ __u16 resrvd1;
+ __u32 resrvd2;
+ __u64 next_req_adr;
};
struct icp_qat_fw_resp_pke_hdr {
- u8 resrvd1;
- u8 resrvd2;
- u8 response_type;
- u8 hdr_flags;
- u16 comn_resp_flags;
- u16 resrvd4;
+ __u8 resrvd1;
+ __u8 resrvd2;
+ __u8 response_type;
+ __u8 hdr_flags;
+ __u16 comn_resp_flags;
+ __u16 resrvd4;
};
struct icp_qat_fw_pke_resp {
struct icp_qat_fw_resp_pke_hdr pke_resp_hdr;
- u64 opaque;
- u64 src_data_addr;
- u64 dest_data_addr;
+ __u64 opaque;
+ __u64 src_data_addr;
+ __u64 dest_data_addr;
};
#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS 7
diff --git a/drivers/crypto/qat/qat_common/icp_qat_hw.h b/drivers/crypto/qat/qat_common/icp_qat_hw.h
index 1f1e7465f3c1..c4b6ef1506ab 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_hw.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_hw.h
@@ -61,8 +61,8 @@ enum icp_qat_hw_auth_mode {
};
struct icp_qat_hw_auth_config {
- uint32_t config;
- uint32_t reserved;
+ __u32 config;
+ __u32 reserved;
};
#define QAT_AUTH_MODE_BITPOS 4
@@ -87,7 +87,7 @@ struct icp_qat_hw_auth_config {
struct icp_qat_hw_auth_counter {
__be32 counter;
- uint32_t reserved;
+ __u32 reserved;
};
#define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
@@ -147,9 +147,9 @@ struct icp_qat_hw_auth_setup {
struct icp_qat_hw_auth_sha512 {
struct icp_qat_hw_auth_setup inner_setup;
- uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
+ __u8 state1[ICP_QAT_HW_SHA512_STATE1_SZ];
struct icp_qat_hw_auth_setup outer_setup;
- uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
+ __u8 state2[ICP_QAT_HW_SHA512_STATE2_SZ];
};
struct icp_qat_hw_auth_algo_blk {
@@ -183,8 +183,8 @@ enum icp_qat_hw_cipher_mode {
};
struct icp_qat_hw_cipher_config {
- uint32_t val;
- uint32_t reserved;
+ __u32 val;
+ __u32 reserved;
};
enum icp_qat_hw_cipher_dir {
@@ -252,7 +252,7 @@ enum icp_qat_hw_cipher_convert {
struct icp_qat_hw_cipher_aes256_f8 {
struct icp_qat_hw_cipher_config cipher_config;
- uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
+ __u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
};
struct icp_qat_hw_cipher_algo_blk {
--
2.26.2
Remove packed attribute in adf_etr_bank_data and adf_etr_ring_data.
Fields in these structures are reordered in order to avoid holes.
Signed-off-by: Giovanni Cabiddu <[email protected]>
---
.../crypto/qat/qat_common/adf_transport_internal.h | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/qat/qat_common/adf_transport_internal.h b/drivers/crypto/qat/qat_common/adf_transport_internal.h
index df4c7195daae..c7faf4e2d302 100644
--- a/drivers/crypto/qat/qat_common/adf_transport_internal.h
+++ b/drivers/crypto/qat/qat_common/adf_transport_internal.h
@@ -15,32 +15,31 @@ struct adf_etr_ring_debug_entry {
struct adf_etr_ring_data {
void *base_addr;
atomic_t *inflights;
- spinlock_t lock; /* protects ring data struct */
adf_callback_fn callback;
struct adf_etr_bank_data *bank;
dma_addr_t dma_addr;
+ struct adf_etr_ring_debug_entry *ring_debug;
+ spinlock_t lock; /* protects ring data struct */
u16 head;
u16 tail;
u8 ring_number;
u8 ring_size;
u8 msg_size;
- u8 reserved;
- struct adf_etr_ring_debug_entry *ring_debug;
-} __packed;
+};
struct adf_etr_bank_data {
struct adf_etr_ring_data rings[ADF_ETR_MAX_RINGS_PER_BANK];
struct tasklet_struct resp_handler;
void __iomem *csr_addr;
- struct adf_accel_dev *accel_dev;
u32 irq_coalesc_timer;
+ u32 bank_number;
u16 ring_mask;
u16 irq_mask;
spinlock_t lock; /* protects bank data struct */
+ struct adf_accel_dev *accel_dev;
struct dentry *bank_debug_dir;
struct dentry *bank_debug_cfg;
- u32 bank_number;
-} __packed;
+};
struct adf_etr_data {
struct adf_etr_bank_data *banks;
--
2.26.2
From: Wojciech Ziemba <[email protected]>
Kernel source code should not include stdint.h types.
This patch replaces uintXX_t types with respective ones defined in kernel
headers.
Signed-off-by: Wojciech Ziemba <[email protected]>
Signed-off-by: Giovanni Cabiddu <[email protected]>
---
.../crypto/qat/qat_common/adf_accel_devices.h | 54 ++++++++--------
.../crypto/qat/qat_common/adf_accel_engine.c | 4 +-
drivers/crypto/qat/qat_common/adf_aer.c | 2 +-
.../crypto/qat/qat_common/adf_common_drv.h | 12 ++--
drivers/crypto/qat/qat_common/adf_ctl_drv.c | 4 +-
drivers/crypto/qat/qat_common/adf_dev_mgr.c | 8 +--
drivers/crypto/qat/qat_common/adf_transport.c | 62 +++++++++----------
drivers/crypto/qat/qat_common/adf_transport.h | 4 +-
.../qat_common/adf_transport_access_macros.h | 6 +-
.../qat/qat_common/adf_transport_internal.h | 20 +++---
drivers/crypto/qat/qat_common/icp_qat_uclo.h | 6 +-
drivers/crypto/qat/qat_common/qat_algs.c | 54 ++++++++--------
drivers/crypto/qat/qat_common/qat_asym_algs.c | 12 ++--
drivers/crypto/qat/qat_common/qat_hal.c | 40 ++++++------
drivers/crypto/qat/qat_common/qat_uclo.c | 20 +++---
.../qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 26 ++++----
16 files changed, 167 insertions(+), 167 deletions(-)
diff --git a/drivers/crypto/qat/qat_common/adf_accel_devices.h b/drivers/crypto/qat/qat_common/adf_accel_devices.h
index b3500bc4a558..c1db8c26afb6 100644
--- a/drivers/crypto/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/qat/qat_common/adf_accel_devices.h
@@ -59,8 +59,8 @@ struct adf_accel_pci {
struct pci_dev *pci_dev;
struct adf_accel_msix msix_entries;
struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
- uint8_t revid;
- uint8_t sku;
+ u8 revid;
+ u8 sku;
} __packed;
enum dev_state {
@@ -100,7 +100,7 @@ static inline const char *get_sku_info(enum dev_sku_info info)
struct adf_hw_device_class {
const char *name;
const enum adf_device_type type;
- uint32_t instances;
+ u32 instances;
} __packed;
struct adf_cfg_device_data;
@@ -110,15 +110,15 @@ struct adf_etr_ring_data;
struct adf_hw_device_data {
struct adf_hw_device_class *dev_class;
- uint32_t (*get_accel_mask)(uint32_t fuse);
- uint32_t (*get_ae_mask)(uint32_t fuse);
- uint32_t (*get_sram_bar_id)(struct adf_hw_device_data *self);
- uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self);
- uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self);
- uint32_t (*get_num_aes)(struct adf_hw_device_data *self);
- uint32_t (*get_num_accels)(struct adf_hw_device_data *self);
- uint32_t (*get_pf2vf_offset)(uint32_t i);
- uint32_t (*get_vintmsk_offset)(uint32_t i);
+ u32 (*get_accel_mask)(u32 fuse);
+ u32 (*get_ae_mask)(u32 fuse);
+ u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
+ u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
+ u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
+ u32 (*get_num_aes)(struct adf_hw_device_data *self);
+ u32 (*get_num_accels)(struct adf_hw_device_data *self);
+ u32 (*get_pf2vf_offset)(u32 i);
+ u32 (*get_vintmsk_offset)(u32 i);
enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
int (*alloc_irq)(struct adf_accel_dev *accel_dev);
void (*free_irq)(struct adf_accel_dev *accel_dev);
@@ -129,25 +129,25 @@ struct adf_hw_device_data {
int (*init_arb)(struct adf_accel_dev *accel_dev);
void (*exit_arb)(struct adf_accel_dev *accel_dev);
void (*get_arb_mapping)(struct adf_accel_dev *accel_dev,
- const uint32_t **cfg);
+ const u32 **cfg);
void (*disable_iov)(struct adf_accel_dev *accel_dev);
void (*enable_ints)(struct adf_accel_dev *accel_dev);
int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev);
void (*reset_device)(struct adf_accel_dev *accel_dev);
const char *fw_name;
const char *fw_mmp_name;
- uint32_t fuses;
- uint32_t accel_capabilities_mask;
- uint32_t instance_id;
- uint16_t accel_mask;
- uint16_t ae_mask;
- uint16_t tx_rings_mask;
- uint8_t tx_rx_gap;
- uint8_t num_banks;
- uint8_t num_accel;
- uint8_t num_logical_accel;
- uint8_t num_engines;
- uint8_t min_iov_compat_ver;
+ u32 fuses;
+ u32 accel_capabilities_mask;
+ u32 instance_id;
+ u16 accel_mask;
+ u16 ae_mask;
+ u16 tx_rings_mask;
+ u8 tx_rx_gap;
+ u8 num_banks;
+ u8 num_accel;
+ u8 num_logical_accel;
+ u8 num_engines;
+ u8 min_iov_compat_ver;
} __packed;
/* CSR write macro */
@@ -204,8 +204,8 @@ struct adf_accel_dev {
struct tasklet_struct pf2vf_bh_tasklet;
struct mutex vf2pf_lock; /* protect CSR access */
struct completion iov_msg_completion;
- uint8_t compatible;
- uint8_t pf_version;
+ u8 compatible;
+ u8 pf_version;
} vf;
};
bool is_vf;
diff --git a/drivers/crypto/qat/qat_common/adf_accel_engine.c b/drivers/crypto/qat/qat_common/adf_accel_engine.c
index 00d4d13e33e8..c8ad85b882be 100644
--- a/drivers/crypto/qat/qat_common/adf_accel_engine.c
+++ b/drivers/crypto/qat/qat_common/adf_accel_engine.c
@@ -74,7 +74,7 @@ int adf_ae_start(struct adf_accel_dev *accel_dev)
{
struct adf_fw_loader_data *loader_data = accel_dev->fw_loader;
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
- uint32_t ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev);
+ u32 ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev);
if (!hw_data->fw_name)
return 0;
@@ -95,7 +95,7 @@ int adf_ae_stop(struct adf_accel_dev *accel_dev)
{
struct adf_fw_loader_data *loader_data = accel_dev->fw_loader;
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
- uint32_t ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev);
+ u32 ae_ctr, ae, max_aes = GET_MAX_ACCELENGINES(accel_dev);
if (!hw_data->fw_name)
return 0;
diff --git a/drivers/crypto/qat/qat_common/adf_aer.c b/drivers/crypto/qat/qat_common/adf_aer.c
index 35cdc0fbbe40..32102e27e559 100644
--- a/drivers/crypto/qat/qat_common/adf_aer.c
+++ b/drivers/crypto/qat/qat_common/adf_aer.c
@@ -42,7 +42,7 @@ void adf_reset_sbr(struct adf_accel_dev *accel_dev)
{
struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
struct pci_dev *parent = pdev->bus->self;
- uint16_t bridge_ctl = 0;
+ u16 bridge_ctl = 0;
if (!parent)
parent = pdev;
diff --git a/drivers/crypto/qat/qat_common/adf_common_drv.h b/drivers/crypto/qat/qat_common/adf_common_drv.h
index ae91203bb617..ebfcb4ea618d 100644
--- a/drivers/crypto/qat/qat_common/adf_common_drv.h
+++ b/drivers/crypto/qat/qat_common/adf_common_drv.h
@@ -79,11 +79,11 @@ int adf_devmgr_add_dev(struct adf_accel_dev *accel_dev,
void adf_devmgr_rm_dev(struct adf_accel_dev *accel_dev,
struct adf_accel_dev *pf);
struct list_head *adf_devmgr_get_head(void);
-struct adf_accel_dev *adf_devmgr_get_dev_by_id(uint32_t id);
+struct adf_accel_dev *adf_devmgr_get_dev_by_id(u32 id);
struct adf_accel_dev *adf_devmgr_get_first(void);
struct adf_accel_dev *adf_devmgr_pci_to_accel_dev(struct pci_dev *pci_dev);
-int adf_devmgr_verify_id(uint32_t id);
-void adf_devmgr_get_num_dev(uint32_t *num);
+int adf_devmgr_verify_id(u32 id);
+void adf_devmgr_get_num_dev(u32 *num);
int adf_devmgr_in_reset(struct adf_accel_dev *accel_dev);
int adf_dev_started(struct adf_accel_dev *accel_dev);
int adf_dev_restarting_notify(struct adf_accel_dev *accel_dev);
@@ -154,7 +154,7 @@ void qat_hal_set_pc(struct icp_qat_fw_loader_handle *handle,
unsigned char ae, unsigned int ctx_mask, unsigned int upc);
void qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle,
unsigned char ae, unsigned int uaddr,
- unsigned int words_num, uint64_t *uword);
+ unsigned int words_num, u64 *uword);
void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
unsigned int uword_addr, unsigned int words_num,
unsigned int *data);
@@ -189,9 +189,9 @@ int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
int adf_sriov_configure(struct pci_dev *pdev, int numvfs);
void adf_disable_sriov(struct adf_accel_dev *accel_dev);
void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
- uint32_t vf_mask);
+ u32 vf_mask);
void adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
- uint32_t vf_mask);
+ u32 vf_mask);
void adf_enable_pf2vf_interrupts(struct adf_accel_dev *accel_dev);
void adf_disable_pf2vf_interrupts(struct adf_accel_dev *accel_dev);
diff --git a/drivers/crypto/qat/qat_common/adf_ctl_drv.c b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
index 4d4589d4b64c..71d0c44aacca 100644
--- a/drivers/crypto/qat/qat_common/adf_ctl_drv.c
+++ b/drivers/crypto/qat/qat_common/adf_ctl_drv.c
@@ -226,7 +226,7 @@ static int adf_ctl_is_device_in_use(int id)
return 0;
}
-static void adf_ctl_stop_devices(uint32_t id)
+static void adf_ctl_stop_devices(u32 id)
{
struct adf_accel_dev *accel_dev;
@@ -330,7 +330,7 @@ static int adf_ctl_ioctl_dev_start(struct file *fp, unsigned int cmd,
static int adf_ctl_ioctl_get_num_devices(struct file *fp, unsigned int cmd,
unsigned long arg)
{
- uint32_t num_devices = 0;
+ u32 num_devices = 0;
adf_devmgr_get_num_dev(&num_devices);
if (copy_to_user((void __user *)arg, &num_devices, sizeof(num_devices)))
diff --git a/drivers/crypto/qat/qat_common/adf_dev_mgr.c b/drivers/crypto/qat/qat_common/adf_dev_mgr.c
index e663054a11d5..72753af056b3 100644
--- a/drivers/crypto/qat/qat_common/adf_dev_mgr.c
+++ b/drivers/crypto/qat/qat_common/adf_dev_mgr.c
@@ -8,7 +8,7 @@
static LIST_HEAD(accel_table);
static LIST_HEAD(vfs_table);
static DEFINE_MUTEX(table_lock);
-static uint32_t num_devices;
+static u32 num_devices;
static u8 id_map[ADF_MAX_DEVICES];
struct vf_id_map {
@@ -311,7 +311,7 @@ struct adf_accel_dev *adf_devmgr_pci_to_accel_dev(struct pci_dev *pci_dev)
}
EXPORT_SYMBOL_GPL(adf_devmgr_pci_to_accel_dev);
-struct adf_accel_dev *adf_devmgr_get_dev_by_id(uint32_t id)
+struct adf_accel_dev *adf_devmgr_get_dev_by_id(u32 id)
{
struct list_head *itr;
int real_id;
@@ -336,7 +336,7 @@ struct adf_accel_dev *adf_devmgr_get_dev_by_id(uint32_t id)
return NULL;
}
-int adf_devmgr_verify_id(uint32_t id)
+int adf_devmgr_verify_id(u32 id)
{
if (id == ADF_CFG_ALL_DEVICES)
return 0;
@@ -363,7 +363,7 @@ static int adf_get_num_dettached_vfs(void)
return vfs;
}
-void adf_devmgr_get_num_dev(uint32_t *num)
+void adf_devmgr_get_num_dev(u32 *num)
{
*num = num_devices - adf_get_num_dettached_vfs();
}
diff --git a/drivers/crypto/qat/qat_common/adf_transport.c b/drivers/crypto/qat/qat_common/adf_transport.c
index 4625881a8832..2ad774017200 100644
--- a/drivers/crypto/qat/qat_common/adf_transport.c
+++ b/drivers/crypto/qat/qat_common/adf_transport.c
@@ -7,22 +7,22 @@
#include "adf_cfg.h"
#include "adf_common_drv.h"
-static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
+static inline u32 adf_modulo(u32 data, u32 shift)
{
- uint32_t div = data >> shift;
- uint32_t mult = div << shift;
+ u32 div = data >> shift;
+ u32 mult = div << shift;
return data - mult;
}
-static inline int adf_check_ring_alignment(uint64_t addr, uint64_t size)
+static inline int adf_check_ring_alignment(u64 addr, u64 size)
{
if (((size - 1) & addr) != 0)
return -EFAULT;
return 0;
}
-static int adf_verify_ring_size(uint32_t msg_size, uint32_t msg_num)
+static int adf_verify_ring_size(u32 msg_size, u32 msg_num)
{
int i = ADF_MIN_RING_SIZE;
@@ -33,7 +33,7 @@ static int adf_verify_ring_size(uint32_t msg_size, uint32_t msg_num)
return ADF_DEFAULT_RING_SIZE;
}
-static int adf_reserve_ring(struct adf_etr_bank_data *bank, uint32_t ring)
+static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring)
{
spin_lock(&bank->lock);
if (bank->ring_mask & (1 << ring)) {
@@ -45,14 +45,14 @@ static int adf_reserve_ring(struct adf_etr_bank_data *bank, uint32_t ring)
return 0;
}
-static void adf_unreserve_ring(struct adf_etr_bank_data *bank, uint32_t ring)
+static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring)
{
spin_lock(&bank->lock);
bank->ring_mask &= ~(1 << ring);
spin_unlock(&bank->lock);
}
-static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring)
+static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, u32 ring)
{
spin_lock_bh(&bank->lock);
bank->irq_mask |= (1 << ring);
@@ -62,7 +62,7 @@ static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring)
bank->irq_coalesc_timer);
}
-static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring)
+static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, u32 ring)
{
spin_lock_bh(&bank->lock);
bank->irq_mask &= ~(1 << ring);
@@ -70,7 +70,7 @@ static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring)
WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask);
}
-int adf_send_message(struct adf_etr_ring_data *ring, uint32_t *msg)
+int adf_send_message(struct adf_etr_ring_data *ring, u32 *msg)
{
if (atomic_add_return(1, ring->inflights) >
ADF_MAX_INFLIGHTS(ring->ring_size, ring->msg_size)) {
@@ -92,18 +92,18 @@ int adf_send_message(struct adf_etr_ring_data *ring, uint32_t *msg)
static int adf_handle_response(struct adf_etr_ring_data *ring)
{
- uint32_t msg_counter = 0;
- uint32_t *msg = (uint32_t *)((uintptr_t)ring->base_addr + ring->head);
+ u32 msg_counter = 0;
+ u32 *msg = (u32 *)((uintptr_t)ring->base_addr + ring->head);
while (*msg != ADF_RING_EMPTY_SIG) {
- ring->callback((uint32_t *)msg);
+ ring->callback((u32 *)msg);
atomic_dec(ring->inflights);
*msg = ADF_RING_EMPTY_SIG;
ring->head = adf_modulo(ring->head +
ADF_MSG_SIZE_TO_BYTES(ring->msg_size),
ADF_RING_SIZE_MODULO(ring->ring_size));
msg_counter++;
- msg = (uint32_t *)((uintptr_t)ring->base_addr + ring->head);
+ msg = (u32 *)((uintptr_t)ring->base_addr + ring->head);
}
if (msg_counter > 0)
WRITE_CSR_RING_HEAD(ring->bank->csr_addr,
@@ -114,7 +114,7 @@ static int adf_handle_response(struct adf_etr_ring_data *ring)
static void adf_configure_tx_ring(struct adf_etr_ring_data *ring)
{
- uint32_t ring_config = BUILD_RING_CONFIG(ring->ring_size);
+ u32 ring_config = BUILD_RING_CONFIG(ring->ring_size);
WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number,
ring->ring_number, ring_config);
@@ -122,7 +122,7 @@ static void adf_configure_tx_ring(struct adf_etr_ring_data *ring)
static void adf_configure_rx_ring(struct adf_etr_ring_data *ring)
{
- uint32_t ring_config =
+ u32 ring_config =
BUILD_RESP_RING_CONFIG(ring->ring_size,
ADF_RING_NEAR_WATERMARK_512,
ADF_RING_NEAR_WATERMARK_0);
@@ -136,8 +136,8 @@ static int adf_init_ring(struct adf_etr_ring_data *ring)
struct adf_etr_bank_data *bank = ring->bank;
struct adf_accel_dev *accel_dev = bank->accel_dev;
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
- uint64_t ring_base;
- uint32_t ring_size_bytes =
+ u64 ring_base;
+ u32 ring_size_bytes =
ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size);
ring_size_bytes = ADF_RING_SIZE_BYTES_MIN(ring_size_bytes);
@@ -171,7 +171,7 @@ static int adf_init_ring(struct adf_etr_ring_data *ring)
static void adf_cleanup_ring(struct adf_etr_ring_data *ring)
{
- uint32_t ring_size_bytes =
+ u32 ring_size_bytes =
ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size);
ring_size_bytes = ADF_RING_SIZE_BYTES_MIN(ring_size_bytes);
@@ -184,8 +184,8 @@ static void adf_cleanup_ring(struct adf_etr_ring_data *ring)
}
int adf_create_ring(struct adf_accel_dev *accel_dev, const char *section,
- uint32_t bank_num, uint32_t num_msgs,
- uint32_t msg_size, const char *ring_name,
+ u32 bank_num, u32 num_msgs,
+ u32 msg_size, const char *ring_name,
adf_callback_fn callback, int poll_mode,
struct adf_etr_ring_data **ring_ptr)
{
@@ -193,7 +193,7 @@ int adf_create_ring(struct adf_accel_dev *accel_dev, const char *section,
struct adf_etr_bank_data *bank;
struct adf_etr_ring_data *ring;
char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
- uint32_t ring_num;
+ u32 ring_num;
int ret;
if (bank_num >= GET_MAX_BANKS(accel_dev)) {
@@ -286,7 +286,7 @@ void adf_remove_ring(struct adf_etr_ring_data *ring)
static void adf_ring_response_handler(struct adf_etr_bank_data *bank)
{
- uint32_t empty_rings, i;
+ u32 empty_rings, i;
empty_rings = READ_CSR_E_STAT(bank->csr_addr, bank->bank_number);
empty_rings = ~empty_rings & bank->irq_mask;
@@ -309,7 +309,7 @@ void adf_response_handler(uintptr_t bank_addr)
static inline int adf_get_cfg_int(struct adf_accel_dev *accel_dev,
const char *section, const char *format,
- uint32_t key, uint32_t *value)
+ u32 key, u32 *value)
{
char key_buf[ADF_CFG_MAX_KEY_LEN_IN_BYTES];
char val_buf[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
@@ -326,7 +326,7 @@ static inline int adf_get_cfg_int(struct adf_accel_dev *accel_dev,
static void adf_get_coalesc_timer(struct adf_etr_bank_data *bank,
const char *section,
- uint32_t bank_num_in_accel)
+ u32 bank_num_in_accel)
{
if (adf_get_cfg_int(bank->accel_dev, section,
ADF_ETRMGR_COALESCE_TIMER_FORMAT,
@@ -340,12 +340,12 @@ static void adf_get_coalesc_timer(struct adf_etr_bank_data *bank,
static int adf_init_bank(struct adf_accel_dev *accel_dev,
struct adf_etr_bank_data *bank,
- uint32_t bank_num, void __iomem *csr_addr)
+ u32 bank_num, void __iomem *csr_addr)
{
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
struct adf_etr_ring_data *ring;
struct adf_etr_ring_data *tx_ring;
- uint32_t i, coalesc_enabled = 0;
+ u32 i, coalesc_enabled = 0;
memset(bank, 0, sizeof(*bank));
bank->bank_number = bank_num;
@@ -417,8 +417,8 @@ int adf_init_etr_data(struct adf_accel_dev *accel_dev)
struct adf_etr_data *etr_data;
struct adf_hw_device_data *hw_data = accel_dev->hw_device;
void __iomem *csr_addr;
- uint32_t size;
- uint32_t num_banks = 0;
+ u32 size;
+ u32 num_banks = 0;
int i, ret;
etr_data = kzalloc_node(sizeof(*etr_data), GFP_KERNEL,
@@ -464,7 +464,7 @@ EXPORT_SYMBOL_GPL(adf_init_etr_data);
static void cleanup_bank(struct adf_etr_bank_data *bank)
{
- uint32_t i;
+ u32 i;
for (i = 0; i < ADF_ETR_MAX_RINGS_PER_BANK; i++) {
struct adf_accel_dev *accel_dev = bank->accel_dev;
@@ -484,7 +484,7 @@ static void cleanup_bank(struct adf_etr_bank_data *bank)
static void adf_cleanup_etr_handles(struct adf_accel_dev *accel_dev)
{
struct adf_etr_data *etr_data = accel_dev->transport;
- uint32_t i, num_banks = GET_MAX_BANKS(accel_dev);
+ u32 i, num_banks = GET_MAX_BANKS(accel_dev);
for (i = 0; i < num_banks; i++)
cleanup_bank(&etr_data->banks[i]);
diff --git a/drivers/crypto/qat/qat_common/adf_transport.h b/drivers/crypto/qat/qat_common/adf_transport.h
index 0faea1032b93..2c95f1697c76 100644
--- a/drivers/crypto/qat/qat_common/adf_transport.h
+++ b/drivers/crypto/qat/qat_common/adf_transport.h
@@ -10,10 +10,10 @@ struct adf_etr_ring_data;
typedef void (*adf_callback_fn)(void *resp_msg);
int adf_create_ring(struct adf_accel_dev *accel_dev, const char *section,
- uint32_t bank_num, uint32_t num_mgs, uint32_t msg_size,
+ u32 bank_num, u32 num_mgs, u32 msg_size,
const char *ring_name, adf_callback_fn callback,
int poll_mode, struct adf_etr_ring_data **ring_ptr);
-int adf_send_message(struct adf_etr_ring_data *ring, uint32_t *msg);
+int adf_send_message(struct adf_etr_ring_data *ring, u32 *msg);
void adf_remove_ring(struct adf_etr_ring_data *ring);
#endif
diff --git a/drivers/crypto/qat/qat_common/adf_transport_access_macros.h b/drivers/crypto/qat/qat_common/adf_transport_access_macros.h
index 1a943f948100..950d1988556c 100644
--- a/drivers/crypto/qat/qat_common/adf_transport_access_macros.h
+++ b/drivers/crypto/qat/qat_common/adf_transport_access_macros.h
@@ -88,9 +88,9 @@
ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
do { \
- uint32_t l_base = 0, u_base = 0; \
- l_base = (uint32_t)(value & 0xFFFFFFFF); \
- u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
+ u32 l_base = 0, u_base = 0; \
+ l_base = (u32)(value & 0xFFFFFFFF); \
+ u_base = (u32)((value & 0xFFFFFFFF00000000ULL) >> 32); \
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
diff --git a/drivers/crypto/qat/qat_common/adf_transport_internal.h b/drivers/crypto/qat/qat_common/adf_transport_internal.h
index fc610ea31869..df4c7195daae 100644
--- a/drivers/crypto/qat/qat_common/adf_transport_internal.h
+++ b/drivers/crypto/qat/qat_common/adf_transport_internal.h
@@ -19,12 +19,12 @@ struct adf_etr_ring_data {
adf_callback_fn callback;
struct adf_etr_bank_data *bank;
dma_addr_t dma_addr;
- uint16_t head;
- uint16_t tail;
- uint8_t ring_number;
- uint8_t ring_size;
- uint8_t msg_size;
- uint8_t reserved;
+ u16 head;
+ u16 tail;
+ u8 ring_number;
+ u8 ring_size;
+ u8 msg_size;
+ u8 reserved;
struct adf_etr_ring_debug_entry *ring_debug;
} __packed;
@@ -33,13 +33,13 @@ struct adf_etr_bank_data {
struct tasklet_struct resp_handler;
void __iomem *csr_addr;
struct adf_accel_dev *accel_dev;
- uint32_t irq_coalesc_timer;
- uint16_t ring_mask;
- uint16_t irq_mask;
+ u32 irq_coalesc_timer;
+ u16 ring_mask;
+ u16 irq_mask;
spinlock_t lock; /* protects bank data struct */
struct dentry *bank_debug_dir;
struct dentry *bank_debug_cfg;
- uint32_t bank_number;
+ u32 bank_number;
} __packed;
struct adf_etr_data {
diff --git a/drivers/crypto/qat/qat_common/icp_qat_uclo.h b/drivers/crypto/qat/qat_common/icp_qat_uclo.h
index dbb58eacc395..8fe1ec344fa2 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_uclo.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_uclo.h
@@ -132,7 +132,7 @@ struct icp_qat_uof_encap_obj {
struct icp_qat_uclo_encap_uwblock {
unsigned int start_addr;
unsigned int words_num;
- uint64_t micro_words;
+ u64 micro_words;
};
struct icp_qat_uclo_encap_page {
@@ -171,7 +171,7 @@ struct icp_qat_uclo_objhdr {
struct icp_qat_uof_strtable {
unsigned int table_len;
unsigned int reserved;
- uint64_t strings;
+ u64 strings;
};
struct icp_qat_uclo_objhandle {
@@ -191,7 +191,7 @@ struct icp_qat_uclo_objhandle {
unsigned int ae_num;
unsigned int ustore_phy_size;
void *obj_buf;
- uint64_t *uword_buf;
+ u64 *uword_buf;
};
struct icp_qat_uof_uword_block {
diff --git a/drivers/crypto/qat/qat_common/qat_algs.c b/drivers/crypto/qat/qat_common/qat_algs.c
index 00e10a4d578a..4f2c402a5de1 100644
--- a/drivers/crypto/qat/qat_common/qat_algs.c
+++ b/drivers/crypto/qat/qat_common/qat_algs.c
@@ -34,15 +34,15 @@ static DEFINE_MUTEX(algs_lock);
static unsigned int active_devs;
struct qat_alg_buf {
- uint32_t len;
- uint32_t resrvd;
- uint64_t addr;
+ u32 len;
+ u32 resrvd;
+ u64 addr;
} __packed;
struct qat_alg_buf_list {
- uint64_t resrvd;
- uint32_t num_bufs;
- uint32_t num_mapped_bufs;
+ u64 resrvd;
+ u32 num_bufs;
+ u32 num_mapped_bufs;
struct qat_alg_buf bufers[];
} __packed __aligned(64);
@@ -107,7 +107,7 @@ static int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg)
static int qat_alg_do_precomputes(struct icp_qat_hw_auth_algo_blk *hash,
struct qat_alg_aead_ctx *ctx,
- const uint8_t *auth_key,
+ const u8 *auth_key,
unsigned int auth_keylen)
{
SHASH_DESC_ON_STACK(shash, ctx->hash_tfm);
@@ -423,7 +423,7 @@ static int qat_alg_aead_init_dec_session(struct crypto_aead *aead_tfm,
static void qat_alg_skcipher_init_com(struct qat_alg_skcipher_ctx *ctx,
struct icp_qat_fw_la_bulk_req *req,
struct icp_qat_hw_cipher_algo_blk *cd,
- const uint8_t *key, unsigned int keylen)
+ const u8 *key, unsigned int keylen)
{
struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req->cd_pars;
struct icp_qat_fw_comn_req_hdr *header = &req->comn_hdr;
@@ -443,7 +443,7 @@ static void qat_alg_skcipher_init_com(struct qat_alg_skcipher_ctx *ctx,
}
static void qat_alg_skcipher_init_enc(struct qat_alg_skcipher_ctx *ctx,
- int alg, const uint8_t *key,
+ int alg, const u8 *key,
unsigned int keylen, int mode)
{
struct icp_qat_hw_cipher_algo_blk *enc_cd = ctx->enc_cd;
@@ -456,7 +456,7 @@ static void qat_alg_skcipher_init_enc(struct qat_alg_skcipher_ctx *ctx,
}
static void qat_alg_skcipher_init_dec(struct qat_alg_skcipher_ctx *ctx,
- int alg, const uint8_t *key,
+ int alg, const u8 *key,
unsigned int keylen, int mode)
{
struct icp_qat_hw_cipher_algo_blk *dec_cd = ctx->dec_cd;
@@ -534,7 +534,7 @@ static int qat_alg_aead_init_sessions(struct crypto_aead *tfm, const u8 *key,
}
static int qat_alg_skcipher_init_sessions(struct qat_alg_skcipher_ctx *ctx,
- const uint8_t *key,
+ const u8 *key,
unsigned int keylen,
int mode)
{
@@ -548,7 +548,7 @@ static int qat_alg_skcipher_init_sessions(struct qat_alg_skcipher_ctx *ctx,
return 0;
}
-static int qat_alg_aead_rekey(struct crypto_aead *tfm, const uint8_t *key,
+static int qat_alg_aead_rekey(struct crypto_aead *tfm, const u8 *key,
unsigned int keylen)
{
struct qat_alg_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -562,7 +562,7 @@ static int qat_alg_aead_rekey(struct crypto_aead *tfm, const uint8_t *key,
ICP_QAT_HW_CIPHER_CBC_MODE);
}
-static int qat_alg_aead_newkey(struct crypto_aead *tfm, const uint8_t *key,
+static int qat_alg_aead_newkey(struct crypto_aead *tfm, const u8 *key,
unsigned int keylen)
{
struct qat_alg_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -614,7 +614,7 @@ static int qat_alg_aead_newkey(struct crypto_aead *tfm, const uint8_t *key,
return ret;
}
-static int qat_alg_aead_setkey(struct crypto_aead *tfm, const uint8_t *key,
+static int qat_alg_aead_setkey(struct crypto_aead *tfm, const u8 *key,
unsigned int keylen)
{
struct qat_alg_aead_ctx *ctx = crypto_aead_ctx(tfm);
@@ -776,7 +776,7 @@ static void qat_aead_alg_callback(struct icp_qat_fw_la_resp *qat_resp,
struct qat_alg_aead_ctx *ctx = qat_req->aead_ctx;
struct qat_crypto_instance *inst = ctx->inst;
struct aead_request *areq = qat_req->aead_req;
- uint8_t stat_filed = qat_resp->comn_resp.comn_status;
+ u8 stat_filed = qat_resp->comn_resp.comn_status;
int res = 0, qat_res = ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(stat_filed);
qat_alg_free_bufl(inst, qat_req);
@@ -791,7 +791,7 @@ static void qat_skcipher_alg_callback(struct icp_qat_fw_la_resp *qat_resp,
struct qat_alg_skcipher_ctx *ctx = qat_req->skcipher_ctx;
struct qat_crypto_instance *inst = ctx->inst;
struct skcipher_request *sreq = qat_req->skcipher_req;
- uint8_t stat_filed = qat_resp->comn_resp.comn_status;
+ u8 stat_filed = qat_resp->comn_resp.comn_status;
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
int res = 0, qat_res = ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(stat_filed);
@@ -843,18 +843,18 @@ static int qat_alg_aead_dec(struct aead_request *areq)
qat_req->aead_ctx = ctx;
qat_req->aead_req = areq;
qat_req->cb = qat_aead_alg_callback;
- qat_req->req.comn_mid.opaque_data = (uint64_t)(__force long)qat_req;
+ qat_req->req.comn_mid.opaque_data = (u64)(__force long)qat_req;
qat_req->req.comn_mid.src_data_addr = qat_req->buf.blp;
qat_req->req.comn_mid.dest_data_addr = qat_req->buf.bloutp;
cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
cipher_param->cipher_length = cipher_length;
cipher_param->cipher_offset = areq->assoclen;
memcpy(cipher_param->u.cipher_IV_array, areq->iv, AES_BLOCK_SIZE);
- auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
+ auth_param = (void *)((u8 *)cipher_param + sizeof(*cipher_param));
auth_param->auth_off = 0;
auth_param->auth_len = areq->assoclen + cipher_param->cipher_length;
do {
- ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg);
+ ret = adf_send_message(ctx->inst->sym_tx, (u32 *)msg);
} while (ret == -EAGAIN && ctr++ < 10);
if (ret == -EAGAIN) {
@@ -873,7 +873,7 @@ static int qat_alg_aead_enc(struct aead_request *areq)
struct icp_qat_fw_la_cipher_req_params *cipher_param;
struct icp_qat_fw_la_auth_req_params *auth_param;
struct icp_qat_fw_la_bulk_req *msg;
- uint8_t *iv = areq->iv;
+ u8 *iv = areq->iv;
int ret, ctr = 0;
if (!areq->cryptlen)
@@ -891,11 +891,11 @@ static int qat_alg_aead_enc(struct aead_request *areq)
qat_req->aead_ctx = ctx;
qat_req->aead_req = areq;
qat_req->cb = qat_aead_alg_callback;
- qat_req->req.comn_mid.opaque_data = (uint64_t)(__force long)qat_req;
+ qat_req->req.comn_mid.opaque_data = (u64)(__force long)qat_req;
qat_req->req.comn_mid.src_data_addr = qat_req->buf.blp;
qat_req->req.comn_mid.dest_data_addr = qat_req->buf.bloutp;
cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
- auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
+ auth_param = (void *)((u8 *)cipher_param + sizeof(*cipher_param));
memcpy(cipher_param->u.cipher_IV_array, iv, AES_BLOCK_SIZE);
cipher_param->cipher_length = areq->cryptlen;
@@ -905,7 +905,7 @@ static int qat_alg_aead_enc(struct aead_request *areq)
auth_param->auth_len = areq->assoclen + areq->cryptlen;
do {
- ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg);
+ ret = adf_send_message(ctx->inst->sym_tx, (u32 *)msg);
} while (ret == -EAGAIN && ctr++ < 10);
if (ret == -EAGAIN) {
@@ -1042,7 +1042,7 @@ static int qat_alg_skcipher_encrypt(struct skcipher_request *req)
qat_req->skcipher_ctx = ctx;
qat_req->skcipher_req = req;
qat_req->cb = qat_skcipher_alg_callback;
- qat_req->req.comn_mid.opaque_data = (uint64_t)(__force long)qat_req;
+ qat_req->req.comn_mid.opaque_data = (u64)(__force long)qat_req;
qat_req->req.comn_mid.src_data_addr = qat_req->buf.blp;
qat_req->req.comn_mid.dest_data_addr = qat_req->buf.bloutp;
cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
@@ -1051,7 +1051,7 @@ static int qat_alg_skcipher_encrypt(struct skcipher_request *req)
cipher_param->u.s.cipher_IV_ptr = qat_req->iv_paddr;
memcpy(qat_req->iv, req->iv, AES_BLOCK_SIZE);
do {
- ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg);
+ ret = adf_send_message(ctx->inst->sym_tx, (u32 *)msg);
} while (ret == -EAGAIN && ctr++ < 10);
if (ret == -EAGAIN) {
@@ -1102,7 +1102,7 @@ static int qat_alg_skcipher_decrypt(struct skcipher_request *req)
qat_req->skcipher_ctx = ctx;
qat_req->skcipher_req = req;
qat_req->cb = qat_skcipher_alg_callback;
- qat_req->req.comn_mid.opaque_data = (uint64_t)(__force long)qat_req;
+ qat_req->req.comn_mid.opaque_data = (u64)(__force long)qat_req;
qat_req->req.comn_mid.src_data_addr = qat_req->buf.blp;
qat_req->req.comn_mid.dest_data_addr = qat_req->buf.bloutp;
cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
@@ -1111,7 +1111,7 @@ static int qat_alg_skcipher_decrypt(struct skcipher_request *req)
cipher_param->u.s.cipher_IV_ptr = qat_req->iv_paddr;
memcpy(qat_req->iv, req->iv, AES_BLOCK_SIZE);
do {
- ret = adf_send_message(ctx->inst->sym_tx, (uint32_t *)msg);
+ ret = adf_send_message(ctx->inst->sym_tx, (u32 *)msg);
} while (ret == -EAGAIN && ctr++ < 10);
if (ret == -EAGAIN) {
diff --git a/drivers/crypto/qat/qat_common/qat_asym_algs.c b/drivers/crypto/qat/qat_common/qat_asym_algs.c
index 6cd67b06979b..846569ec9066 100644
--- a/drivers/crypto/qat/qat_common/qat_asym_algs.c
+++ b/drivers/crypto/qat/qat_common/qat_asym_algs.c
@@ -339,12 +339,12 @@ static int qat_dh_compute_value(struct kpp_request *req)
msg->pke_mid.src_data_addr = qat_req->phy_in;
msg->pke_mid.dest_data_addr = qat_req->phy_out;
- msg->pke_mid.opaque = (uint64_t)(__force long)qat_req;
+ msg->pke_mid.opaque = (u64)(__force long)qat_req;
msg->input_param_count = n_input_params;
msg->output_param_count = 1;
do {
- ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
+ ret = adf_send_message(ctx->inst->pke_tx, (u32 *)msg);
} while (ret == -EBUSY && ctr++ < 100);
if (!ret)
@@ -734,11 +734,11 @@ static int qat_rsa_enc(struct akcipher_request *req)
msg->pke_mid.src_data_addr = qat_req->phy_in;
msg->pke_mid.dest_data_addr = qat_req->phy_out;
- msg->pke_mid.opaque = (uint64_t)(__force long)qat_req;
+ msg->pke_mid.opaque = (u64)(__force long)qat_req;
msg->input_param_count = 3;
msg->output_param_count = 1;
do {
- ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
+ ret = adf_send_message(ctx->inst->pke_tx, (u32 *)msg);
} while (ret == -EBUSY && ctr++ < 100);
if (!ret)
@@ -882,7 +882,7 @@ static int qat_rsa_dec(struct akcipher_request *req)
msg->pke_mid.src_data_addr = qat_req->phy_in;
msg->pke_mid.dest_data_addr = qat_req->phy_out;
- msg->pke_mid.opaque = (uint64_t)(__force long)qat_req;
+ msg->pke_mid.opaque = (u64)(__force long)qat_req;
if (ctx->crt_mode)
msg->input_param_count = 6;
else
@@ -890,7 +890,7 @@ static int qat_rsa_dec(struct akcipher_request *req)
msg->output_param_count = 1;
do {
- ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
+ ret = adf_send_message(ctx->inst->pke_tx, (u32 *)msg);
} while (ret == -EBUSY && ctr++ < 100);
if (!ret)
diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c
index 9a80da0b3b28..fa467e0f8285 100644
--- a/drivers/crypto/qat/qat_common/qat_hal.c
+++ b/drivers/crypto/qat/qat_common/qat_hal.c
@@ -34,13 +34,13 @@
#define AE(handle, ae) handle->hal_handle->aes[ae]
-static const uint64_t inst_4b[] = {
+static const u64 inst_4b[] = {
0x0F0400C0000ull, 0x0F4400C0000ull, 0x0F040000300ull, 0x0F440000300ull,
0x0FC066C0000ull, 0x0F0000C0300ull, 0x0F0000C0300ull, 0x0F0000C0300ull,
0x0A021000000ull
};
-static const uint64_t inst[] = {
+static const u64 inst[] = {
0x0F0000C0000ull, 0x0F000000380ull, 0x0D805000011ull, 0x0FC082C0300ull,
0x0F0000C0300ull, 0x0F0000C0300ull, 0x0F0000C0300ull, 0x0F0000C0300ull,
0x0A0643C0000ull, 0x0BAC0000301ull, 0x0D802000101ull, 0x0F0000C0001ull,
@@ -502,7 +502,7 @@ static void qat_hal_disable_ctx(struct icp_qat_fw_loader_handle *handle,
qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx);
}
-static uint64_t qat_hal_parity_64bit(uint64_t word)
+static u64 qat_hal_parity_64bit(u64 word)
{
word ^= word >> 1;
word ^= word >> 2;
@@ -513,9 +513,9 @@ static uint64_t qat_hal_parity_64bit(uint64_t word)
return word & 1;
}
-static uint64_t qat_hal_set_uword_ecc(uint64_t uword)
+static u64 qat_hal_set_uword_ecc(u64 uword)
{
- uint64_t bit0_mask = 0xff800007fffULL, bit1_mask = 0x1f801ff801fULL,
+ u64 bit0_mask = 0xff800007fffULL, bit1_mask = 0x1f801ff801fULL,
bit2_mask = 0xe387e0781e1ULL, bit3_mask = 0x7cb8e388e22ULL,
bit4_mask = 0xaf5b2c93244ULL, bit5_mask = 0xf56d5525488ULL,
bit6_mask = 0xdaf69a46910ULL;
@@ -534,7 +534,7 @@ static uint64_t qat_hal_set_uword_ecc(uint64_t uword)
void qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle,
unsigned char ae, unsigned int uaddr,
- unsigned int words_num, uint64_t *uword)
+ unsigned int words_num, u64 *uword)
{
unsigned int ustore_addr;
unsigned int i;
@@ -544,7 +544,7 @@ void qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle,
qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);
for (i = 0; i < words_num; i++) {
unsigned int uwrd_lo, uwrd_hi;
- uint64_t tmp;
+ u64 tmp;
tmp = qat_hal_set_uword_ecc(uword[i]);
uwrd_lo = (unsigned int)(tmp & 0xffffffff);
@@ -600,7 +600,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
csr_val |= CE_NN_MODE;
qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);
qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst),
- (uint64_t *)inst);
+ (u64 *)inst);
qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT,
handle->hal_handle->upc_mask &
INIT_PC_VALUE);
@@ -777,7 +777,7 @@ void qat_hal_set_pc(struct icp_qat_fw_loader_handle *handle,
static void qat_hal_get_uwords(struct icp_qat_fw_loader_handle *handle,
unsigned char ae, unsigned int uaddr,
- unsigned int words_num, uint64_t *uword)
+ unsigned int words_num, u64 *uword)
{
unsigned int i, uwrd_lo, uwrd_hi;
unsigned int ustore_addr, misc_control;
@@ -827,11 +827,11 @@ void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle,
#define MAX_EXEC_INST 100
static int qat_hal_exec_micro_inst(struct icp_qat_fw_loader_handle *handle,
unsigned char ae, unsigned char ctx,
- uint64_t *micro_inst, unsigned int inst_num,
+ u64 *micro_inst, unsigned int inst_num,
int code_off, unsigned int max_cycle,
unsigned int *endpc)
{
- uint64_t savuwords[MAX_EXEC_INST];
+ u64 savuwords[MAX_EXEC_INST];
unsigned int ind_lm_addr0, ind_lm_addr1;
unsigned int ind_lm_addr_byte0, ind_lm_addr_byte1;
unsigned int ind_cnt_sig;
@@ -928,7 +928,7 @@ static int qat_hal_rd_rel_reg(struct icp_qat_fw_loader_handle *handle,
unsigned int ctxarb_cntl, ustore_addr, ctx_enables;
unsigned short reg_addr;
int status = 0;
- uint64_t insts, savuword;
+ u64 insts, savuword;
reg_addr = qat_hal_get_reg_addr(reg_type, reg_num);
if (reg_addr == BAD_REGADDR) {
@@ -940,7 +940,7 @@ static int qat_hal_rd_rel_reg(struct icp_qat_fw_loader_handle *handle,
insts = 0xA070000000ull | (reg_addr & 0x3ff);
break;
default:
- insts = (uint64_t)0xA030000000ull | ((reg_addr & 0x3ff) << 10);
+ insts = (u64)0xA030000000ull | ((reg_addr & 0x3ff) << 10);
break;
}
savctx = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);
@@ -986,7 +986,7 @@ static int qat_hal_wr_rel_reg(struct icp_qat_fw_loader_handle *handle,
unsigned short reg_num, unsigned int data)
{
unsigned short src_hiaddr, src_lowaddr, dest_addr, data16hi, data16lo;
- uint64_t insts[] = {
+ u64 insts[] = {
0x0F440000000ull,
0x0F040000000ull,
0x0F0000C0300ull,
@@ -1032,13 +1032,13 @@ int qat_hal_get_ins_num(void)
return ARRAY_SIZE(inst_4b);
}
-static int qat_hal_concat_micro_code(uint64_t *micro_inst,
+static int qat_hal_concat_micro_code(u64 *micro_inst,
unsigned int inst_num, unsigned int size,
unsigned int addr, unsigned int *value)
{
int i;
unsigned int cur_value;
- const uint64_t *inst_arr;
+ const u64 *inst_arr;
int fixup_offset;
int usize = 0;
int orig_num;
@@ -1063,7 +1063,7 @@ static int qat_hal_concat_micro_code(uint64_t *micro_inst,
static int qat_hal_exec_micro_init_lm(struct icp_qat_fw_loader_handle *handle,
unsigned char ae, unsigned char ctx,
- int *pfirst_exec, uint64_t *micro_inst,
+ int *pfirst_exec, u64 *micro_inst,
unsigned int inst_num)
{
int stat = 0;
@@ -1096,7 +1096,7 @@ int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle,
struct icp_qat_uof_batch_init *lm_init_header)
{
struct icp_qat_uof_batch_init *plm_init;
- uint64_t *micro_inst_arry;
+ u64 *micro_inst_arry;
int micro_inst_num;
int alloc_inst_size;
int first_exec = 1;
@@ -1106,7 +1106,7 @@ int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle,
alloc_inst_size = lm_init_header->size;
if ((unsigned int)alloc_inst_size > handle->hal_handle->max_ustore)
alloc_inst_size = handle->hal_handle->max_ustore;
- micro_inst_arry = kmalloc_array(alloc_inst_size, sizeof(uint64_t),
+ micro_inst_arry = kmalloc_array(alloc_inst_size, sizeof(u64),
GFP_KERNEL);
if (!micro_inst_arry)
return -ENOMEM;
@@ -1185,7 +1185,7 @@ static int qat_hal_put_rel_wr_xfer(struct icp_qat_fw_loader_handle *handle,
data16low;
unsigned short reg_mask;
int status = 0;
- uint64_t micro_inst[] = {
+ u64 micro_inst[] = {
0x0F440000000ull,
0x0F040000000ull,
0x0A000000000ull,
diff --git a/drivers/crypto/qat/qat_common/qat_uclo.c b/drivers/crypto/qat/qat_common/qat_uclo.c
index 3f079e336f64..4cc1f436b075 100644
--- a/drivers/crypto/qat/qat_common/qat_uclo.c
+++ b/drivers/crypto/qat/qat_common/qat_uclo.c
@@ -367,16 +367,16 @@ static int qat_uclo_init_ustore(struct icp_qat_fw_loader_handle *handle,
unsigned int ustore_size;
unsigned int patt_pos;
struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
- uint64_t *fill_data;
+ u64 *fill_data;
uof_image = image->img_ptr;
- fill_data = kcalloc(ICP_QAT_UCLO_MAX_USTORE, sizeof(uint64_t),
+ fill_data = kcalloc(ICP_QAT_UCLO_MAX_USTORE, sizeof(u64),
GFP_KERNEL);
if (!fill_data)
return -ENOMEM;
for (i = 0; i < ICP_QAT_UCLO_MAX_USTORE; i++)
memcpy(&fill_data[i], &uof_image->fill_pattern,
- sizeof(uint64_t));
+ sizeof(u64));
page = image->page;
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) {
@@ -937,7 +937,7 @@ static int qat_uclo_parse_uof_obj(struct icp_qat_fw_loader_handle *handle)
pr_err("QAT: UOF incompatible\n");
return -EINVAL;
}
- obj_handle->uword_buf = kcalloc(UWORD_CPYBUF_SIZE, sizeof(uint64_t),
+ obj_handle->uword_buf = kcalloc(UWORD_CPYBUF_SIZE, sizeof(u64),
GFP_KERNEL);
if (!obj_handle->uword_buf)
return -ENOMEM;
@@ -1141,7 +1141,7 @@ static int qat_uclo_map_suof(struct icp_qat_fw_loader_handle *handle,
return 0;
}
-#define ADD_ADDR(high, low) ((((uint64_t)high) << 32) + low)
+#define ADD_ADDR(high, low) ((((u64)high) << 32) + low)
#define BITS_IN_DWORD 32
static int qat_uclo_auth_fw(struct icp_qat_fw_loader_handle *handle,
@@ -1470,10 +1470,10 @@ void qat_uclo_del_uof_obj(struct icp_qat_fw_loader_handle *handle)
static void qat_uclo_fill_uwords(struct icp_qat_uclo_objhandle *obj_handle,
struct icp_qat_uclo_encap_page *encap_page,
- uint64_t *uword, unsigned int addr_p,
- unsigned int raddr, uint64_t fill)
+ u64 *uword, unsigned int addr_p,
+ unsigned int raddr, u64 fill)
{
- uint64_t uwrd = 0;
+ u64 uwrd = 0;
unsigned int i;
if (!encap_page) {
@@ -1503,12 +1503,12 @@ static void qat_uclo_wr_uimage_raw_page(struct icp_qat_fw_loader_handle *handle,
{
unsigned int uw_physical_addr, uw_relative_addr, i, words_num, cpylen;
struct icp_qat_uclo_objhandle *obj_handle = handle->obj_handle;
- uint64_t fill_pat;
+ u64 fill_pat;
/* load the page starting at appropriate ustore address */
/* get fill-pattern from an image -- they are all the same */
memcpy(&fill_pat, obj_handle->ae_uimage[0].img_ptr->fill_pattern,
- sizeof(uint64_t));
+ sizeof(u64));
uw_physical_addr = encap_page->beg_addr_p;
uw_relative_addr = 0;
words_num = encap_page->micro_words_num;
diff --git a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
index 0461040303a2..b975c263446d 100644
--- a/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+++ b/drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
@@ -6,13 +6,13 @@
#include "adf_dh895xcc_hw_data.h"
/* Worker thread to service arbiter mappings based on dev SKUs */
-static const uint32_t thrd_to_arb_map_sku4[] = {
+static const u32 thrd_to_arb_map_sku4[] = {
0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
0x00000000, 0x00000000, 0x00000000, 0x00000000
};
-static const uint32_t thrd_to_arb_map_sku6[] = {
+static const u32 thrd_to_arb_map_sku6[] = {
0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222
@@ -24,20 +24,20 @@ static struct adf_hw_device_class dh895xcc_class = {
.instances = 0
};
-static uint32_t get_accel_mask(uint32_t fuse)
+static u32 get_accel_mask(u32 fuse)
{
return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
ADF_DH895XCC_ACCELERATORS_MASK;
}
-static uint32_t get_ae_mask(uint32_t fuse)
+static u32 get_ae_mask(u32 fuse)
{
return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK;
}
-static uint32_t get_num_accels(struct adf_hw_device_data *self)
+static u32 get_num_accels(struct adf_hw_device_data *self)
{
- uint32_t i, ctr = 0;
+ u32 i, ctr = 0;
if (!self || !self->accel_mask)
return 0;
@@ -49,9 +49,9 @@ static uint32_t get_num_accels(struct adf_hw_device_data *self)
return ctr;
}
-static uint32_t get_num_aes(struct adf_hw_device_data *self)
+static u32 get_num_aes(struct adf_hw_device_data *self)
{
- uint32_t i, ctr = 0;
+ u32 i, ctr = 0;
if (!self || !self->ae_mask)
return 0;
@@ -63,17 +63,17 @@ static uint32_t get_num_aes(struct adf_hw_device_data *self)
return ctr;
}
-static uint32_t get_misc_bar_id(struct adf_hw_device_data *self)
+static u32 get_misc_bar_id(struct adf_hw_device_data *self)
{
return ADF_DH895XCC_PMISC_BAR;
}
-static uint32_t get_etr_bar_id(struct adf_hw_device_data *self)
+static u32 get_etr_bar_id(struct adf_hw_device_data *self)
{
return ADF_DH895XCC_ETR_BAR;
}
-static uint32_t get_sram_bar_id(struct adf_hw_device_data *self)
+static u32 get_sram_bar_id(struct adf_hw_device_data *self)
{
return ADF_DH895XCC_SRAM_BAR;
}
@@ -117,12 +117,12 @@ static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
}
}
-static uint32_t get_pf2vf_offset(uint32_t i)
+static u32 get_pf2vf_offset(u32 i)
{
return ADF_DH895XCC_PF2VF_OFFSET(i);
}
-static uint32_t get_vintmsk_offset(uint32_t i)
+static u32 get_vintmsk_offset(u32 i)
{
return ADF_DH895XCC_VINTMSK_OFFSET(i);
}
--
2.26.2
On Wed, Jun 03, 2020 at 06:33:43PM +0100, Giovanni Cabiddu wrote:
> Remove user types across qat code base and replace packed attribute in
> etr ring struct which causes a split lock.
>
> These changes are on top of "crypto: qat - fix parameter check in aead
> encryption" (https://patchwork.kernel.org/patch/11574001/)
>
> Giovanni Cabiddu (1):
> crypto: qat - remove packed attribute in etr structs
>
> Wojciech Ziemba (2):
> crypto: qat - replace user types with kernel u types
> crypto: qat - replace user types with kernel ABI __u types
>
> .../crypto/qat/qat_common/adf_accel_devices.h | 54 +++---
> .../crypto/qat/qat_common/adf_accel_engine.c | 4 +-
> drivers/crypto/qat/qat_common/adf_aer.c | 2 +-
> .../crypto/qat/qat_common/adf_cfg_common.h | 24 +--
> drivers/crypto/qat/qat_common/adf_cfg_user.h | 10 +-
> .../crypto/qat/qat_common/adf_common_drv.h | 12 +-
> drivers/crypto/qat/qat_common/adf_ctl_drv.c | 4 +-
> drivers/crypto/qat/qat_common/adf_dev_mgr.c | 8 +-
> drivers/crypto/qat/qat_common/adf_transport.c | 62 +++----
> drivers/crypto/qat/qat_common/adf_transport.h | 4 +-
> .../qat_common/adf_transport_access_macros.h | 6 +-
> .../qat/qat_common/adf_transport_internal.h | 27 ++-
> drivers/crypto/qat/qat_common/icp_qat_fw.h | 58 +++----
> .../qat/qat_common/icp_qat_fw_init_admin.h | 46 ++---
> drivers/crypto/qat/qat_common/icp_qat_fw_la.h | 158 +++++++++---------
> .../crypto/qat/qat_common/icp_qat_fw_pke.h | 52 +++---
> drivers/crypto/qat/qat_common/icp_qat_hw.h | 16 +-
> drivers/crypto/qat/qat_common/icp_qat_uclo.h | 6 +-
> drivers/crypto/qat/qat_common/qat_algs.c | 54 +++---
> drivers/crypto/qat/qat_common/qat_asym_algs.c | 12 +-
> drivers/crypto/qat/qat_common/qat_hal.c | 40 ++---
> drivers/crypto/qat/qat_common/qat_uclo.c | 20 +--
> .../qat/qat_dh895xcc/adf_dh895xcc_hw_data.c | 26 +--
> 23 files changed, 352 insertions(+), 353 deletions(-)
All applied. Thanks.
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt