From: Conor Dooley <[email protected]>
This series updates the Microchip Icicle Kit device tree by adding a
host of peripherals, and some updates to the memory map. In addition,
the device tree has been split into a third part, which contains "soft"
peripherals that are in the fpga fabric.
Several of the entries are for peripherals that have not get had their
drivers upstreamed, so in those cases the dt bindings are included where
appropriate in order to avoid as many "DT compatible string <x> appears
un-documented" errors as possible.
Depends on mpfs clock driver series [1] to provide:
dt-bindings/clock/microchip,mpfs-clock.h
and on the other changes to the icicle/mpfs device tree (mmc) that are
already in linux/riscv/for-next.
Also depends on Geert's format changes to interrupt grouping etc [2].
Additionally, the interrupt-extended warnings on the plic/clint are
cleared by [3] & [4], which lore appears to have been very confused about.
[1] https://lore.kernel.org/linux-clk/[email protected]/T/
[2] https://lore.kernel.org/linux-riscv/[email protected]/T/
[3] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
[4] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
Conor Dooley (16):
dt-bindings: soc/microchip: update syscontroller compatibles
dt-bindings: soc/microchip: make systemcontroller a mfd
mailbox: change mailbox-mpfs compatible string
dt-bindings: i2c: add bindings for microchip mpfs i2c
dt-bindings: rng: add bindings for microchip mpfs rng
dt-bindings: rtc: add bindings for microchip mpfs rtc
dt-bindings: soc/microchip: add bindings for mpfs system services
dt-bindings: gpio: add bindings for microchip mpfs gpio
dt-bindings: spi: add bindings for microchip mpfs spi
dt-bindings: usb: add bindings for microchip mpfs musb
dt-bindings: pwm: add microchip corePWM binding
riscv: dts: microchip: use hart and clk defines for icicle kit
riscv: dts: microchip: add fpga fabric section to icicle kit
riscv: dts: microchip: refactor icicle kit device tree
riscv: dts: microchip: update peripherals in icicle kit device tree
MAINTAINERS: update riscv/microchip entry
Ivan Griffin (1):
dt-bindings: interrupt-controller: create a header for RISC-V
interrupts
.../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++
.../bindings/i2c/microchip,mpfs-i2c.yaml | 54 ++++
...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +-
.../bindings/pwm/microchip,corepwm.yaml | 61 ++++
.../bindings/rng/microchip,mpfs-rng.yaml | 29 ++
.../bindings/rtc/microchip,mfps-rtc.yaml | 63 ++++
.../microchip,mpfs-generic-service.yaml | 33 ++
.../microchip,mpfs-sys-controller.yaml | 62 ++++
...icrochip,polarfire-soc-sys-controller.yaml | 35 ---
.../bindings/spi/microchip,mpfs-spi.yaml | 61 ++++
.../bindings/usb/microchip,mpfs-musb.yaml | 61 ++++
MAINTAINERS | 2 +
.../dts/microchip/microchip-mpfs-fabric.dtsi | 13 +
.../microchip/microchip-mpfs-icicle-kit.dts | 111 +++++--
.../boot/dts/microchip/microchip-mpfs.dtsi | 295 ++++++++++++++----
drivers/mailbox/mailbox-mpfs.c | 2 +-
.../interrupt-controller/riscv-hart.h | 19 ++
17 files changed, 872 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
--
2.33.1
From: Ivan Griffin <[email protected]>
Provide named identifiers for device tree for RISC-V interrupts.
Licensed under GPL and MIT, as this file may be useful to any OS that
uses device tree.
Signed-off-by: Ivan Griffin <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
.../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
new file mode 100644
index 000000000000..e1c32f6090ac
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/riscv-hart.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2021 Microchip Technology Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
+
+#define HART_INT_U_SOFT 0
+#define HART_INT_S_SOFT 1
+#define HART_INT_M_SOFT 3
+#define HART_INT_U_TIMER 4
+#define HART_INT_S_TIMER 5
+#define HART_INT_M_TIMER 7
+#define HART_INT_U_EXT 8
+#define HART_INT_S_EXT 9
+#define HART_INT_M_EXT 11
+
+#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
--
2.33.1
From: Conor Dooley <[email protected]>
The Polarfire SoC is currently using two different compatible string
prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
its system controller in order to match the compatible string used in
the soc binding and device tree.
Signed-off-by: Conor Dooley <[email protected]>
---
...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)
diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
similarity index 82%
rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
index bbb173ea483c..9251c2218c68 100644
--- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
+$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
@@ -11,7 +11,7 @@ maintainers:
properties:
compatible:
- const: microchip,polarfire-soc-mailbox
+ const: microchip,mpfs-mailbox
reg:
items:
@@ -38,7 +38,7 @@ examples:
#address-cells = <2>;
#size-cells = <2>;
mbox: mailbox@37020000 {
- compatible = "microchip,polarfire-soc-mailbox";
+ compatible = "mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
interrupt-parent = <&L1>;
interrupts = <96>;
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
similarity index 75%
rename from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 2cd3bc6bd8d6..f699772fedf3 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
@@ -19,7 +19,7 @@ properties:
maxItems: 1
compatible:
- const: microchip,polarfire-soc-sys-controller
+ const: microchip,mpfs-sys-controller
required:
- compatible
@@ -30,6 +30,6 @@ additionalProperties: false
examples:
- |
syscontroller: syscontroller {
- compatible = "microchip,polarfire-soc-sys-controller";
+ compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
--
2.33.1
From: Conor Dooley <[email protected]>
Make the system controller on the Polarfire SoC
a "simple,mfd" so that the services can be child
nodes of the system controller node.
Signed-off-by: Conor Dooley <[email protected]>
---
.../microchip,mpfs-sys-controller.yaml | 33 +++++++++++++++++--
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index f699772fedf3..014cb44b8f31 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -13,13 +13,34 @@ description: |
The PolarFire SoC system controller is communicated with via a mailbox.
This document describes the bindings for the client portion of that mailbox.
-
properties:
mboxes:
maxItems: 1
compatible:
- const: microchip,mpfs-sys-controller
+ items:
+ - const: microchip,mpfs-sys-controller
+ - const: simple-mfd
+
+ hwrandom:
+ type: object
+
+ properties:
+ compatible:
+ const: microchip,mpfs-rng
+
+ required:
+ - compatible
+
+ sysserv:
+ type: object
+
+ properties:
+ compatible:
+ const: microchip,mpfs-generic-service
+
+ required:
+ - compatible
required:
- compatible
@@ -30,6 +51,12 @@ additionalProperties: false
examples:
- |
syscontroller: syscontroller {
- compatible = "microchip,mpfs-sys-controller";
+ compatible = "microchip,mpfs-sys-controller", "simple-mfd";
mboxes = <&mbox 0>;
+ hwrandom: hwrandom {
+ compatible = "microchip,mpfs-rng";
+ };
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ };
};
--
2.33.1
From: Conor Dooley <[email protected]>
The Polarfire SoC is currently using two different compatible string
prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
its system controller in order to match the compatible string used in
the soc binding and device tree.
Signed-off-by: Conor Dooley <[email protected]>
---
drivers/mailbox/mailbox-mpfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index 0d6e2231a2c7..4e34854d1238 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -232,7 +232,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev)
}
static const struct of_device_id mpfs_mbox_of_match[] = {
- {.compatible = "microchip,polarfire-soc-mailbox", },
+ {.compatible = "microchip,mpfs-mailbox", },
{},
};
MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the hardware rng device accessed via
the system services on the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/rng/microchip,mpfs-rng.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
new file mode 100644
index 000000000000..32cbc37c9292
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip MPFS random number generator
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+description: |
+ The hardware random number generator on the Polarfire SoC is
+ accessed via the mailbox interface provided by the system controller
+
+properties:
+ compatible:
+ const: microchip,mpfs-rng
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ hwrandom: hwrandom {
+ compatible = "microchip,mpfs-rng";
+ };
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the i2c controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Daire McNamara <[email protected]>
---
.../bindings/i2c/microchip,mpfs-i2c.yaml | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
new file mode 100644
index 000000000000..2acaf1a7e0de
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/microchip,mpfs-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS I2C Controller Device Tree Bindings
+
+maintainers:
+ - Daire McNamara <[email protected]>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ description: |
+ Desired I2C bus clock frequency in Hz. As only Standard and Fast
+ modes are supported, possible values are 100000 and 400000.
+ enum: [100000, 400000]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x2010a000 0x1000>;
+ clocks = <&clkcfg CLK_I2C0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clock-frequency = <100000>;
+ };
+...
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the real time clock on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Daire McNamara <[email protected]>
---
.../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
new file mode 100644
index 000000000000..d57460cbe5e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Daire McNamara <[email protected]>
+ - Lewis Hanly <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 2
+
+ microchip,prescaler:
+ description: |
+ The prescaler divides the input frequency to create a time-based strobe (typically 1 Hz) for
+ the calendar counter. The Alarm and Compare Registers, in conjunction with the calendar
+ counter, facilitate time-matched events. To properly operate in Calendar or Binary mode,
+ the 26-bit prescaler must be programmed to generate a strobe to the RTC.
+ maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rtc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x20124000 0x1000>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ interrupts = <80>, <81>;
+ };
+...
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the gpio controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 000000000000..aa1fbb44f9ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,mpfs-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 1
+
+ ngpios:
+ description:
+ The number of GPIOs available.
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - interrupt-controller
+ - "#gpio-cells"
+ - gpio-controller
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x20122000 0x1000>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ };
+...
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the services provided by the system
controller directly on the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
---
.../microchip,mpfs-generic-service.yaml | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
new file mode 100644
index 000000000000..d044525b3487
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-generic-service.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip MPFS system services
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+description: |
+ The PolarFire SoC system controller is communicated with via a mailbox.
+ This binding represents several of the functions provided by the system
+ controller which do not belong in a specific subsystem, such as reading
+ the fpga device certificate, all of which follow the same format:
+ - a command + optional payload sent to the sys controller
+ - a status + a payload returned to Linux.
+
+properties:
+ compatible:
+ const: microchip,mpfs-generic-service
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ };
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the {q,}spi controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/spi/microchip,mpfs-spi.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
new file mode 100644
index 000000000000..fe257b3384a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-spi
+ - microchip,mpfs-qspi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ num-cs:
+ description: |
+ Number of chip selects used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 8
+ default: 8
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ reg = <0x20108000 0x1000>;
+ clocks = <&clkcfg CLK_SPI0>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ };
+...
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the usb controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/usb/microchip,mpfs-musb.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
new file mode 100644
index 000000000000..eec918046c73
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS USB Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-musb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ interrupt-names:
+ items:
+ - const: dma
+ - const: mc
+
+ clocks:
+ maxItems: 1
+
+ dr_mode:
+ enum:
+ - host
+ - otg
+ - peripheral
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - dr_mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x20201000 0x1000>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ interrupt-names = "dma","mc";
+ dr_mode = "host";
+ };
+
+...
--
2.33.1
From: Conor Dooley <[email protected]>
Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.
Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/pwm/microchip,corepwm.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
new file mode 100644
index 000000000000..ed7d0351adc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip ip core PWM controller bindings
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+description: |
+ corePWM is an 16 channel pulse width modulator FPGA IP
+
+ https://www.microsemi.com/existing-parts/parts/152118
+
+properties:
+ compatible:
+ items:
+ - const: microchip,corepwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ microchip,sync-update:
+ description: |
+ In synchronous mode, all channels are updated at the beginning of the PWM period.
+ Asynchronous mode is relevant to applications such as LED control, where
+ synchronous updates are not required. Asynchronous mode lowers the area size,
+ reducing shadow register requirements. This can be set at run time, provided
+ SHADOW_REG_EN is asserted. SHADOW_REG_EN is set by the FPGA bitstream programmed
+ to the device.
+
+ $ref: /schemas/types.yaml#/definitions/uint8
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#pwm-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ corePWN1: corePWM@41000000 {
+ compatible = "microchip,corepwm";
+ microchip,sync-update = /bits/ 8 <1>;
+ clocks = <&clkcfg CLK_FIC3>;
+ reg = <0x41000000 0xF0>;
+ #pwm-cells = <2>;
+ };
--
2.33.1
From: Conor Dooley <[email protected]>
Update the Microchip Icicle kit device tree by replacing interrupt and
clock related magic numbers with their defined counterparts.
Signed-off-by: Conor Dooley <[email protected]>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 2 +-
.../boot/dts/microchip/microchip-mpfs.dtsi | 55 +++++++++++--------
2 files changed, 34 insertions(+), 23 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 0c748ae1b006..6d19ba196f12 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -31,7 +31,7 @@ cpus {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
- clocks = <&clkcfg 26>;
+ clocks = <&clkcfg CLK_DDRC>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 869aaf0d5c06..ce9151edd1b6 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -2,6 +2,8 @@
/* Copyright (c) 2020 Microchip Technology Inc */
/dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "dt-bindings/interrupt-controller/riscv-hart.h"
/ {
#address-cells = <2>;
@@ -14,7 +16,6 @@ cpus {
#size-cells = <0>;
cpu@0 {
- clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -22,6 +23,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -32,7 +34,6 @@ cpu0_intc: interrupt-controller {
};
cpu@1 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -48,6 +49,7 @@ cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -59,7 +61,6 @@ cpu1_intc: interrupt-controller {
};
cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -75,6 +76,7 @@ cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -86,7 +88,6 @@ cpu2_intc: interrupt-controller {
};
cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -102,6 +103,7 @@ cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -113,7 +115,6 @@ cpu3_intc: interrupt-controller {
};
cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -129,6 +130,7 @@ cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
cpu4_intc: interrupt-controller {
@@ -165,11 +167,16 @@ cache-controller@2010000 {
clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
- <&cpu1_intc 3>, <&cpu1_intc 7>,
- <&cpu2_intc 3>, <&cpu2_intc 7>,
- <&cpu3_intc 3>, <&cpu3_intc 7>,
- <&cpu4_intc 3>, <&cpu4_intc 7>;
+ interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>,
+ <&cpu0_intc HART_INT_M_TIMER>,
+ <&cpu1_intc HART_INT_M_SOFT>,
+ <&cpu1_intc HART_INT_M_TIMER>,
+ <&cpu2_intc HART_INT_M_SOFT>,
+ <&cpu2_intc HART_INT_M_TIMER>,
+ <&cpu3_intc HART_INT_M_SOFT>,
+ <&cpu3_intc HART_INT_M_TIMER>,
+ <&cpu4_intc HART_INT_M_SOFT>,
+ <&cpu4_intc HART_INT_M_TIMER>;
};
plic: interrupt-controller@c000000 {
@@ -178,11 +185,15 @@ plic: interrupt-controller@c000000 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>,
- <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupts-extended = <&cpu0_intc HART_INT_M_EXT>,
+ <&cpu1_intc HART_INT_M_EXT>,
+ <&cpu1_intc HART_INT_S_EXT>,
+ <&cpu2_intc HART_INT_M_EXT>,
+ <&cpu2_intc HART_INT_S_EXT>,
+ <&cpu3_intc HART_INT_M_EXT>,
+ <&cpu3_intc HART_INT_S_EXT>,
+ <&cpu4_intc HART_INT_M_EXT>,
+ <&cpu4_intc HART_INT_S_EXT>;
riscv,ndev = <186>;
};
@@ -210,7 +221,7 @@ serial0: serial@20000000 {
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
- clocks = <&clkcfg 8>;
+ clocks = <&clkcfg CLK_MMUART0>;
status = "disabled";
};
@@ -222,7 +233,7 @@ serial1: serial@20100000 {
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
- clocks = <&clkcfg 9>;
+ clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
@@ -234,7 +245,7 @@ serial2: serial@20102000 {
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
- clocks = <&clkcfg 10>;
+ clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
@@ -246,7 +257,7 @@ serial3: serial@20104000 {
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
- clocks = <&clkcfg 11>;
+ clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
@@ -256,7 +267,7 @@ mmc: mmc@20008000 {
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>, <89>;
- clocks = <&clkcfg 6>;
+ clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
@@ -267,7 +278,7 @@ emac0: ethernet@20110000 {
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 4>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
#address-cells = <1>;
@@ -280,7 +291,7 @@ emac1: ethernet@20112000 {
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 5>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
status = "disabled";
clock-names = "pclk", "hclk";
#address-cells = <1>;
--
2.33.1
From: Conor Dooley <[email protected]>
Split the device tree for the Microchip MPFS into two sections by adding
microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
FPGA fabric.
Signed-off-by: Conor Dooley <[email protected]>
---
.../boot/dts/microchip/microchip-mpfs-fabric.dtsi | 13 +++++++++++++
.../dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 1 +
3 files changed, 18 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
new file mode 100644
index 000000000000..234c1f9bea40
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+ corePWM0: pwm@41000000 {
+ compatible = "microchip,corepwm";
+ reg = <0x0 0x41000000 0x0 0xF0>;
+ microchip,sync-update = /bits/ 8 <0>;
+ #pwm-cells = <2>;
+ clocks = <&clkcfg CLK_FIC3>;
+ status = "disabled";
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 6d19ba196f12..174f977c164b 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -86,3 +86,7 @@ phy1: ethernet-phy@9 {
ti,fifo-depth = <0x01>;
};
};
+
+&corePWM0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index ce9151edd1b6..808500be26c3 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -4,6 +4,7 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
#include "dt-bindings/interrupt-controller/riscv-hart.h"
+#include "microchip-mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.33.1
From: Conor Dooley <[email protected]>
Assorted minor changes to the MPFS/Icicle kit device tree:
- rename serial to mmuart to match microchip documentation
- enable mmuart4 instead of mmuart0
- move stdout path to serial1 to avoid collision with
bootloader running on the e51
- split memory node to match updated fpga design
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs
Signed-off-by: Conor Dooley <[email protected]>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 52 ++++++++------
.../boot/dts/microchip/microchip-mpfs.dtsi | 70 ++++++++++---------
2 files changed, 68 insertions(+), 54 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 174f977c164b..f6542ef76046 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
@@ -13,25 +13,34 @@ / {
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- ethernet0 = &emac1;
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
};
chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
- memory@80000000 {
+ ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x40000000>;
+ clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
};
};
@@ -39,19 +48,19 @@ &refclk {
clock-frequency = <600000000>;
};
-&serial0 {
+&mmuart1 {
status = "okay";
};
-&serial1 {
+&mmuart2 {
status = "okay";
};
-&serial2 {
+&mmuart3 {
status = "okay";
};
-&serial3 {
+&mmuart4 {
status = "okay";
};
@@ -61,29 +70,32 @@ &mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
+ cap-mmc-highspeed;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
-&emac0 {
+&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x01>;
- };
};
-&emac1 {
+&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
- ti,fifo-depth = <0x01>;
+ ti,fifo-depth = <0x1>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x1>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 808500be26c3..d311c5ea27c9 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
@@ -16,7 +16,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -34,7 +34,7 @@ cpu0_intc: interrupt-controller {
};
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -61,7 +61,7 @@ cpu1_intc: interrupt-controller {
};
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -88,7 +88,7 @@ cpu2_intc: interrupt-controller {
};
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -115,7 +115,7 @@ cpu3_intc: interrupt-controller {
};
};
- cpu@4 {
+ cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -153,8 +153,9 @@ soc {
compatible = "simple-bus";
ranges;
- cache-controller@2010000 {
+ cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
@@ -162,10 +163,9 @@ cache-controller@2010000 {
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <2>, <3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
};
- clint@2000000 {
+ clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>,
@@ -198,15 +198,6 @@ plic: interrupt-controller@c000000 {
riscv,ndev = <186>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
@@ -214,7 +205,7 @@ clkcfg: clkcfg@20002000 {
#clock-cells = <1>;
};
- serial0: serial@20000000 {
+ mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
@@ -223,10 +214,10 @@ serial0: serial@20000000 {
interrupts = <90>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART0>;
- status = "disabled";
+ status = "disabled"; /* Reserved for the HSS */
};
- serial1: serial@20100000 {
+ mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
@@ -238,7 +229,7 @@ serial1: serial@20100000 {
status = "disabled";
};
- serial2: serial@20102000 {
+ mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
@@ -250,7 +241,7 @@ serial2: serial@20102000 {
status = "disabled";
};
- serial3: serial@20104000 {
+ mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
@@ -262,42 +253,53 @@ serial3: serial@20104000 {
status = "disabled";
};
+ mmuart4: serial@20106000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20106000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <94>;
+ clocks = <&clkcfg CLK_MMUART4>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
/* Common node entry for emmc/sd */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88>, <89>;
+ interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
- emac0: ethernet@20110000 {
+ mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <64>, <65>, <66>, <67>;
+ interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
- emac1: ethernet@20112000 {
+ mac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <70>, <71>, <72>, <73>;
+ interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- status = "disabled";
clock-names = "pclk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
+ status = "disabled";
};
-
};
};
--
2.33.1
From: Conor Dooley <[email protected]>
Add new peripherals to the MPFS, and enable them in the Icicle kit device tree:
2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.
Signed-off-by: Conor Dooley <[email protected]>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 171 ++++++++++++++++++
2 files changed, 224 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index f6542ef76046..13172dec8e9f 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -80,6 +80,26 @@ &mmc {
sd-uhs-sdr104;
};
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
@@ -99,6 +119,39 @@ phy0: ethernet-phy@8 {
};
};
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
&corePWM0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index d311c5ea27c9..2de9b23af46d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -276,6 +276,69 @@ mmc: mmc@20008000 {
status = "disabled";
};
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ clocks = <&clkcfg CLK_SPI0>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <55>;
+ clocks = <&clkcfg CLK_SPI1>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ qspi: spi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <85>;
+ clocks = <&clkcfg CLK_QSPI>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clocks = <&clkcfg CLK_I2C0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <61>;
+ clocks = <&clkcfg CLK_I2C1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
@@ -301,5 +364,113 @@ mac1: ethernet@20112000 {
clock-names = "pclk", "hclk";
status = "disabled";
};
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <80>, <81>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-names = "dma","mc";
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ microchip,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <96>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller", "simple-mfd";
+ mboxes = <&mbox 0>;
+
+ hwrandom: hwrandom {
+ compatible = "microchip,mpfs-rng";
+ };
+
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ };
+ };
};
};
--
2.33.1
From: Conor Dooley <[email protected]>
Update the RISC-V/Microchip entry by adding the microchip dts
directory and myself as maintainer
Signed-off-by: Conor Dooley <[email protected]>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a2345ce8521..3b1d6be7bd56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16348,8 +16348,10 @@ K: riscv
RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
M: Lewis Hanly <[email protected]>
+M: Conor Dooley <[email protected]>
L: [email protected]
S: Supported
+F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.33.1
Hi Conor,
On Fri, Dec 17, 2021 at 10:31 AM <[email protected]> wrote:
> Also depends on Geert's format changes to interrupt grouping etc [2].
>
> Additionally, the interrupt-extended warnings on the plic/clint are
> cleared by [3] & [4], which lore appears to have been very confused about.
Right, it ended up being even more messier than I thought, and confuses
"b4 am" too.
I will resend these 3 series later today.
> [1] https://lore.kernel.org/linux-clk/[email protected]/T/
> [2] https://lore.kernel.org/linux-riscv/[email protected]/T/
> [3] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
> [4] https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Dec 17, 2021 at 09:33:18AM +0000, [email protected] wrote:
> + num-cs:
> + description: |
> + Number of chip selects used.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 8
> + default: 8
Why do you need this property in the DT - isn't the number of chip
selects in the IP a fixes property?
On 17/12/2021 11:17, Mark Brown wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
know the content is safe
> On Fri, Dec 17, 2021 at 09:33:18AM +0000, [email protected]
wrote:
> > + num-cs:
> > + description: |
> > + Number of chip selects used.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + minimum: 1
> > + maximum: 8
> > + default: 8
>
> Why do you need this property in the DT - isn't the number of chip
> selects in the IP a fixes property?
Nope! It's an IP that's intended for use in FPGAs so the number of
selects may (and does) vary based on implementation.
On Fri, Dec 17, 2021 at 11:40:29AM +0000, [email protected] wrote:
> On 17/12/2021 11:17, Mark Brown wrote:
> > Why do you need this property in the DT - isn't the number of chip
> > selects in the IP a fixes property?
> Nope! It's an IP that's intended for use in FPGAs so the number of
> selects may (and does) vary based on implementation.
That doesn't explain why the number is needed in the binding - why do
you need this property in the DT?
On Fri, Dec 17, 2021 at 10:32 AM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> The Polarfire SoC is currently using two different compatible string
> prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
> its system controller in order to match the compatible string used in
> the soc binding and device tree.
>
> Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Dec 17, 2021 at 10:32 AM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> The Polarfire SoC is currently using two different compatible string
> prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
> its system controller in order to match the compatible string used in
> the soc binding and device tree.
>
> Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Conor,
Thanks for your patch!
On Fri, Dec 17, 2021 at 10:33 AM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Update the Microchip Icicle kit device tree by replacing interrupt and
> clock related magic numbers with their defined counterparts.
Usually we make a distinction between (a) numbers that can be looked
up easily in a datasheet, and (b) numbers that were made up because
we needed some mapping. Of course both types of numbers are fixed,
and cannot be changed.
For (a), we tend to use the hardcoded numbers in the DTS files, to
avoid reviewers having to go through another layer of indirection
(i.e. does the number for the define match the number in the
datasheet?).
For (b), we use the defines, as there is no other official place to
look up the numbers.
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -2,6 +2,8 @@
> /* Copyright (c) 2020 Microchip Technology Inc */
>
> /dts-v1/;
> +#include "dt-bindings/clock/microchip,mpfs-clock.h"
The clock numbers we're made-up, so they fall under (b).
> +#include "dt-bindings/interrupt-controller/riscv-hart.h"
I believe these are just the official CLIC interrupt IDs, so they
fall under (a)?
> @@ -165,11 +167,16 @@ cache-controller@2010000 {
> clint@2000000 {
> compatible = "sifive,fu540-c000-clint", "sifive,clint0";
> reg = <0x0 0x2000000 0x0 0xC000>;
> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> - <&cpu1_intc 3>, <&cpu1_intc 7>,
> - <&cpu2_intc 3>, <&cpu2_intc 7>,
> - <&cpu3_intc 3>, <&cpu3_intc 7>,
> - <&cpu4_intc 3>, <&cpu4_intc 7>;
> + interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>,
> + <&cpu0_intc HART_INT_M_TIMER>,
> + <&cpu1_intc HART_INT_M_SOFT>,
> + <&cpu1_intc HART_INT_M_TIMER>,
> + <&cpu2_intc HART_INT_M_SOFT>,
> + <&cpu2_intc HART_INT_M_TIMER>,
> + <&cpu3_intc HART_INT_M_SOFT>,
> + <&cpu3_intc HART_INT_M_TIMER>,
> + <&cpu4_intc HART_INT_M_SOFT>,
> + <&cpu4_intc HART_INT_M_TIMER>;
Hence I'm not sure we want changes like this?
> };
>
> plic: interrupt-controller@c000000 {
};
>
> @@ -210,7 +221,7 @@ serial0: serial@20000000 {
> interrupt-parent = <&plic>;
> interrupts = <90>;
> current-speed = <115200>;
> - clocks = <&clkcfg 8>;
> + clocks = <&clkcfg CLK_MMUART0>;
But this change is fine.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Conor,
On Fri, Dec 17, 2021 at 10:33 AM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Split the device tree for the Microchip MPFS into two sections by adding
> microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
> FPGA fabric.
>
> Signed-off-by: Conor Dooley <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> +
> +/ {
> + corePWM0: pwm@41000000 {
> + compatible = "microchip,corepwm";
> + reg = <0x0 0x41000000 0x0 0xF0>;
> + microchip,sync-update = /bits/ 8 <0>;
> + #pwm-cells = <2>;
> + clocks = <&clkcfg CLK_FIC3>;
> + status = "disabled";
> + };
I'm wondering if these should be grouped under a "fabric" subnode,
like we have an "soc" subnode for on-SoC devices? Rob?
BTW, do you already have a naming plan for different revisions of
FPGA fabric cores?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, 17 Dec 2021 09:33:10 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> The Polarfire SoC is currently using two different compatible string
> prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
> its system controller in order to match the compatible string used in
> the soc binding and device tree.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> ...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
> ...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
> rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.example.dt.yaml:0:0: /example-0/soc/mailbox@37020000: failed to match any schema with compatible: ['mpfs-mailbox']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1569804
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, 17 Dec 2021 09:33:18 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the {q,}spi controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/spi/microchip,mpfs-spi.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1569843
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, 17 Dec 2021 09:33:20 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/pwm/microchip,corepwm.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pwm/microchip,corepwm.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/pwm/microchip,corepwm.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1569853
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, 17 Dec 2021 09:33:19 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the usb controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/usb/microchip,mpfs-musb.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/usb/microchip,mpfs-musb.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1569849
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, 17 Dec 2021 09:33:15 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>
> ---
> .../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include <dt-bindings/clock/microchip,mpfs-clock.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1569828
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, 17 Dec 2021 09:33:13 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the i2c controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>
> ---
> .../bindings/i2c/microchip,mpfs-i2c.yaml | 54 +++++++++++++++++++
> 1 file changed, 54 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include <dt-bindings/clock/microchip,mpfs-clock.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1569825
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Fri, 17 Dec 2021 09:33:17 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the gpio controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1569834
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On 17/12/2021 10:33, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the hardware rng device accessed via
> the system services on the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/rng/microchip,mpfs-rng.yaml | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>
> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> new file mode 100644
> index 000000000000..32cbc37c9292
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> @@ -0,0 +1,29 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Microchip MPFS random number generator
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + The hardware random number generator on the Polarfire SoC is
> + accessed via the mailbox interface provided by the system controller
> +
> +properties:
> + compatible:
> + const: microchip,mpfs-rng
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + hwrandom: hwrandom {
Three topics:
1. Node name (as most of others are using): rng
2. skip the label, not helping in example.
3. This looks very simple, so I wonder if the bindings are complete. No
IO space/address... How is it going to be instantiated?
> + compatible = "microchip,mpfs-rng";
> + };
>
Best regards,
Krzysztof
On 17/12/2021 10:33, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/pwm/microchip,corepwm.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> new file mode 100644
> index 000000000000..ed7d0351adc9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip ip core PWM controller bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + corePWM is an 16 channel pulse width modulator FPGA IP
> +
> + https://www.microsemi.com/existing-parts/parts/152118
> +
> +properties:
> + compatible:
> + items:
> + - const: microchip,corepwm
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + "#pwm-cells":
> + const: 2
> +
> + microchip,sync-update:
> + description: |
> + In synchronous mode, all channels are updated at the beginning of the PWM period.
> + Asynchronous mode is relevant to applications such as LED control, where
> + synchronous updates are not required. Asynchronous mode lowers the area size,
> + reducing shadow register requirements. This can be set at run time, provided
> + SHADOW_REG_EN is asserted. SHADOW_REG_EN is set by the FPGA bitstream programmed
> + to the device.
Please also describe what is the meaning of the values used here. What
does a value "2" mean?
> +
> + $ref: /schemas/types.yaml#/definitions/uint8
> + default: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - "#pwm-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + corePWN1: corePWM@41000000 {
Here and in all patches, please skip the label. It's not helping.
Node name: pwm
> + compatible = "microchip,corepwm";
> + microchip,sync-update = /bits/ 8 <1>;
> + clocks = <&clkcfg CLK_FIC3>;
> + reg = <0x41000000 0xF0>;
> + #pwm-cells = <2>;
> + };
>
Best regards,
Krzysztof
On 17/12/2021 10:33, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Split the device tree for the Microchip MPFS into two sections by adding
> microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
> FPGA fabric.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../boot/dts/microchip/microchip-mpfs-fabric.dtsi | 13 +++++++++++++
> .../dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 1 +
> 3 files changed, 18 insertions(+)
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> new file mode 100644
> index 000000000000..234c1f9bea40
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> +
> +/ {
> + corePWM0: pwm@41000000 {
Lowercase labels please, so could be "core_pwm0".
Best regards,
Krzysztof
On 17/12/2021 10:33, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Assorted minor changes to the MPFS/Icicle kit device tree:
>
> - rename serial to mmuart to match microchip documentation
> - enable mmuart4 instead of mmuart0
This is not refactoring. Refactoring could include renames,
hierarchy/layout differences, naming, coding convention. You are
changing features, e.g. using different UART. Please split the changes.
> - move stdout path to serial1 to avoid collision with
> bootloader running on the e51
> - split memory node to match updated fpga design
> - move phy0 inside mac1 node to match phy configuration
> - add labels where missing (cpus, cache controller)
> - add missing address cells & interrupts to MACs
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../microchip/microchip-mpfs-icicle-kit.dts | 52 ++++++++------
> .../boot/dts/microchip/microchip-mpfs.dtsi | 70 ++++++++++---------
> 2 files changed, 68 insertions(+), 54 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> index 174f977c164b..f6542ef76046 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> -/* Copyright (c) 2020 Microchip Technology Inc */
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>
> /dts-v1/;
>
> @@ -13,25 +13,34 @@ / {
> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
>
> aliases {
> - ethernet0 = &emac1;
> - serial0 = &serial0;
> - serial1 = &serial1;
> - serial2 = &serial2;
> - serial3 = &serial3;
> + ethernet0 = &mac1;
> + serial0 = &mmuart0;
> + serial1 = &mmuart1;
> + serial2 = &mmuart2;
> + serial3 = &mmuart3;
> + serial4 = &mmuart4;
> };
>
> chosen {
> - stdout-path = "serial0:115200n8";
> + stdout-path = "serial1:115200n8";
> };
>
> cpus {
> timebase-frequency = <RTCCLK_FREQ>;
> };
>
> - memory@80000000 {
> + ddrc_cache_lo: memory@80000000 {
> device_type = "memory";
> - reg = <0x0 0x80000000 0x0 0x40000000>;
> + reg = <0x0 0x80000000 0x0 0x2e000000>;
> clocks = <&clkcfg CLK_DDRC>;
> + status = "okay";
> + };
> +
> + ddrc_cache_hi: memory@1000000000 {
This looks unrelated to refactoring - split of memory - and needs
separate change.
> + device_type = "memory";
> + reg = <0x10 0x0 0x0 0x40000000>;
> + clocks = <&clkcfg CLK_DDRC>;
> + status = "okay";
> };
> };
>
> @@ -39,19 +48,19 @@ &refclk {
> clock-frequency = <600000000>;
> };
>
> -&serial0 {
> +&mmuart1 {
> status = "okay";
> };
>
> -&serial1 {
> +&mmuart2 {
> status = "okay";
> };
>
> -&serial2 {
> +&mmuart3 {
> status = "okay";
> };
>
> -&serial3 {
> +&mmuart4 {
> status = "okay";
> };
>
> @@ -61,29 +70,32 @@ &mmc {
> bus-width = <4>;
> disable-wp;
> cap-sd-highspeed;
> + cap-mmc-highspeed;
> card-detect-delay = <200>;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
This looks unrelated to refactoring - new modes for MMC - and needs
separate change.
> sd-uhs-sdr12;
> sd-uhs-sdr25;
> sd-uhs-sdr50;
> sd-uhs-sdr104;
> };
>
> -&emac0 {
> +&mac0 {
> phy-mode = "sgmii";
> phy-handle = <&phy0>;
> - phy0: ethernet-phy@8 {
> - reg = <8>;
> - ti,fifo-depth = <0x01>;
> - };
> };
>
> -&emac1 {
> +&mac1 {
> status = "okay";
> phy-mode = "sgmii";
> phy-handle = <&phy1>;
> phy1: ethernet-phy@9 {
> reg = <9>;
> - ti,fifo-depth = <0x01>;
> + ti,fifo-depth = <0x1>;
> + };
> + phy0: ethernet-phy@8 {
> + reg = <8>;
> + ti,fifo-depth = <0x1>;
> };
> };
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index 808500be26c3..d311c5ea27c9 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> -/* Copyright (c) 2020 Microchip Technology Inc */
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>
> /dts-v1/;
> #include "dt-bindings/clock/microchip,mpfs-clock.h"
> @@ -16,7 +16,7 @@ cpus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> - cpu@0 {
> + cpu0: cpu@0 {
> compatible = "sifive,e51", "sifive,rocket0", "riscv";
> device_type = "cpu";
> i-cache-block-size = <64>;
> @@ -34,7 +34,7 @@ cpu0_intc: interrupt-controller {
> };
> };
>
> - cpu@1 {
> + cpu1: cpu@1 {
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -61,7 +61,7 @@ cpu1_intc: interrupt-controller {
> };
> };
>
> - cpu@2 {
> + cpu2: cpu@2 {
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -88,7 +88,7 @@ cpu2_intc: interrupt-controller {
> };
> };
>
> - cpu@3 {
> + cpu3: cpu@3 {
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -115,7 +115,7 @@ cpu3_intc: interrupt-controller {
> };
> };
>
> - cpu@4 {
> + cpu4: cpu@4 {
> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> d-cache-block-size = <64>;
> d-cache-sets = <64>;
> @@ -153,8 +153,9 @@ soc {
> compatible = "simple-bus";
> ranges;
>
> - cache-controller@2010000 {
> + cctrllr: cache-controller@2010000 {
> compatible = "sifive,fu540-c000-ccache", "cache";
> + reg = <0x0 0x2010000 0x0 0x1000>;
> cache-block-size = <64>;
> cache-level = <2>;
> cache-sets = <1024>;
> @@ -162,10 +163,9 @@ cache-controller@2010000 {
> cache-unified;
> interrupt-parent = <&plic>;
> interrupts = <1>, <2>, <3>;
> - reg = <0x0 0x2010000 0x0 0x1000>;
> };
>
> - clint@2000000 {
> + clint: clint@2000000 {
> compatible = "sifive,fu540-c000-clint", "sifive,clint0";
> reg = <0x0 0x2000000 0x0 0xC000>;
> interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>,
> @@ -198,15 +198,6 @@ plic: interrupt-controller@c000000 {
> riscv,ndev = <186>;
> };
>
> - dma@3000000 {
> - compatible = "sifive,fu540-c000-pdma";
Removal of nodes does not look like refactoring.
> - reg = <0x0 0x3000000 0x0 0x8000>;
> - interrupt-parent = <&plic>;
> - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
> - <30>;
> - #dma-cells = <1>;
> - };
> -
Best regards,
Krzysztof
On 17/12/2021 15:53, Krzysztof Kozlowski wrote:
> On 17/12/2021 10:33, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Add device tree bindings for the hardware rng device accessed via
>> the system services on the Microchip PolarFire SoC.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> .../bindings/rng/microchip,mpfs-rng.yaml | 29 +++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>> new file mode 100644
>> index 000000000000..32cbc37c9292
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>> @@ -0,0 +1,29 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Microchip MPFS random number generator
>> +
>> +maintainers:
>> + - Conor Dooley <[email protected]>
>> +
>> +description: |
>> + The hardware random number generator on the Polarfire SoC is
>> + accessed via the mailbox interface provided by the system controller
>> +
>> +properties:
>> + compatible:
>> + const: microchip,mpfs-rng
>> +
>> +required:
>> + - compatible
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + hwrandom: hwrandom {
>
> Three topics:
> 1. Node name (as most of others are using): rng
> 2. skip the label, not helping in example.
> 3. This looks very simple, so I wonder if the bindings are complete. No
> IO space/address... How is it going to be instantiated?
>
OK, now I saw the usage in DTS. I have doubts this makes sense as
separate bindings. It looks like integrated part of syscontroller, so
maybe make it part of that binding? Or at least add ref to syscontroller
bindings that such child is expected.
Best regards,
Krzysztof
On 17/12/2021 10:33, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Update the RISC-V/Microchip entry by adding the microchip dts
> directory and myself as maintainer
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7a2345ce8521..3b1d6be7bd56 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16348,8 +16348,10 @@ K: riscv
>
> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
> M: Lewis Hanly <[email protected]>
> +M: Conor Dooley <[email protected]>
> L: [email protected]
> S: Supported
> +F: arch/riscv/boot/dts/microchip/
> F: drivers/mailbox/mailbox-mpfs.c
> F: drivers/soc/microchip/
> F: include/soc/microchip/mpfs.h
>
Good to have the DTS covered, so FWIW:
Acked-by: Krzysztof Kozlowski <[email protected]>
You still should get Lewis' ack (unless he merges it)
Best regards,
Krzysztof
On 17/12/2021 15:07, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 17/12/2021 15:53, Krzysztof Kozlowski wrote:
>> On 17/12/2021 10:33, [email protected] wrote:
>>> From: Conor Dooley <[email protected]>
>>>
>>> Add device tree bindings for the hardware rng device accessed via
>>> the system services on the Microchip PolarFire SoC.
>>>
>>> Signed-off-by: Conor Dooley <[email protected]>
>>> ---
>>> .../bindings/rng/microchip,mpfs-rng.yaml | 29 +++++++++++++++++++
>>> 1 file changed, 29 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>> new file mode 100644
>>> index 000000000000..32cbc37c9292
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>> @@ -0,0 +1,29 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>> +
>>> +title: Microchip MPFS random number generator
>>> +
>>> +maintainers:
>>> + - Conor Dooley <[email protected]>
>>> +
>>> +description: |
>>> + The hardware random number generator on the Polarfire SoC is
>>> + accessed via the mailbox interface provided by the system controller
>>> +
>>> +properties:
>>> + compatible:
>>> + const: microchip,mpfs-rng
>>> +
>>> +required:
>>> + - compatible
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + hwrandom: hwrandom {
>>
>> Three topics:
>> 1. Node name (as most of others are using): rng
>> 2. skip the label, not helping in example.
>> 3. This looks very simple, so I wonder if the bindings are complete. No
>> IO space/address... How is it going to be instantiated?
>>
>
> OK, now I saw the usage in DTS. I have doubts this makes sense as
> separate bindings. It looks like integrated part of syscontroller, so
> maybe make it part of that binding? Or at least add ref to syscontroller
> bindings that such child is expected.
Acking the rest of this, re: adding the ref: is what is being done in
patch 03/17 insufficient?
>
>
> Best regards,
> Krzysztof
>
On 17/12/2021 15:04, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 17/12/2021 10:33, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Assorted minor changes to the MPFS/Icicle kit device tree:
>>
>> - rename serial to mmuart to match microchip documentation
>> - enable mmuart4 instead of mmuart0
>
> This is not refactoring. Refactoring could include renames,
> hierarchy/layout differences, naming, coding convention. You are
> changing features, e.g. using different UART. Please split the changes.
will do :)
>
>> - move stdout path to serial1 to avoid collision with
>> bootloader running on the e51
>> - split memory node to match updated fpga design
>> - move phy0 inside mac1 node to match phy configuration
>> - add labels where missing (cpus, cache controller)
>> - add missing address cells & interrupts to MACs
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> .../microchip/microchip-mpfs-icicle-kit.dts | 52 ++++++++------
>> .../boot/dts/microchip/microchip-mpfs.dtsi | 70 ++++++++++---------
>> 2 files changed, 68 insertions(+), 54 deletions(-)
>>
>> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> index 174f977c164b..f6542ef76046 100644
>> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> @@ -1,5 +1,5 @@
>> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> -/* Copyright (c) 2020 Microchip Technology Inc */
>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>>
>> /dts-v1/;
>>
>> @@ -13,25 +13,34 @@ / {
>> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
>>
>> aliases {
>> - ethernet0 = &emac1;
>> - serial0 = &serial0;
>> - serial1 = &serial1;
>> - serial2 = &serial2;
>> - serial3 = &serial3;
>> + ethernet0 = &mac1;
>> + serial0 = &mmuart0;
>> + serial1 = &mmuart1;
>> + serial2 = &mmuart2;
>> + serial3 = &mmuart3;
>> + serial4 = &mmuart4;
>> };
>>
>> chosen {
>> - stdout-path = "serial0:115200n8";
>> + stdout-path = "serial1:115200n8";
>> };
>>
>> cpus {
>> timebase-frequency = <RTCCLK_FREQ>;
>> };
>>
>> - memory@80000000 {
>> + ddrc_cache_lo: memory@80000000 {
>> device_type = "memory";
>> - reg = <0x0 0x80000000 0x0 0x40000000>;
>> + reg = <0x0 0x80000000 0x0 0x2e000000>;
>> clocks = <&clkcfg CLK_DDRC>;
>> + status = "okay";
>> + };
>> +
>> + ddrc_cache_hi: memory@1000000000 {
>
> This looks unrelated to refactoring - split of memory - and needs
> separate change.
>
>> + device_type = "memory";
>> + reg = <0x10 0x0 0x0 0x40000000>;
>> + clocks = <&clkcfg CLK_DDRC>;
>> + status = "okay";
>> };
>> };
>>
>> @@ -39,19 +48,19 @@ &refclk {
>> clock-frequency = <600000000>;
>> };
>>
>> -&serial0 {
>> +&mmuart1 {
>> status = "okay";
>> };
>>
>> -&serial1 {
>> +&mmuart2 {
>> status = "okay";
>> };
>>
>> -&serial2 {
>> +&mmuart3 {
>> status = "okay";
>> };
>>
>> -&serial3 {
>> +&mmuart4 {
>> status = "okay";
>> };
>>
>> @@ -61,29 +70,32 @@ &mmc {
>> bus-width = <4>;
>> disable-wp;
>> cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> card-detect-delay = <200>;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>
> This looks unrelated to refactoring - new modes for MMC - and needs
> separate change.
>
>> sd-uhs-sdr12;
>> sd-uhs-sdr25;
>> sd-uhs-sdr50;
>> sd-uhs-sdr104;
>> };
>>
>> -&emac0 {
>> +&mac0 {
>> phy-mode = "sgmii";
>> phy-handle = <&phy0>;
>> - phy0: ethernet-phy@8 {
>> - reg = <8>;
>> - ti,fifo-depth = <0x01>;
>> - };
>> };
>>
>> -&emac1 {
>> +&mac1 {
>> status = "okay";
>> phy-mode = "sgmii";
>> phy-handle = <&phy1>;
>> phy1: ethernet-phy@9 {
>> reg = <9>;
>> - ti,fifo-depth = <0x01>;
>> + ti,fifo-depth = <0x1>;
>> + };
>> + phy0: ethernet-phy@8 {
>> + reg = <8>;
>> + ti,fifo-depth = <0x1>;
>> };
>> };
>>
>> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> index 808500be26c3..d311c5ea27c9 100644
>> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> @@ -1,5 +1,5 @@
>> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> -/* Copyright (c) 2020 Microchip Technology Inc */
>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>>
>> /dts-v1/;
>> #include "dt-bindings/clock/microchip,mpfs-clock.h"
>> @@ -16,7 +16,7 @@ cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> - cpu@0 {
>> + cpu0: cpu@0 {
>> compatible = "sifive,e51", "sifive,rocket0", "riscv";
>> device_type = "cpu";
>> i-cache-block-size = <64>;
>> @@ -34,7 +34,7 @@ cpu0_intc: interrupt-controller {
>> };
>> };
>>
>> - cpu@1 {
>> + cpu1: cpu@1 {
>> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>> d-cache-block-size = <64>;
>> d-cache-sets = <64>;
>> @@ -61,7 +61,7 @@ cpu1_intc: interrupt-controller {
>> };
>> };
>>
>> - cpu@2 {
>> + cpu2: cpu@2 {
>> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>> d-cache-block-size = <64>;
>> d-cache-sets = <64>;
>> @@ -88,7 +88,7 @@ cpu2_intc: interrupt-controller {
>> };
>> };
>>
>> - cpu@3 {
>> + cpu3: cpu@3 {
>> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>> d-cache-block-size = <64>;
>> d-cache-sets = <64>;
>> @@ -115,7 +115,7 @@ cpu3_intc: interrupt-controller {
>> };
>> };
>>
>> - cpu@4 {
>> + cpu4: cpu@4 {
>> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>> d-cache-block-size = <64>;
>> d-cache-sets = <64>;
>> @@ -153,8 +153,9 @@ soc {
>> compatible = "simple-bus";
>> ranges;
>>
>> - cache-controller@2010000 {
>> + cctrllr: cache-controller@2010000 {
>> compatible = "sifive,fu540-c000-ccache", "cache";
>> + reg = <0x0 0x2010000 0x0 0x1000>;
>> cache-block-size = <64>;
>> cache-level = <2>;
>> cache-sets = <1024>;
>> @@ -162,10 +163,9 @@ cache-controller@2010000 {
>> cache-unified;
>> interrupt-parent = <&plic>;
>> interrupts = <1>, <2>, <3>;
>> - reg = <0x0 0x2010000 0x0 0x1000>;
>> };
>>
>> - clint@2000000 {
>> + clint: clint@2000000 {
>> compatible = "sifive,fu540-c000-clint", "sifive,clint0";
>> reg = <0x0 0x2000000 0x0 0xC000>;
>> interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>,
>> @@ -198,15 +198,6 @@ plic: interrupt-controller@c000000 {
>> riscv,ndev = <186>;
>> };
>>
>> - dma@3000000 {
>> - compatible = "sifive,fu540-c000-pdma";
>
> Removal of nodes does not look like refactoring.
>
>> - reg = <0x0 0x3000000 0x0 0x8000>;
>> - interrupt-parent = <&plic>;
>> - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
>> - <30>;
>> - #dma-cells = <1>;
>> - };
>> -
>
>
> Best regards,
> Krzysztof
>
On 17/12/2021 13:43, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Fri, Dec 17, 2021 at 10:33 AM <[email protected]> wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Split the device tree for the Microchip MPFS into two sections by adding
>> microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
>> FPGA fabric.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>
> Thanks for your patch!
>
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>> +
>> +/ {
>> + corePWM0: pwm@41000000 {
>> + compatible = "microchip,corepwm";
>> + reg = <0x0 0x41000000 0x0 0xF0>;
>> + microchip,sync-update = /bits/ 8 <0>;
>> + #pwm-cells = <2>;
>> + clocks = <&clkcfg CLK_FIC3>;
>> + status = "disabled";
>> + };
>
> I'm wondering if these should be grouped under a "fabric" subnode,
> like we have an "soc" subnode for on-SoC devices? Rob?
>
> BTW, do you already have a naming plan for different revisions of
> FPGA fabric cores?
Not yet (assuming you mean specifically how we will handle it in the
device tree) - although i was talking to someone about it yesterday.
It's possible that we might handle that via a register, but if you have
a suggestion or some precedence that you're aware of that would be useful.
The actual naming convention of the IP cores themselves, yeah. I will
dig it up for you on Monday.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
On 17/12/2021 16:22, [email protected] wrote:
> On 17/12/2021 15:07, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 17/12/2021 15:53, Krzysztof Kozlowski wrote:
>>> On 17/12/2021 10:33, [email protected] wrote:
>>>> From: Conor Dooley <[email protected]>
>>>>
>>>> Add device tree bindings for the hardware rng device accessed via
>>>> the system services on the Microchip PolarFire SoC.
>>>>
>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>> ---
>>>> .../bindings/rng/microchip,mpfs-rng.yaml | 29 +++++++++++++++++++
>>>> 1 file changed, 29 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>> new file mode 100644
>>>> index 000000000000..32cbc37c9292
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>> @@ -0,0 +1,29 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>>> +
>>>> +title: Microchip MPFS random number generator
>>>> +
>>>> +maintainers:
>>>> + - Conor Dooley <[email protected]>
>>>> +
>>>> +description: |
>>>> + The hardware random number generator on the Polarfire SoC is
>>>> + accessed via the mailbox interface provided by the system controller
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: microchip,mpfs-rng
>>>> +
>>>> +required:
>>>> + - compatible
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> + - |
>>>> + hwrandom: hwrandom {
>>>
>>> Three topics:
>>> 1. Node name (as most of others are using): rng
>>> 2. skip the label, not helping in example.
>>> 3. This looks very simple, so I wonder if the bindings are complete. No
>>> IO space/address... How is it going to be instantiated?
>>>
>>
>> OK, now I saw the usage in DTS. I have doubts this makes sense as
>> separate bindings. It looks like integrated part of syscontroller, so
>> maybe make it part of that binding? Or at least add ref to syscontroller
>> bindings that such child is expected.
> Acking the rest of this, re: adding the ref: is what is being done in
> patch 03/17 insufficient?
Ops, I missed the 03/17. Yeah, it looks it is sufficient and in such
case I think you do not need this patch. The compatible is documented in
03/17. The same for sysserv.
Best regards,
Krzysztof
Hi Conor,
On Fri, Dec 17, 2021 at 4:32 PM <[email protected]> wrote:
> On 17/12/2021 13:43, Geert Uytterhoeven wrote:
> > On Fri, Dec 17, 2021 at 10:33 AM <[email protected]> wrote:
> >> From: Conor Dooley <[email protected]>
> >>
> >> Split the device tree for the Microchip MPFS into two sections by adding
> >> microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
> >> FPGA fabric.
> >>
> >> Signed-off-by: Conor Dooley <[email protected]>
> >
> > Thanks for your patch!
> >
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> >> @@ -0,0 +1,13 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> >> +
> >> +/ {
> >> + corePWM0: pwm@41000000 {
> >> + compatible = "microchip,corepwm";
> >> + reg = <0x0 0x41000000 0x0 0xF0>;
> >> + microchip,sync-update = /bits/ 8 <0>;
> >> + #pwm-cells = <2>;
> >> + clocks = <&clkcfg CLK_FIC3>;
> >> + status = "disabled";
> >> + };
> >
> > I'm wondering if these should be grouped under a "fabric" subnode,
> > like we have an "soc" subnode for on-SoC devices? Rob?
> >
> > BTW, do you already have a naming plan for different revisions of
> > FPGA fabric cores?
> Not yet (assuming you mean specifically how we will handle it in the
> device tree) - although i was talking to someone about it yesterday.
> It's possible that we might handle that via a register, but if you have
> a suggestion or some precedence that you're aware of that would be useful.
>
> The actual naming convention of the IP cores themselves, yeah. I will
> dig it up for you on Monday.
I meant what if corepwm is enhanced, and how to detect that?
SiFive uses an integer version number, even for hard cores[1].
OpenCores uses an "-rtlsvnN" suffix (isn't svn dead? ;-)
No idea what e.g. LiteX and Microwatt are planning.
[1] Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Friday, December 17th, 2021 at 15:47, Krzysztof Kozlowski <[email protected]> wrote:
> On 17/12/2021 16:22, [email protected] wrote:
>
> > On 17/12/2021 15:07, Krzysztof Kozlowski wrote:
> >
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > On 17/12/2021 15:53, Krzysztof Kozlowski wrote:
> > >
> > > > On 17/12/2021 10:33, [email protected] wrote:
> > > >
> > > > > From: Conor Dooley [email protected]
> > > > >
> > > > > Add device tree bindings for the hardware rng device accessed via
> > > > >
> > > > > the system services on the Microchip PolarFire SoC.
> > > > >
> > > > > Signed-off-by: Conor Dooley [email protected]
> > > > > ------------------------------------------------------
> > > >
> > > > Three topics:
> > > >
> > > > 1. Node name (as most of others are using): rng
> > > > 2. skip the label, not helping in example.
> > > > 3. This looks very simple, so I wonder if the bindings are complete. No
> > > >
> > > > IO space/address... How is it going to be instantiated?
> > > OK, now I saw the usage in DTS. I have doubts this makes sense as
> > > separate bindings. It looks like integrated part of syscontroller, so
> > > maybe make it part of that binding? Or at least add ref to syscontroller
> > > bindings that such child is expected.
> > Acking the rest of this, re: adding the ref: is what is being done in
> > patch 03/17 insufficient?
> Ops, I missed the 03/17. Yeah, it looks it is sufficient and in such
> case I think you do not need this patch. The compatible is documented in
> 03/17. The same for sysserv.
Grand, that makes things easier.
Conor.
>
> Best regards,
>
> Krzysztof
>
> linux-riscv mailing list
>
> [email protected]
>
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On 17/12/2021 11:43, Mark Brown wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
know the content is safe
>
> On Fri, Dec 17, 2021 at 11:40:29AM +0000, [email protected]
wrote:
>> On 17/12/2021 11:17, Mark Brown wrote:
>>> Why do you need this property in the DT - isn't the number of chip
>>> selects in the IP a fixes property?
>>
>> Nope! It's an IP that's intended for use in FPGAs so the number of
>> selects may (and does) vary based on implementation.
>
> That doesn't explain why the number is needed in the binding - why do
> you need this property in the DT?
Took another look at the IP core configuration & I think you're right
and that property can be dropped. The register responsible for CS
control will not be optimised away even if the CS is not used & the
worst outcome is that nothing will happen.
On Fri, Dec 17, 2021 at 09:33:15AM +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>
> ---
> .../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>
> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> new file mode 100644
> index 000000000000..d57460cbe5e3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> +
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> +
> +allOf:
> + - $ref: rtc.yaml#
> +
> +maintainers:
> + - Daire McNamara <[email protected]>
> + - Lewis Hanly <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-rtc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 2
Need to define what each one is.
> +
> + microchip,prescaler:
> + description: |
> + The prescaler divides the input frequency to create a time-based strobe (typically 1 Hz) for
> + the calendar counter. The Alarm and Compare Registers, in conjunction with the calendar
> + counter, facilitate time-matched events. To properly operate in Calendar or Binary mode,
> + the 26-bit prescaler must be programmed to generate a strobe to the RTC.
> + maxItems: 1
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: rtc
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/microchip,mpfs-clock.h>
> + rtc@20124000 {
> + compatible = "microchip,mpfs-rtc";
> + reg = <0x20124000 0x1000>;
> + clocks = <&clkcfg CLK_RTC>;
> + clock-names = "rtc";
> + interrupts = <80>, <81>;
> + };
> +...
> --
> 2.33.1
>
>
On Fri, Dec 17, 2021 at 09:33:19AM +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the usb controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/usb/microchip,mpfs-musb.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
> new file mode 100644
> index 000000000000..eec918046c73
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS USB Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-musb
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 2
> + maxItems: 2
> +
> + interrupt-names:
> + items:
> + - const: dma
> + - const: mc
> +
> + clocks:
> + maxItems: 1
> +
> + dr_mode:
> + enum:
> + - host
> + - otg
> + - peripheral
Reference usb-drd.yaml and you can drop this.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - dr_mode
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + usb: usb@20201000 {
Drop unused labels.
> + compatible = "microchip,mpfs-musb";
> + reg = <0x20201000 0x1000>;
> + clocks = <&clkcfg CLK_USB>;
> + interrupt-parent = <&plic>;
> + interrupts = <86>, <87>;
> + interrupt-names = "dma","mc";
space ^
> + dr_mode = "host";
> + };
> +
> +...
> --
> 2.33.1
>
>
On Fri, 17 Dec 2021 09:33:09 +0000, [email protected] wrote:
> From: Ivan Griffin <[email protected]>
>
> Provide named identifiers for device tree for RISC-V interrupts.
>
> Licensed under GPL and MIT, as this file may be useful to any OS that
> uses device tree.
>
> Signed-off-by: Ivan Griffin <[email protected]>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
>
Acked-by: Rob Herring <[email protected]>
On Fri, Dec 17, 2021 at 09:33:11AM +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Make the system controller on the Polarfire SoC
> a "simple,mfd" so that the services can be child
> nodes of the system controller node.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../microchip,mpfs-sys-controller.yaml | 33 +++++++++++++++++--
> 1 file changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> index f699772fedf3..014cb44b8f31 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
> @@ -13,13 +13,34 @@ description: |
> The PolarFire SoC system controller is communicated with via a mailbox.
> This document describes the bindings for the client portion of that mailbox.
>
> -
> properties:
> mboxes:
> maxItems: 1
>
> compatible:
> - const: microchip,mpfs-sys-controller
> + items:
> + - const: microchip,mpfs-sys-controller
> + - const: simple-mfd
'simple-mfd' means there is zero dependency on the parent for the child
nodes. Isn't 'mboxes' a dependency?
> +
> + hwrandom:
> + type: object
> +
> + properties:
> + compatible:
> + const: microchip,mpfs-rng
> +
> + required:
> + - compatible
> +
> + sysserv:
> + type: object
> +
> + properties:
> + compatible:
> + const: microchip,mpfs-generic-service
> +
> + required:
> + - compatible
There's not really any need to have child nodes which have no resources.
The driver for microchip,mpfs-sys-controller can create child devices.
Rob
On Tuesday, December 21st, 2021 at 17:55, Rob Herring <[email protected]> wrote:
>On Fri, Dec 17, 2021 at 09:33:11AM +0000, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Make the system controller on the Polarfire SoC
>> a "simple,mfd" so that the services can be child
>> nodes of the system controller node.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> .../microchip,mpfs-sys-controller.yaml | 33 +++++++++++++++++--
>> 1 file changed, 30 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/>Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>> index f699772fedf3..014cb44b8f31 100644
>> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
>> @@ -13,13 +13,34 @@ description: |
>> The PolarFire SoC system controller is communicated with via a mailbox.
>> This document describes the bindings for the client portion of that mailbox.
>>
>> -
>> properties:
>> mboxes:
>> maxItems: 1
>>
>> compatible:
>> - const: microchip,mpfs-sys-controller
>> + items:
>> + - const: microchip,mpfs-sys-controller
>> + - const: simple-mfd
>
>'simple-mfd' means there is zero dependency on the parent for the child
>nodes. Isn't 'mboxes' a dependency?
I suppose it is. I was going off what had been done for the bcm2835
firmware for the rpi its also a mailbox providing "services".
(arm/bcm/raspberrypi,bcm2835-firmware.yaml)
>
>> +
>> + hwrandom:
>> + type: object
>> +
>> + properties:
>> + compatible:
>> + const: microchip,mpfs-rng
>> +
>> + required:
>> + - compatible
>> +
>> + sysserv:
>> + type: object
>> +
>> + properties:
>> + compatible:
>> + const: microchip,mpfs-generic-service
>> +
>> + required:
>> + - compatible
>
>There's not really any need to have child nodes which have no resources.
>The driver for microchip,mpfs-sys-controller can create child devices.
I am assuming by this you mean say, take a list of boolean properties and
convert those into child devices? There's a fairly decent number of services
provided by the system controller and these children just represent the
subset that we've implemented so far.
Conor
>
>Rob
On 17/12/2021 15:09, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 17/12/2021 10:33, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Update the RISC-V/Microchip entry by adding the microchip dts
>> directory and myself as maintainer
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> MAINTAINERS | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 7a2345ce8521..3b1d6be7bd56 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -16348,8 +16348,10 @@ K: riscv
>>
>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>> M: Lewis Hanly <[email protected]>
>> +M: Conor Dooley <[email protected]>
>> L: [email protected]
>> S: Supported
>> +F: arch/riscv/boot/dts/microchip/
>> F: drivers/mailbox/mailbox-mpfs.c
>> F: drivers/soc/microchip/
>> F: include/soc/microchip/mpfs.h
>>
>
> Good to have the DTS covered, so FWIW:
> Acked-by: Krzysztof Kozlowski <[email protected]>
>
> You still should get Lewis' ack (unless he merges it)
Aye, it'll be an ack. We don't currently have a tree & would rather do
this via risc-v than the at91/sam arm soc tree.
>
> Best regards,
> Krzysztof
>
On Thu, 23 Dec 2021 06:56:45 PST (-0800), [email protected] wrote:
> On 17/12/2021 15:09, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 17/12/2021 10:33, [email protected] wrote:
>>> From: Conor Dooley <[email protected]>
>>>
>>> Update the RISC-V/Microchip entry by adding the microchip dts
>>> directory and myself as maintainer
>>>
>>> Signed-off-by: Conor Dooley <[email protected]>
>>> ---
>>> MAINTAINERS | 2 ++
>>> 1 file changed, 2 insertions(+)
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 7a2345ce8521..3b1d6be7bd56 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -16348,8 +16348,10 @@ K: riscv
>>>
>>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>>> M: Lewis Hanly <[email protected]>
>>> +M: Conor Dooley <[email protected]>
>>> L: [email protected]
>>> S: Supported
>>> +F: arch/riscv/boot/dts/microchip/
>>> F: drivers/mailbox/mailbox-mpfs.c
>>> F: drivers/soc/microchip/
>>> F: include/soc/microchip/mpfs.h
>>>
>>
>> Good to have the DTS covered, so FWIW:
>> Acked-by: Krzysztof Kozlowski <[email protected]>
>>
>> You still should get Lewis' ack (unless he merges it)
> Aye, it'll be an ack. We don't currently have a tree & would rather do
> this via risc-v than the at91/sam arm soc tree.
WFM. I'll be awaiting the ack. I don't see any fundamental issues from
my end, as long is it's got all the acks/reviews then I'm generally fine
with this sort of stuff. I'll take a look before merging it, I'm kind
of buried right now. Sorry!
>>
>> Best regards,
>> Krzysztof
>>
>
On 17/12/2021 16:00, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Fri, Dec 17, 2021 at 4:32 PM <[email protected]> wrote:
>> On 17/12/2021 13:43, Geert Uytterhoeven wrote:
>>> On Fri, Dec 17, 2021 at 10:33 AM <[email protected]> wrote:
>>>> From: Conor Dooley <[email protected]>
>>>>
>>>> Split the device tree for the Microchip MPFS into two sections by adding
>>>> microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
>>>> FPGA fabric.
>>>>
>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>
>>> Thanks for your patch!
>>>
>>>> --- /dev/null
>>>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>>> @@ -0,0 +1,13 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>>>> +
>>>> +/ {
>>>> + corePWM0: pwm@41000000 {
>>>> + compatible = "microchip,corepwm";
>>>> + reg = <0x0 0x41000000 0x0 0xF0>;
>>>> + microchip,sync-update = /bits/ 8 <0>;
>>>> + #pwm-cells = <2>;
>>>> + clocks = <&clkcfg CLK_FIC3>;
>>>> + status = "disabled";
>>>> + };
>>>
>>> I'm wondering if these should be grouped under a "fabric" subnode,
>>> like we have an "soc" subnode for on-SoC devices? Rob?
>>>
>>> BTW, do you already have a naming plan for different revisions of
>>> FPGA fabric cores?
>> Not yet (assuming you mean specifically how we will handle it in the
>> device tree) - although i was talking to someone about it yesterday.
>> It's possible that we might handle that via a register, but if you have
>> a suggestion or some precedence that you're aware of that would be useful.
>>
>> The actual naming convention of the IP cores themselves, yeah. I will
>> dig it up for you on Monday.
>
> I meant what if corepwm is enhanced, and how to detect that?
>
Looks like "microchip,core<name>-N" is the plan. More recent IP cores
have a register from which the version number can be read but that isnt
(and wont be) the case for all versions.
Where this register does exist, we will use it & if not fall back onto
the compat. string.
> SiFive uses an integer version number, even for hard cores[1].
> OpenCores uses an "-rtlsvnN" suffix (isn't svn dead? ;-)
At least here, "hardware" people seem to be a fan of it still (sadly?)
> No idea what e.g. LiteX and Microwatt are planning. >
> [1] Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt
>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
On 17/12/2021 15:09, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know
> the content is safe
>
> On 17/12/2021 10:33, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Update the RISC-V/Microchip entry by adding the microchip dts
>> directory and myself as maintainer
>>
>> Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Lewis Hanly <[email protected]>
>> ---
>> MAINTAINERS | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS index
>> 7a2345ce8521..3b1d6be7bd56 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -16348,8 +16348,10 @@ K: riscv
>>
>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
>> M: Lewis Hanly <[email protected]>
>> +M: Conor Dooley <[email protected]>
>> L: [email protected]
>> S: Supported
>> +F: arch/riscv/boot/dts/microchip/
>> F: drivers/mailbox/mailbox-mpfs.c
>> F: drivers/soc/microchip/
>> F: include/soc/microchip/mpfs.h
>>
>
> Good to have the DTS covered, so FWIW:
> Acked-by: Krzysztof Kozlowski <[email protected]>
>
> You still should get Lewis' ack (unless he merges it)
Aye, it'll be an ack. We don't currently have a tree & would rather do this via risc-v than the at91/sam arm soc tree.
>
> Best regards,
> Krzysztof
>