The following patchset adds async hashing (sha1 and hmac-sha1) to the
mv_cesa crypto driver. This driver utilizes the Marvell CESA crypto
accelerator that exists in some Marvell CPU's (Orion and Kirkwood). The
existing driver has AES crypto support.
Compared to SW hashing on a 1.2GHz Kirkwood, the HW acceleration is
about 20% faster, but more importantly, at nearly 0% CPU utilization.
The patchset is divided as follows:
- patches 1-4 are bug/warning fixes to the existing driver
- patches 5-9 refactor the exisintg driver with no functional change to
accommodate the added functionality
- patch 10 adds the sha1 and hmac-sha1 support.
The driver requires the sha1 and hmac sw drivers in order to handle some
corner cases (i.e. it never falls back on a complete request but
sometimes it hashes the last 64 bytes in sw)