This patch series adds i.MX6 support to the Freescale CAAM driver.
Modifications include:
- explicit cache coherency support in the driver
- register I/O primitive support
- scatter/gather entry modifications
- clocking support
- i.MX6 device tree support for CAAM
- DMA fixes
These patches have been tested on the i.MX6 and regression tested
on QorIQ platforms. These patches include changes based on responses
to the original RFC.
arch/arm/boot/dts/imx6qdl.dtsi | 30 ++++-
arch/arm/boot/dts/imx6sx.dtsi | 29 +++++
arch/arm/configs/imx_v6_v7_defconfig | 3 +-
drivers/clk/imx/clk-imx6q.c | 3 +
drivers/crypto/caam/Kconfig | 2 +-
drivers/crypto/caam/caamalg.c | 20 +--
drivers/crypto/caam/caamhash.c | 29 +++--
drivers/crypto/caam/caamrng.c | 4 +
drivers/crypto/caam/compat.h | 1 +
drivers/crypto/caam/ctrl.c | 197 +++++++++++++++++++++++++++++-
drivers/crypto/caam/desc.h | 25 +++-
drivers/crypto/caam/intern.h | 5 +
drivers/crypto/caam/jr.c | 18 +++
drivers/crypto/caam/regs.h | 23 ++++
drivers/crypto/caam/sg_sw_sec4.h | 25 ++--
include/dt-bindings/clock/imx6qdl-clock.h | 5 +-
16 files changed, 371 insertions(+), 48 deletions(-)
--
2.1.4
Freescale i.MX6 ARM platforms do not support hardware cache coherency.
This patch adds cache coherency support to the CAAM driver.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/caamhash.c | 2 +-
drivers/crypto/caam/caamrng.c | 4 ++++
drivers/crypto/caam/jr.c | 18 ++++++++++++++++++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index dae1e80..9622a81 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -127,7 +127,7 @@ struct caam_hash_state {
int buflen_0;
u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
int buflen_1;
- u8 caam_ctx[MAX_CTX_LEN];
+ u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
int (*update)(struct ahash_request *req);
int (*final)(struct ahash_request *req);
int (*finup)(struct ahash_request *req);
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 5095337..a1d21d5 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -108,6 +108,10 @@ static void rng_done(struct device *jrdev, u32 *desc, u32 err, void *context)
atomic_set(&bd->empty, BUF_NOT_EMPTY);
complete(&bd->filled);
+
+ /* Buffer refilled, invalidate cache */
+ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE);
+
#ifdef DEBUG
print_hex_dump(KERN_ERR, "rng refreshed buf@: ",
DUMP_PREFIX_ADDRESS, 16, 4, bd->buf, RN_BUF_SIZE, 1);
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index b8b5d47..b7ec1ad 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -202,6 +202,13 @@ static void caam_jr_dequeue(unsigned long devarg)
userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
userstatus = jrp->outring[hw_idx].jrstatus;
+ /*
+ * Make sure all information from the job has been obtained
+ * before telling CAAM that the job has been removed from the
+ * output ring.
+ */
+ mb();
+
/* set done */
wr_reg32(&jrp->rregs->outring_rmvd, 1);
@@ -351,12 +358,23 @@ int caam_jr_enqueue(struct device *dev, u32 *desc,
jrp->inpring[jrp->inp_ring_write_index] = desc_dma;
+ /*
+ * Guarantee that the descriptor's DMA address has been written to
+ * the next slot in the ring before the write index is updated, since
+ * other cores may update this index independently.
+ */
smp_wmb();
jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) &
(JOBR_DEPTH - 1);
jrp->head = (head + 1) & (JOBR_DEPTH - 1);
+ /*
+ * Ensure that all job information has been written before
+ * notifying CAAM that a new job was added to the input ring.
+ */
+ wmb();
+
wr_reg32(&jrp->rregs->inpring_jobadd, 1);
spin_unlock_bh(&jrp->inplock);
--
2.1.4
From: Steve Cornelius <[email protected]>
Allow CAAM to be selected in the kernel for Freescale i.MX devices if
ARCH_MXC is enabled.
Signed-off-by: Steve Cornelius <[email protected]>
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig
index e286e28..66ef0c0 100644
--- a/drivers/crypto/caam/Kconfig
+++ b/drivers/crypto/caam/Kconfig
@@ -1,6 +1,6 @@
config CRYPTO_DEV_FSL_CAAM
tristate "Freescale CAAM-Multicore driver backend"
- depends on FSL_SOC
+ depends on FSL_SOC || ARCH_MXC
help
Enables the driver module for Freescale's Cryptographic Accelerator
and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
--
2.1.4
Add set/clear 32-bit primitives for compatibility with ARM devices since
the primitives were previously only defined for the Power architecture.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/ctrl.c | 6 +++---
drivers/crypto/caam/regs.h | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 1891809..660cc3e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -445,9 +445,9 @@ static int caam_probe(struct platform_device *pdev)
* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
* long pointers in master configuration register
*/
- clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
- MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
- MCFGR_LONG_PTR : 0));
+ clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
+ MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
+ MCFGR_LONG_PTR : 0));
/*
* Read the Compile Time paramters and SCFGR to determine
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 5e64352..3a2a788 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -65,9 +65,31 @@
*
*/
+#ifdef CONFIG_ARM
+/* These are common macros for Power, put here for ARM */
+#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
+#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
+
+#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v) out_arch(l, le32, a, v)
+#define in_le32(a) in_arch(l, le32, a)
+
+#define out_be32(a, v) out_arch(l, be32, a, v)
+#define in_be32(a) in_arch(l, be32, a)
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+#endif
+
#ifdef __BIG_ENDIAN
#define wr_reg32(reg, data) out_be32(reg, data)
#define rd_reg32(reg) in_be32(reg)
+#define clrsetbits_32(addr, clear, set) clrsetbits_be32(addr, clear, set)
#ifdef CONFIG_64BIT
#define wr_reg64(reg, data) out_be64(reg, data)
#define rd_reg64(reg) in_be64(reg)
@@ -76,6 +98,7 @@
#ifdef __LITTLE_ENDIAN
#define wr_reg32(reg, data) __raw_writel(data, reg)
#define rd_reg32(reg) __raw_readl(reg)
+#define clrsetbits_32(addr, clear, set) clrsetbits_le32(addr, clear, set)
#ifdef CONFIG_64BIT
#define wr_reg64(reg, data) __raw_writeq(data, reg)
#define rd_reg64(reg) __raw_readq(reg)
--
2.1.4
Select CAAM for i.MX6 devices.
Signed-off-by: Victoria Milhoan <[email protected]>
---
arch/arm/configs/imx_v6_v7_defconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index b47863d..7569b39 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -354,8 +354,7 @@ CONFIG_PROVE_LOCKING=y
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_SECURITYFS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
CONFIG_CRC_CCITT=m
CONFIG_CRC_T10DIF=y
CONFIG_CRC7=m
--
2.1.4
This change fixes:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 456 at lib/dma-debug.c:1103 check_unmap+0x438/0x958()
caam_jr 2101000.jr0: DMA-API: device driver frees DMA memory with different size [device address=0x000000003a241080] [map ]
Modules linked in: tcrypt(+)
CPU: 0 PID: 456 Comm: insmod Not tainted 4.1.0-248766-gf823586-dirty #82
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[<80015e0c>] (unwind_backtrace) from [<80012764>] (show_stack+0x10/0x14)
[<80012764>] (show_stack) from [<806df8e8>] (dump_stack+0x84/0xc4)
[<806df8e8>] (dump_stack) from [<800266fc>] (warn_slowpath_common+0x84/0xb4)
[<800266fc>] (warn_slowpath_common) from [<8002675c>] (warn_slowpath_fmt+0x30/0x40)
[<8002675c>] (warn_slowpath_fmt) from [<802c7db8>] (check_unmap+0x438/0x958)
[<802c7db8>] (check_unmap) from [<802c835c>] (debug_dma_unmap_page+0x84/0x8c)
[<802c835c>] (debug_dma_unmap_page) from [<804d3b94>] (ahash_update_ctx+0xb08/0xec4)
[<804d3b94>] (ahash_update_ctx) from [<7f002984>] (test_ahash_pnum.isra.9.constprop.19+0x2b8/0x514 [tcrypt])
[<7f002984>] (test_ahash_pnum.isra.9.constprop.19 [tcrypt]) from [<7f005998>] (do_test+0x2db8/0x37cc [tcrypt])
[<7f005998>] (do_test [tcrypt]) from [<7f00b050>] (tcrypt_mod_init+0x50/0x9c [tcrypt])
[<7f00b050>] (tcrypt_mod_init [tcrypt]) from [<80009730>] (do_one_initcall+0x8c/0x1d4)
[<80009730>] (do_one_initcall) from [<806dda4c>] (do_init_module+0x5c/0x1a8)
[<806dda4c>] (do_init_module) from [<80085308>] (load_module+0x17e0/0x1da0)
[<80085308>] (load_module) from [<80085998>] (SyS_init_module+0xd0/0x120)
[<80085998>] (SyS_init_module) from [<8000f4c0>] (ret_fast_syscall+0x0/0x3c)
---[ end trace 60807cfb6521c79f ]---
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/caamhash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 2361beb..16c03f8 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -829,7 +829,7 @@ static int ahash_update_ctx(struct ahash_request *req)
state->buf_dma = try_buf_map_to_sec4_sg(jrdev,
edesc->sec4_sg + 1,
buf, state->buf_dma,
- *buflen, last_buflen);
+ *next_buflen, *buflen);
if (src_nents) {
src_map_to_sec4_sg(jrdev, req->src, src_nents,
--
2.1.4
Add CAAM device node to the i.MX6 device tree.
Signed-off-by: Victoria Milhoan <[email protected]>
---
arch/arm/boot/dts/imx6qdl.dtsi | 30 ++++++++++++++++++++++++++----
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e6d1359..4df9f1e 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -836,10 +836,32 @@
reg = <0x02100000 0x100000>;
ranges;
- caam@02100000 {
- reg = <0x02100000 0x40000>;
- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
- <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ crypto: caam@2100000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2100000 0x10000>;
+ ranges = <0 0x2100000 0x10000>;
+ interrupt-parent = <&intc>;
+ clocks = <&clks IMX6QDL_CAAM_MEM>,
+ <&clks IMX6QDL_CAAM_ACLK>,
+ <&clks IMX6QDL_CAAM_IPG>,
+ <&clks IMX6QDL_CLK_EIM_SLOW>;
+ clock-names = "caam_mem", "caam_aclk",
+ "caam_ipg", "caam_emi_slow";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
aipstz@0217c000 { /* AIPSTZ2 */
--
2.1.4
Avoid moving the head of the scatterlist entry by using temporary
pointers to walk the scatterlist.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/sg_sw_sec4.h | 24 +++++++++++++++++-------
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h
index 711bb39..18cd6d1 100644
--- a/drivers/crypto/caam/sg_sw_sec4.h
+++ b/drivers/crypto/caam/sg_sw_sec4.h
@@ -105,9 +105,15 @@ static inline void dma_unmap_sg_chained(
{
if (unlikely(chained)) {
int i;
+ struct scatterlist *tsg = sg;
+
+ /*
+ * Use a local copy of the sg pointer to avoid moving the
+ * head of the list pointed to by sg as we walk the list.
+ */
for (i = 0; i < nents; i++) {
- dma_unmap_sg(dev, sg, 1, dir);
- sg = sg_next(sg);
+ dma_unmap_sg(dev, tsg, 1, dir);
+ tsg = sg_next(tsg);
}
} else if (nents) {
dma_unmap_sg(dev, sg, nents, dir);
@@ -118,19 +124,23 @@ static inline int dma_map_sg_chained(
struct device *dev, struct scatterlist *sg, unsigned int nents,
enum dma_data_direction dir, bool chained)
{
- struct scatterlist *first = sg;
-
if (unlikely(chained)) {
int i;
+ struct scatterlist *tsg = sg;
+
+ /*
+ * Use a local copy of the sg pointer to avoid moving the
+ * head of the list pointed to by sg as we walk the list.
+ */
for (i = 0; i < nents; i++) {
- if (!dma_map_sg(dev, sg, 1, dir)) {
- dma_unmap_sg_chained(dev, first, i, dir,
+ if (!dma_map_sg(dev, tsg, 1, dir)) {
+ dma_unmap_sg_chained(dev, sg, i, dir,
chained);
nents = 0;
break;
}
- sg = sg_next(sg);
+ tsg = sg_next(tsg);
}
} else
nents = dma_map_sg(dev, sg, nents, dir);
--
2.1.4
Since fields must be ORed in to operate correctly using any order of
operations, changed allocations of the combination of extended
descriptor structs + hardware scatterlists to use kzalloc() instead
of kmalloc(), so as to ensure that residue data would not be ORed in
with the correct data.
Signed-off-by: Steve Cornelius <[email protected]>
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/caamalg.c | 20 ++++++++++----------
drivers/crypto/caam/caamhash.c | 25 ++++++++++++-------------
2 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 3c50a50..33b6861 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2482,8 +2482,8 @@ static struct aead_edesc *old_aead_edesc_alloc(struct aead_request *req,
sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
@@ -2585,8 +2585,8 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
@@ -2921,8 +2921,8 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
@@ -3094,8 +3094,8 @@ static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
@@ -3273,8 +3273,8 @@ static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc(
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(*edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 9622a81..2361beb 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -807,7 +807,7 @@ static int ahash_update_ctx(struct ahash_request *req)
* allocate space for base edesc and hw desc commands,
* link tables
*/
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
sec4_sg_bytes, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev,
@@ -918,8 +918,8 @@ static int ahash_final_ctx(struct ahash_request *req)
sec4_sg_bytes = (1 + (buflen ? 1 : 0)) * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1005,8 +1005,8 @@ static int ahash_finup_ctx(struct ahash_request *req)
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1091,8 +1091,8 @@ static int ahash_digest(struct ahash_request *req)
sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
- DESC_JOB_IO_LEN, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + sec4_sg_bytes + DESC_JOB_IO_LEN,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1165,8 +1165,7 @@ static int ahash_final_no_ctx(struct ahash_request *req)
int sh_len;
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
- GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1245,7 +1244,7 @@ static int ahash_update_no_ctx(struct ahash_request *req)
* allocate space for base edesc and hw desc commands,
* link tables
*/
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
sec4_sg_bytes, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev,
@@ -1353,8 +1352,8 @@ static int ahash_finup_no_ctx(struct ahash_request *req)
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1448,7 +1447,7 @@ static int ahash_update_first(struct ahash_request *req)
* allocate space for base edesc and hw desc commands,
* link tables
*/
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
sec4_sg_bytes, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev,
--
2.1.4
Add CAAM device node to the i.MX6SX device tree.
Signed-off-by: Victoria Milhoan <[email protected]>
---
arch/arm/boot/dts/imx6sx.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 708175d..c73cee4 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -738,6 +738,35 @@
reg = <0x02100000 0x100000>;
ranges;
+ crypto: caam@2100000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2100000 0x10000>;
+ ranges = <0 0x2100000 0x10000>;
+ interrupt-parent = <&intc>;
+ clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
+ <&clks IMX6SX_CLK_CAAM_ACLK>,
+ <&clks IMX6SX_CLK_CAAM_IPG>,
+ <&clks IMX6SX_CLK_EIM_SLOW>;
+ clock-names = "caam_mem", "caam_aclk",
+ "caam_ipg", "caam_emi_slow";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <0 106 0x4>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usbotg1: usb@02184000 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
--
2.1.4
ARM-based systems may disable clocking to the CAAM device on the
Freescale i.MX platform for power management purposes. This patch
enables the required clocks when the CAAM module is initialized and
disables the required clocks when the CAAM module is shut down.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/compat.h | 1 +
drivers/crypto/caam/ctrl.c | 191 +++++++++++++++++++++++++++++++++++++++++++
drivers/crypto/caam/intern.h | 5 ++
3 files changed, 197 insertions(+)
diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h
index f57f395..b6955ec 100644
--- a/drivers/crypto/caam/compat.h
+++ b/drivers/crypto/caam/compat.h
@@ -23,6 +23,7 @@
#include <linux/types.h>
#include <linux/debugfs.h>
#include <linux/circ_buf.h>
+#include <linux/clk.h>
#include <net/xfrm.h>
#include <crypto/algapi.h>
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 660cc3e..cfd8c9e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -16,6 +16,121 @@
#include "error.h"
/*
+ * ARM targets tend to have clock control subsystems that can
+ * enable/disable clocking to our device. Support clocking
+ * with the following functions.
+ */
+#ifdef CONFIG_ARM
+static inline struct clk *caam_drv_get_clk_ipg(struct caam_drv_private *drv)
+{
+ return drv->caam_ipg;
+}
+
+static inline struct clk *caam_drv_get_clk_mem(struct caam_drv_private *drv)
+{
+ return drv->caam_mem;
+}
+
+static inline struct clk *caam_drv_get_clk_aclk(struct caam_drv_private *drv)
+{
+ return drv->caam_aclk;
+}
+
+static inline struct clk *caam_drv_get_clk_emislow(struct caam_drv_private *drv)
+{
+ return drv->caam_emi_slow;
+}
+
+static inline void caam_drv_set_clk_ipg(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+ drv->caam_ipg = clk;
+}
+
+static inline void caam_drv_set_clk_mem(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+ drv->caam_mem = clk;
+}
+
+static inline void caam_drv_set_clk_aclk(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+ drv->caam_aclk = clk;
+}
+
+static inline void caam_drv_set_clk_emislow(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+ drv->caam_emi_slow = clk;
+}
+
+static inline struct clk *caam_drv_identify_clk(struct device *dev,
+ char *clk_name)
+{
+ return devm_clk_get(dev, clk_name);
+}
+
+static inline void caam_drv_show_clk(struct device *dev, struct clk *clk,
+ char *clk_name)
+{
+ dev_info(dev, "%s clock:%d\n", clk_name, (int)clk_get_rate(clk));
+}
+
+#else
+static inline struct clk *caam_drv_get_clk_ipg(struct caam_drv_private *drv)
+{
+ return NULL;
+}
+
+static inline struct clk *caam_drv_get_clk_mem(struct caam_drv_private *drv)
+{
+ return NULL;
+}
+
+static inline struct clk *caam_drv_get_clk_aclk(struct caam_drv_private *drv)
+{
+ return NULL;
+}
+
+static inline struct clk *caam_drv_get_clk_emislow(struct caam_drv_private *drv)
+{
+ return NULL;
+}
+
+static inline void caam_drv_set_clk_ipg(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+}
+
+static inline void caam_drv_set_clk_mem(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+}
+
+static inline void caam_drv_set_clk_aclk(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+}
+
+static inline void caam_drv_set_clk_emislow(struct caam_drv_private *drv,
+ struct clk *clk)
+{
+}
+
+static inline struct clk *caam_drv_identify_clk(struct device *dev,
+ char *clk_name)
+{
+ return 0;
+}
+
+static inline void caam_drv_show_clk(struct device *dev, struct clk *clk,
+ char *clk_name)
+{
+}
+#endif
+
+/*
* Descriptor to instantiate RNG State Handle 0 in normal mode and
* load the JDKEK, TDKEK and TDSK registers
*/
@@ -304,6 +419,12 @@ static int caam_remove(struct platform_device *pdev)
/* Unmap controller region */
iounmap(ctrl);
+ /* shut clocks off before finalizing shutdown */
+ clk_disable_unprepare(caam_drv_get_clk_ipg(ctrlpriv));
+ clk_disable_unprepare(caam_drv_get_clk_mem(ctrlpriv));
+ clk_disable_unprepare(caam_drv_get_clk_aclk(ctrlpriv));
+ clk_disable_unprepare(caam_drv_get_clk_emislow(ctrlpriv));
+
return ret;
}
@@ -391,6 +512,7 @@ static int caam_probe(struct platform_device *pdev)
struct device_node *nprop, *np;
struct caam_ctrl __iomem *ctrl;
struct caam_drv_private *ctrlpriv;
+ struct clk *clk;
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
@@ -409,6 +531,75 @@ static int caam_probe(struct platform_device *pdev)
ctrlpriv->pdev = pdev;
nprop = pdev->dev.of_node;
+ /* Enable clocking */
+ clk = caam_drv_identify_clk(&pdev->dev, "caam_ipg");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM ipg clk: %d\n", ret);
+ return -ENODEV;
+ }
+ caam_drv_set_clk_ipg(ctrlpriv, clk);
+
+ clk = caam_drv_identify_clk(&pdev->dev, "caam_mem");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM mem clk: %d\n", ret);
+ return -ENODEV;
+ }
+ caam_drv_set_clk_mem(ctrlpriv, clk);
+
+ clk = caam_drv_identify_clk(&pdev->dev, "caam_aclk");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM aclk clk: %d\n", ret);
+ return -ENODEV;
+ }
+ caam_drv_set_clk_aclk(ctrlpriv, clk);
+
+ clk = caam_drv_identify_clk(&pdev->dev, "caam_emi_slow");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM emi_slow clk: %d\n", ret);
+ return -ENODEV;
+ }
+ caam_drv_set_clk_emislow(ctrlpriv, clk);
+
+ ret = clk_prepare_enable(caam_drv_get_clk_ipg(ctrlpriv));
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
+ return -ENODEV;
+ }
+
+ ret = clk_prepare_enable(caam_drv_get_clk_mem(ctrlpriv));
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
+ ret);
+ return -ENODEV;
+ }
+
+ ret = clk_prepare_enable(caam_drv_get_clk_aclk(ctrlpriv));
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
+ return -ENODEV;
+ }
+
+ ret = clk_prepare_enable(caam_drv_get_clk_emislow(ctrlpriv));
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
+ ret);
+ return -ENODEV;
+ }
+
+ caam_drv_show_clk(dev, caam_drv_get_clk_ipg(ctrlpriv), "caam_ipg");
+ caam_drv_show_clk(dev, caam_drv_get_clk_mem(ctrlpriv), "caam_mem");
+ caam_drv_show_clk(dev, caam_drv_get_clk_aclk(ctrlpriv), "caam_aclk");
+ caam_drv_show_clk(dev, caam_drv_get_clk_emislow(ctrlpriv),
+ "caam_emi_slow");
+
/* Get configuration properties from device tree */
/* First, get register page */
ctrl = of_iomap(nprop, 0);
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 89b94cc..e2bcacc 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -91,6 +91,11 @@ struct caam_drv_private {
Handles of the RNG4 block are initialized
by this driver */
+ struct clk *caam_ipg;
+ struct clk *caam_mem;
+ struct clk *caam_aclk;
+ struct clk *caam_emi_slow;
+
/*
* debugfs entries for developer view into driver/device
* variables at runtime.
--
2.1.4
Add CAAM clock support to the i.MX6 clocking infrastructure.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/clk/imx/clk-imx6q.c | 3 +++
include/dt-bindings/clock/imx6qdl-clock.h | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index d046f8e..4de4943 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -381,6 +381,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
+ clk[IMX6QDL_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
+ clk[IMX6QDL_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
+ clk[IMX6QDL_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 8780868..f68e925 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -251,6 +251,9 @@
#define IMX6QDL_CLK_VIDEO_27M 238
#define IMX6QDL_CLK_MIPI_CORE_CFG 239
#define IMX6QDL_CLK_MIPI_IPG 240
-#define IMX6QDL_CLK_END 241
+#define IMX6QDL_CAAM_MEM 241
+#define IMX6QDL_CAAM_ACLK 242
+#define IMX6QDL_CAAM_IPG 243
+#define IMX6QDL_CLK_END 244
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.4
Modify the Scatter-Gather entry definitions for the Freescale
CAAM driver to include support for both 64- and 32-bit DMA pointers.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/desc.h | 25 +++++++++++++++++++++----
drivers/crypto/caam/sg_sw_sec4.h | 1 -
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index d397ff9..405acbf 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -8,12 +8,29 @@
#ifndef DESC_H
#define DESC_H
+/*
+ * 16-byte hardware scatter/gather table
+ * An 8-byte table exists in the hardware spec, but has never been
+ * implemented to date. The 8/16 option is selected at RTL-compile-time.
+ * and this selection is visible in the Compile Time Parameters Register
+ */
+
+#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
+#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
+#define SEC4_SG_BPID_MASK 0x000000ff
+#define SEC4_SG_BPID_SHIFT 16
+#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
+#define SEC4_SG_OFFS_MASK 0x00001fff
+
struct sec4_sg_entry {
- u64 ptr;
-#define SEC4_SG_LEN_FIN 0x40000000
-#define SEC4_SG_LEN_EXT 0x80000000
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+ dma_addr_t ptr;
+#else
+ u32 rsvd1;
+ dma_addr_t ptr;
+#endif
u32 len;
- u8 reserved;
+ u8 rsvd2;
u8 buf_pool_id;
u16 offset;
};
diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h
index b68b74c..711bb39 100644
--- a/drivers/crypto/caam/sg_sw_sec4.h
+++ b/drivers/crypto/caam/sg_sw_sec4.h
@@ -15,7 +15,6 @@ static inline void dma_to_sec4_sg_one(struct sec4_sg_entry *sec4_sg_ptr,
{
sec4_sg_ptr->ptr = dma;
sec4_sg_ptr->len = len;
- sec4_sg_ptr->reserved = 0;
sec4_sg_ptr->buf_pool_id = 0;
sec4_sg_ptr->offset = offset;
#ifdef DEBUG
--
2.1.4
Hi Victoria,
comments inline.
On Wed, Jul 29, 2015 at 08:58:20PM -0700, Victoria Milhoan wrote:
> ARM-based systems may disable clocking to the CAAM device on the
> Freescale i.MX platform for power management purposes. This patch
> enables the required clocks when the CAAM module is initialized and
> disables the required clocks when the CAAM module is shut down.
>
> Signed-off-by: Victoria Milhoan <[email protected]>
> ---
> drivers/crypto/caam/compat.h | 1 +
> drivers/crypto/caam/ctrl.c | 191 +++++++++++++++++++++++++++++++++++++++++++
> drivers/crypto/caam/intern.h | 5 ++
> 3 files changed, 197 insertions(+)
>
> diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h
> index f57f395..b6955ec 100644
> --- a/drivers/crypto/caam/compat.h
> +++ b/drivers/crypto/caam/compat.h
> @@ -23,6 +23,7 @@
> #include <linux/types.h>
> #include <linux/debugfs.h>
> #include <linux/circ_buf.h>
> +#include <linux/clk.h>
> #include <net/xfrm.h>
>
> #include <crypto/algapi.h>
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
> index 660cc3e..cfd8c9e 100644
> --- a/drivers/crypto/caam/ctrl.c
> +++ b/drivers/crypto/caam/ctrl.c
> @@ -16,6 +16,121 @@
> #include "error.h"
>
> /*
> + * ARM targets tend to have clock control subsystems that can
> + * enable/disable clocking to our device. Support clocking
> + * with the following functions.
> + */
> +#ifdef CONFIG_ARM
> +static inline struct clk *caam_drv_get_clk_ipg(struct caam_drv_private *drv)
> +{
> + return drv->caam_ipg;
> +}
You return drv->caam_ipg on ARM and NULL on powerpc. drv->caam_ipg is
NULL on powerpc anyway which makes this different implementations for
ARM and powerpc unnecessary. Just access drv->caam_ipg directly where
needed.
> +
> +static inline struct clk *caam_drv_get_clk_mem(struct caam_drv_private *drv)
> +{
> + return drv->caam_mem;
> +}
> +
> +static inline struct clk *caam_drv_get_clk_aclk(struct caam_drv_private *drv)
> +{
> + return drv->caam_aclk;
> +}
> +
> +static inline struct clk *caam_drv_get_clk_emislow(struct caam_drv_private *drv)
> +{
> + return drv->caam_emi_slow;
> +}
> +
> +static inline void caam_drv_set_clk_ipg(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> + drv->caam_ipg = clk;
> +}
Ditto, just access drv->caam_ipg when needed.
> +
> +static inline void caam_drv_set_clk_mem(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> + drv->caam_mem = clk;
> +}
> +
> +static inline void caam_drv_set_clk_aclk(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> + drv->caam_aclk = clk;
> +}
> +
> +static inline void caam_drv_set_clk_emislow(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> + drv->caam_emi_slow = clk;
> +}
> +
> +static inline struct clk *caam_drv_identify_clk(struct device *dev,
> + char *clk_name)
> +{
> + return devm_clk_get(dev, clk_name);
> +}
devm_clk_get() returns NULL when the architecture does not have clk
support, so it also seems unnecessary to have architecture specific
implementations for this.
> +
> +static inline void caam_drv_show_clk(struct device *dev, struct clk *clk,
> + char *clk_name)
> +{
> + dev_info(dev, "%s clock:%d\n", clk_name, (int)clk_get_rate(clk));
> +}
The correct format specifier for unsigned long is "%lu", no need to cast
it to int. Besides, this information is not generally interesting, you
can drop this.
> +
> +#else
> +static inline struct clk *caam_drv_get_clk_ipg(struct caam_drv_private *drv)
> +{
> + return NULL;
> +}
> +
> +static inline struct clk *caam_drv_get_clk_mem(struct caam_drv_private *drv)
> +{
> + return NULL;
> +}
> +
> +static inline struct clk *caam_drv_get_clk_aclk(struct caam_drv_private *drv)
> +{
> + return NULL;
> +}
> +
> +static inline struct clk *caam_drv_get_clk_emislow(struct caam_drv_private *drv)
> +{
> + return NULL;
> +}
> +
> +static inline void caam_drv_set_clk_ipg(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> +}
> +
> +static inline void caam_drv_set_clk_mem(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> +}
> +
> +static inline void caam_drv_set_clk_aclk(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> +}
> +
> +static inline void caam_drv_set_clk_emislow(struct caam_drv_private *drv,
> + struct clk *clk)
> +{
> +}
> +
> +static inline struct clk *caam_drv_identify_clk(struct device *dev,
> + char *clk_name)
> +{
> + return 0;
> +}
> +
> +static inline void caam_drv_show_clk(struct device *dev, struct clk *clk,
> + char *clk_name)
> +{
> +}
> +#endif
> +
> +/*
> * Descriptor to instantiate RNG State Handle 0 in normal mode and
> * load the JDKEK, TDKEK and TDSK registers
> */
> @@ -304,6 +419,12 @@ static int caam_remove(struct platform_device *pdev)
> /* Unmap controller region */
> iounmap(ctrl);
>
> + /* shut clocks off before finalizing shutdown */
> + clk_disable_unprepare(caam_drv_get_clk_ipg(ctrlpriv));
> + clk_disable_unprepare(caam_drv_get_clk_mem(ctrlpriv));
> + clk_disable_unprepare(caam_drv_get_clk_aclk(ctrlpriv));
> + clk_disable_unprepare(caam_drv_get_clk_emislow(ctrlpriv));
> +
> return ret;
> }
>
> @@ -391,6 +512,7 @@ static int caam_probe(struct platform_device *pdev)
> struct device_node *nprop, *np;
> struct caam_ctrl __iomem *ctrl;
> struct caam_drv_private *ctrlpriv;
> + struct clk *clk;
> #ifdef CONFIG_DEBUG_FS
> struct caam_perfmon *perfmon;
> #endif
> @@ -409,6 +531,75 @@ static int caam_probe(struct platform_device *pdev)
> ctrlpriv->pdev = pdev;
> nprop = pdev->dev.of_node;
>
> + /* Enable clocking */
> + clk = caam_drv_identify_clk(&pdev->dev, "caam_ipg");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + dev_err(&pdev->dev,
> + "can't identify CAAM ipg clk: %d\n", ret);
> + return -ENODEV;
> + }
> + caam_drv_set_clk_ipg(ctrlpriv, clk);
> +
> + clk = caam_drv_identify_clk(&pdev->dev, "caam_mem");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + dev_err(&pdev->dev,
> + "can't identify CAAM mem clk: %d\n", ret);
> + return -ENODEV;
> + }
> + caam_drv_set_clk_mem(ctrlpriv, clk);
> +
> + clk = caam_drv_identify_clk(&pdev->dev, "caam_aclk");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + dev_err(&pdev->dev,
> + "can't identify CAAM aclk clk: %d\n", ret);
> + return -ENODEV;
> + }
> + caam_drv_set_clk_aclk(ctrlpriv, clk);
> +
> + clk = caam_drv_identify_clk(&pdev->dev, "caam_emi_slow");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + dev_err(&pdev->dev,
> + "can't identify CAAM emi_slow clk: %d\n", ret);
> + return -ENODEV;
> + }
> + caam_drv_set_clk_emislow(ctrlpriv, clk);
> +
> + ret = clk_prepare_enable(caam_drv_get_clk_ipg(ctrlpriv));
> + if (ret < 0) {
> + dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
> + return -ENODEV;
> + }
> +
> + ret = clk_prepare_enable(caam_drv_get_clk_mem(ctrlpriv));
> + if (ret < 0) {
> + dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
> + ret);
> + return -ENODEV;
> + }
> +
> + ret = clk_prepare_enable(caam_drv_get_clk_aclk(ctrlpriv));
> + if (ret < 0) {
> + dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
> + return -ENODEV;
> + }
> +
> + ret = clk_prepare_enable(caam_drv_get_clk_emislow(ctrlpriv));
> + if (ret < 0) {
> + dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
> + ret);
> + return -ENODEV;
> + }
> +
> + caam_drv_show_clk(dev, caam_drv_get_clk_ipg(ctrlpriv), "caam_ipg");
No. Each clk_get takes a reference to the clk and must be balanced with
clk_put. You can't just take a new reference each time you need that
clk.
Sascha
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On Wed, Jul 29, 2015 at 08:58:26PM -0700, Victoria Milhoan wrote:
> Add CAAM device node to the i.MX6 device tree.
>
> Signed-off-by: Victoria Milhoan <[email protected]>
> ---
> arch/arm/boot/dts/imx6qdl.dtsi | 30 ++++++++++++++++++++++++++----
> 1 file changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
> index e6d1359..4df9f1e 100644
> --- a/arch/arm/boot/dts/imx6qdl.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl.dtsi
> @@ -836,10 +836,32 @@
> reg = <0x02100000 0x100000>;
> ranges;
>
> - caam@02100000 {
> - reg = <0x02100000 0x40000>;
> - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
> - <0 106 IRQ_TYPE_LEVEL_HIGH>;
> + crypto: caam@2100000 {
> + compatible = "fsl,sec-v4.0";
> + fsl,sec-era = <4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x2100000 0x10000>;
> + ranges = <0 0x2100000 0x10000>;
> + interrupt-parent = <&intc>;
> + clocks = <&clks IMX6QDL_CAAM_MEM>,
> + <&clks IMX6QDL_CAAM_ACLK>,
> + <&clks IMX6QDL_CAAM_IPG>,
> + <&clks IMX6QDL_CLK_EIM_SLOW>;
> + clock-names = "caam_mem", "caam_aclk",
> + "caam_ipg", "caam_emi_slow";
The binding document should be updated for these additional properties.
The namespace caam_ is already clear from the context, you can drop
these prefixes.
Sascha
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On Wed, Jul 29, 2015 at 08:58:25PM -0700, Victoria Milhoan wrote:
> Add CAAM clock support to the i.MX6 clocking infrastructure.
>
> Signed-off-by: Victoria Milhoan <[email protected]>
> ---
> drivers/clk/imx/clk-imx6q.c | 3 +++
> include/dt-bindings/clock/imx6qdl-clock.h | 5 ++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> index d046f8e..4de4943 100644
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -381,6 +381,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
> clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
> clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
> clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
> + clk[IMX6QDL_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
> + clk[IMX6QDL_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
> + clk[IMX6QDL_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
> clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
> clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
> clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
> diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
> index 8780868..f68e925 100644
> --- a/include/dt-bindings/clock/imx6qdl-clock.h
> +++ b/include/dt-bindings/clock/imx6qdl-clock.h
> @@ -251,6 +251,9 @@
> #define IMX6QDL_CLK_VIDEO_27M 238
> #define IMX6QDL_CLK_MIPI_CORE_CFG 239
> #define IMX6QDL_CLK_MIPI_IPG 240
> -#define IMX6QDL_CLK_END 241
> +#define IMX6QDL_CAAM_MEM 241
> +#define IMX6QDL_CAAM_ACLK 242
> +#define IMX6QDL_CAAM_IPG 243
IMX6QDL_CLK_* please.
Sascha
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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On 7/30/2015 6:58 AM, Victoria Milhoan wrote:
> This patch series adds i.MX6 support to the Freescale CAAM driver.
>
> Modifications include:
>
> - explicit cache coherency support in the driver
1. Please check the aead failures when enabling self-tests
(CONFIG_CRYPTO_MANAGER_DISABLE_TESTS not set).
They seem related with the lack of cache coherency support in caamalg.c.
> - register I/O primitive support
> - scatter/gather entry modifications
> - clocking support
> - i.MX6 device tree support for CAAM
> - DMA fixes
>
> These patches have been tested on the i.MX6 and regression tested
> on QorIQ platforms. These patches include changes based on responses
> to the original RFC.
2. i.MX60 and i.MX61 have CHAVID_LS[MDVID] (MDHA version ID) equal to 0.
Thus, there is no support for sha384 and sha512.
Accordingly, all algorithms (hash-only or aead) that use them fail with
MDHA Mode error.
The driver should not be advertising these algorithms to Crypto API
unless supported (MDVID >=1).
3. Another type of failures is the following:
caam_jr 2101000.jr0: 40001d0a: DECO: desc idx 29: Invalid FIFO LOAD Command
alg: aead: encryption failed on test 1 for rfc4106-gcm-aes-caam:
ret=-1073749258
caam_jr 2101000.jr0: 40001c0a: DECO: desc idx 28: Invalid FIFO LOAD Command
alg: aead: encryption failed on test 1 for rfc4543-gcm-aes-caam:
ret=-1073749002
caam_jr 2101000.jr0: 4000210a: DECO: desc idx 33: Invalid FIFO LOAD Command
alg: aead: encryption failed on test 1 for gcm-aes-caam: ret=-1073750282
Thanks,
Horia
Hi Sascha,
Thank you for the responses. Comments inline. Changes will be
in the next version of the patch set.
-Victoria
On Thu, 30 Jul 2015 08:02:14 +0200
Sascha Hauer <[email protected]> wrote:
> Hi Victoria,
>
> comments inline.
>
> On Wed, Jul 29, 2015 at 08:58:20PM -0700, Victoria Milhoan wrote:
> > ARM-based systems may disable clocking to the CAAM device on the
> > Freescale i.MX platform for power management purposes. This patch
> > enables the required clocks when the CAAM module is initialized and
> > disables the required clocks when the CAAM module is shut down.
> >
> > Signed-off-by: Victoria Milhoan <[email protected]>
> > ---
> > drivers/crypto/caam/compat.h | 1 +
> > drivers/crypto/caam/ctrl.c | 191 +++++++++++++++++++++++++++++++++++++++++++
> > drivers/crypto/caam/intern.h | 5 ++
> > 3 files changed, 197 insertions(+)
> >
> > diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h
> > index f57f395..b6955ec 100644
> > --- a/drivers/crypto/caam/compat.h
> > +++ b/drivers/crypto/caam/compat.h
> > @@ -23,6 +23,7 @@
> > #include <linux/types.h>
> > #include <linux/debugfs.h>
> > #include <linux/circ_buf.h>
> > +#include <linux/clk.h>
> > #include <net/xfrm.h>
> >
> > #include <crypto/algapi.h>
> > diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
> > index 660cc3e..cfd8c9e 100644
> > --- a/drivers/crypto/caam/ctrl.c
> > +++ b/drivers/crypto/caam/ctrl.c
> > @@ -16,6 +16,121 @@
> > #include "error.h"
> >
> > /*
> > + * ARM targets tend to have clock control subsystems that can
> > + * enable/disable clocking to our device. Support clocking
> > + * with the following functions.
> > + */
> > +#ifdef CONFIG_ARM
> > +static inline struct clk *caam_drv_get_clk_ipg(struct caam_drv_private *drv)
> > +{
> > + return drv->caam_ipg;
> > +}
>
> You return drv->caam_ipg on ARM and NULL on powerpc. drv->caam_ipg is
> NULL on powerpc anyway which makes this different implementations for
> ARM and powerpc unnecessary. Just access drv->caam_ipg directly where
> needed.
Agreed. I've reworked the patch to use direct references to the clocks.
>
> > +
> > +static inline struct clk *caam_drv_get_clk_mem(struct caam_drv_private *drv)
> > +{
> > + return drv->caam_mem;
> > +}
> > +
> > +static inline struct clk *caam_drv_get_clk_aclk(struct caam_drv_private *drv)
> > +{
> > + return drv->caam_aclk;
> > +}
> > +
> > +static inline struct clk *caam_drv_get_clk_emislow(struct caam_drv_private *drv)
> > +{
> > + return drv->caam_emi_slow;
> > +}
> > +
> > +static inline void caam_drv_set_clk_ipg(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > + drv->caam_ipg = clk;
> > +}
>
> Ditto, just access drv->caam_ipg when needed.
>
> > +
> > +static inline void caam_drv_set_clk_mem(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > + drv->caam_mem = clk;
> > +}
> > +
> > +static inline void caam_drv_set_clk_aclk(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > + drv->caam_aclk = clk;
> > +}
> > +
> > +static inline void caam_drv_set_clk_emislow(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > + drv->caam_emi_slow = clk;
> > +}
> > +
> > +static inline struct clk *caam_drv_identify_clk(struct device *dev,
> > + char *clk_name)
> > +{
> > + return devm_clk_get(dev, clk_name);
> > +}
>
> devm_clk_get() returns NULL when the architecture does not have clk
> support, so it also seems unnecessary to have architecture specific
> implementations for this.
>
Some of the QorIQ architectures have clock support enabled but do not
support clocking to CAAM. This causes devm_clk_get() to return an error
for these clocks instead of NULL. So, the only architecture-specific code
left in the reworked patch is caam_drv_identify_clk().
> > +
> > +static inline void caam_drv_show_clk(struct device *dev, struct clk *clk,
> > + char *clk_name)
> > +{
> > + dev_info(dev, "%s clock:%d\n", clk_name, (int)clk_get_rate(clk));
> > +}
>
> The correct format specifier for unsigned long is "%lu", no need to cast
> it to int. Besides, this information is not generally interesting, you
> can drop this.
>
I removed this code.
> > +
> > +#else
> > +static inline struct clk *caam_drv_get_clk_ipg(struct caam_drv_private *drv)
> > +{
> > + return NULL;
> > +}
> > +
> > +static inline struct clk *caam_drv_get_clk_mem(struct caam_drv_private *drv)
> > +{
> > + return NULL;
> > +}
> > +
> > +static inline struct clk *caam_drv_get_clk_aclk(struct caam_drv_private *drv)
> > +{
> > + return NULL;
> > +}
> > +
> > +static inline struct clk *caam_drv_get_clk_emislow(struct caam_drv_private *drv)
> > +{
> > + return NULL;
> > +}
> > +
> > +static inline void caam_drv_set_clk_ipg(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > +}
> > +
> > +static inline void caam_drv_set_clk_mem(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > +}
> > +
> > +static inline void caam_drv_set_clk_aclk(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > +}
> > +
> > +static inline void caam_drv_set_clk_emislow(struct caam_drv_private *drv,
> > + struct clk *clk)
> > +{
> > +}
> > +
> > +static inline struct clk *caam_drv_identify_clk(struct device *dev,
> > + char *clk_name)
> > +{
> > + return 0;
> > +}
> > +
> > +static inline void caam_drv_show_clk(struct device *dev, struct clk *clk,
> > + char *clk_name)
> > +{
> > +}
> > +#endif
> > +
> > +/*
> > * Descriptor to instantiate RNG State Handle 0 in normal mode and
> > * load the JDKEK, TDKEK and TDSK registers
> > */
> > @@ -304,6 +419,12 @@ static int caam_remove(struct platform_device *pdev)
> > /* Unmap controller region */
> > iounmap(ctrl);
> >
> > + /* shut clocks off before finalizing shutdown */
> > + clk_disable_unprepare(caam_drv_get_clk_ipg(ctrlpriv));
> > + clk_disable_unprepare(caam_drv_get_clk_mem(ctrlpriv));
> > + clk_disable_unprepare(caam_drv_get_clk_aclk(ctrlpriv));
> > + clk_disable_unprepare(caam_drv_get_clk_emislow(ctrlpriv));
> > +
> > return ret;
> > }
> >
> > @@ -391,6 +512,7 @@ static int caam_probe(struct platform_device *pdev)
> > struct device_node *nprop, *np;
> > struct caam_ctrl __iomem *ctrl;
> > struct caam_drv_private *ctrlpriv;
> > + struct clk *clk;
> > #ifdef CONFIG_DEBUG_FS
> > struct caam_perfmon *perfmon;
> > #endif
> > @@ -409,6 +531,75 @@ static int caam_probe(struct platform_device *pdev)
> > ctrlpriv->pdev = pdev;
> > nprop = pdev->dev.of_node;
> >
> > + /* Enable clocking */
> > + clk = caam_drv_identify_clk(&pdev->dev, "caam_ipg");
> > + if (IS_ERR(clk)) {
> > + ret = PTR_ERR(clk);
> > + dev_err(&pdev->dev,
> > + "can't identify CAAM ipg clk: %d\n", ret);
> > + return -ENODEV;
> > + }
> > + caam_drv_set_clk_ipg(ctrlpriv, clk);
> > +
> > + clk = caam_drv_identify_clk(&pdev->dev, "caam_mem");
> > + if (IS_ERR(clk)) {
> > + ret = PTR_ERR(clk);
> > + dev_err(&pdev->dev,
> > + "can't identify CAAM mem clk: %d\n", ret);
> > + return -ENODEV;
> > + }
> > + caam_drv_set_clk_mem(ctrlpriv, clk);
> > +
> > + clk = caam_drv_identify_clk(&pdev->dev, "caam_aclk");
> > + if (IS_ERR(clk)) {
> > + ret = PTR_ERR(clk);
> > + dev_err(&pdev->dev,
> > + "can't identify CAAM aclk clk: %d\n", ret);
> > + return -ENODEV;
> > + }
> > + caam_drv_set_clk_aclk(ctrlpriv, clk);
> > +
> > + clk = caam_drv_identify_clk(&pdev->dev, "caam_emi_slow");
> > + if (IS_ERR(clk)) {
> > + ret = PTR_ERR(clk);
> > + dev_err(&pdev->dev,
> > + "can't identify CAAM emi_slow clk: %d\n", ret);
> > + return -ENODEV;
> > + }
> > + caam_drv_set_clk_emislow(ctrlpriv, clk);
> > +
> > + ret = clk_prepare_enable(caam_drv_get_clk_ipg(ctrlpriv));
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
> > + return -ENODEV;
> > + }
> > +
> > + ret = clk_prepare_enable(caam_drv_get_clk_mem(ctrlpriv));
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
> > + ret);
> > + return -ENODEV;
> > + }
> > +
> > + ret = clk_prepare_enable(caam_drv_get_clk_aclk(ctrlpriv));
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
> > + return -ENODEV;
> > + }
> > +
> > + ret = clk_prepare_enable(caam_drv_get_clk_emislow(ctrlpriv));
> > + if (ret < 0) {
> > + dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
> > + ret);
> > + return -ENODEV;
> > + }
> > +
> > + caam_drv_show_clk(dev, caam_drv_get_clk_ipg(ctrlpriv), "caam_ipg");
>
> No. Each clk_get takes a reference to the clk and must be balanced with
> clk_put. You can't just take a new reference each time you need that
> clk.
This is no longer an issue in the modified code.
>
> Sascha
>
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> Industrial Linux Solutions | http://www.pengutronix.de/ |
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> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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On Thu, 30 Jul 2015 08:14:11 +0200
Sascha Hauer <[email protected]> wrote:
> On Wed, Jul 29, 2015 at 08:58:25PM -0700, Victoria Milhoan wrote:
> > Add CAAM clock support to the i.MX6 clocking infrastructure.
> >
> > Signed-off-by: Victoria Milhoan <[email protected]>
> > ---
> > drivers/clk/imx/clk-imx6q.c | 3 +++
> > include/dt-bindings/clock/imx6qdl-clock.h | 5 ++++-
> > 2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> > index d046f8e..4de4943 100644
> > --- a/drivers/clk/imx/clk-imx6q.c
> > +++ b/drivers/clk/imx/clk-imx6q.c
> > @@ -381,6 +381,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
> > clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
> > clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
> > clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
> > + clk[IMX6QDL_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
> > + clk[IMX6QDL_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
> > + clk[IMX6QDL_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
> > clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
> > clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
> > clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
> > diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
> > index 8780868..f68e925 100644
> > --- a/include/dt-bindings/clock/imx6qdl-clock.h
> > +++ b/include/dt-bindings/clock/imx6qdl-clock.h
> > @@ -251,6 +251,9 @@
> > #define IMX6QDL_CLK_VIDEO_27M 238
> > #define IMX6QDL_CLK_MIPI_CORE_CFG 239
> > #define IMX6QDL_CLK_MIPI_IPG 240
> > -#define IMX6QDL_CLK_END 241
> > +#define IMX6QDL_CAAM_MEM 241
> > +#define IMX6QDL_CAAM_ACLK 242
> > +#define IMX6QDL_CAAM_IPG 243
>
> IMX6QDL_CLK_* please.
Changes made and will be available in the next revision of patches.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
> --
> To unsubscribe from this list: send the line "unsubscribe linux-crypto" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Jul 30, 2015 at 11:32:44PM -0700, Victoria Milhoan wrote:
> Hi Sascha,
>
> Thank you for the responses. Comments inline. Changes will be
> in the next version of the patch set.
>
> -Victoria
>
> On Thu, 30 Jul 2015 08:02:14 +0200
> Sascha Hauer <[email protected]> wrote:
>
> > Hi Victoria,
> >
> > comments inline.
> >
> > On Wed, Jul 29, 2015 at 08:58:20PM -0700, Victoria Milhoan wrote:
> > > ARM-based systems may disable clocking to the CAAM device on the
> > > Freescale i.MX platform for power management purposes. This patch
> > > enables the required clocks when the CAAM module is initialized and
> > > disables the required clocks when the CAAM module is shut down.
> > >
> > > Signed-off-by: Victoria Milhoan <[email protected]>
> > > ---
> > > drivers/crypto/caam/compat.h | 1 +
> > > drivers/crypto/caam/ctrl.c | 191 +++++++++++++++++++++++++++++++++++++++++++
> > > drivers/crypto/caam/intern.h | 5 ++
> > > 3 files changed, 197 insertions(+)
> > >
> > > diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h
> > > index f57f395..b6955ec 100644
> > > --- a/drivers/crypto/caam/compat.h
> > > +++ b/drivers/crypto/caam/compat.h
> > > @@ -23,6 +23,7 @@
> > > #include <linux/types.h>
> > > #include <linux/debugfs.h>
> > > #include <linux/circ_buf.h>
> > > +#include <linux/clk.h>
> > > #include <net/xfrm.h>
> > >
> > > #include <crypto/algapi.h>
> > > diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
> > > index 660cc3e..cfd8c9e 100644
> > > --- a/drivers/crypto/caam/ctrl.c
> > > +++ b/drivers/crypto/caam/ctrl.c
> > > @@ -16,6 +16,121 @@
> > > #include "error.h"
> > >
> > > /*
> > > + * ARM targets tend to have clock control subsystems that can
> > > + * enable/disable clocking to our device. Support clocking
> > > + * with the following functions.
> > > + */
> > > +#ifdef CONFIG_ARM
> > > +static inline struct clk *caam_drv_get_clk_ipg(struct caam_drv_private *drv)
> > > +{
> > > + return drv->caam_ipg;
> > > +}
> >
> > You return drv->caam_ipg on ARM and NULL on powerpc. drv->caam_ipg is
> > NULL on powerpc anyway which makes this different implementations for
> > ARM and powerpc unnecessary. Just access drv->caam_ipg directly where
> > needed.
>
> Agreed. I've reworked the patch to use direct references to the clocks.
>
> >
> > > +
> > > +static inline struct clk *caam_drv_get_clk_mem(struct caam_drv_private *drv)
> > > +{
> > > + return drv->caam_mem;
> > > +}
> > > +
> > > +static inline struct clk *caam_drv_get_clk_aclk(struct caam_drv_private *drv)
> > > +{
> > > + return drv->caam_aclk;
> > > +}
> > > +
> > > +static inline struct clk *caam_drv_get_clk_emislow(struct caam_drv_private *drv)
> > > +{
> > > + return drv->caam_emi_slow;
> > > +}
> > > +
> > > +static inline void caam_drv_set_clk_ipg(struct caam_drv_private *drv,
> > > + struct clk *clk)
> > > +{
> > > + drv->caam_ipg = clk;
> > > +}
> >
> > Ditto, just access drv->caam_ipg when needed.
> >
> > > +
> > > +static inline void caam_drv_set_clk_mem(struct caam_drv_private *drv,
> > > + struct clk *clk)
> > > +{
> > > + drv->caam_mem = clk;
> > > +}
> > > +
> > > +static inline void caam_drv_set_clk_aclk(struct caam_drv_private *drv,
> > > + struct clk *clk)
> > > +{
> > > + drv->caam_aclk = clk;
> > > +}
> > > +
> > > +static inline void caam_drv_set_clk_emislow(struct caam_drv_private *drv,
> > > + struct clk *clk)
> > > +{
> > > + drv->caam_emi_slow = clk;
> > > +}
> > > +
> > > +static inline struct clk *caam_drv_identify_clk(struct device *dev,
> > > + char *clk_name)
> > > +{
> > > + return devm_clk_get(dev, clk_name);
> > > +}
> >
> > devm_clk_get() returns NULL when the architecture does not have clk
> > support, so it also seems unnecessary to have architecture specific
> > implementations for this.
> >
>
> Some of the QorIQ architectures have clock support enabled but do not
> support clocking to CAAM. This causes devm_clk_get() to return an error
> for these clocks instead of NULL. So, the only architecture-specific code
> left in the reworked patch is caam_drv_identify_clk().
I see. Wouldn't it be better to add CAAM clk support for QorIQ then?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Modify the Scatter-Gather entry definitions for the Freescale
CAAM driver to include support for both 64- and 32-bit DMA pointers.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/desc.h | 25 +++++++++++++++++++++----
drivers/crypto/caam/sg_sw_sec4.h | 1 -
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index d397ff9..405acbf 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -8,12 +8,29 @@
#ifndef DESC_H
#define DESC_H
+/*
+ * 16-byte hardware scatter/gather table
+ * An 8-byte table exists in the hardware spec, but has never been
+ * implemented to date. The 8/16 option is selected at RTL-compile-time.
+ * and this selection is visible in the Compile Time Parameters Register
+ */
+
+#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
+#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
+#define SEC4_SG_BPID_MASK 0x000000ff
+#define SEC4_SG_BPID_SHIFT 16
+#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
+#define SEC4_SG_OFFS_MASK 0x00001fff
+
struct sec4_sg_entry {
- u64 ptr;
-#define SEC4_SG_LEN_FIN 0x40000000
-#define SEC4_SG_LEN_EXT 0x80000000
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+ dma_addr_t ptr;
+#else
+ u32 rsvd1;
+ dma_addr_t ptr;
+#endif
u32 len;
- u8 reserved;
+ u8 rsvd2;
u8 buf_pool_id;
u16 offset;
};
diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h
index b68b74c..711bb39 100644
--- a/drivers/crypto/caam/sg_sw_sec4.h
+++ b/drivers/crypto/caam/sg_sw_sec4.h
@@ -15,7 +15,6 @@ static inline void dma_to_sec4_sg_one(struct sec4_sg_entry *sec4_sg_ptr,
{
sec4_sg_ptr->ptr = dma;
sec4_sg_ptr->len = len;
- sec4_sg_ptr->reserved = 0;
sec4_sg_ptr->buf_pool_id = 0;
sec4_sg_ptr->offset = offset;
#ifdef DEBUG
--
2.1.4
Add set/clear 32-bit primitives for compatibility with ARM devices since
the primitives were previously only defined for the Power architecture.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/ctrl.c | 6 +++---
drivers/crypto/caam/regs.h | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 1891809..660cc3e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -445,9 +445,9 @@ static int caam_probe(struct platform_device *pdev)
* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
* long pointers in master configuration register
*/
- clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
- MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
- MCFGR_LONG_PTR : 0));
+ clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
+ MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
+ MCFGR_LONG_PTR : 0));
/*
* Read the Compile Time paramters and SCFGR to determine
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 5e64352..3a2a788 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -65,9 +65,31 @@
*
*/
+#ifdef CONFIG_ARM
+/* These are common macros for Power, put here for ARM */
+#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
+#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
+
+#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v) out_arch(l, le32, a, v)
+#define in_le32(a) in_arch(l, le32, a)
+
+#define out_be32(a, v) out_arch(l, be32, a, v)
+#define in_be32(a) in_arch(l, be32, a)
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+#endif
+
#ifdef __BIG_ENDIAN
#define wr_reg32(reg, data) out_be32(reg, data)
#define rd_reg32(reg) in_be32(reg)
+#define clrsetbits_32(addr, clear, set) clrsetbits_be32(addr, clear, set)
#ifdef CONFIG_64BIT
#define wr_reg64(reg, data) out_be64(reg, data)
#define rd_reg64(reg) in_be64(reg)
@@ -76,6 +98,7 @@
#ifdef __LITTLE_ENDIAN
#define wr_reg32(reg, data) __raw_writel(data, reg)
#define rd_reg32(reg) __raw_readl(reg)
+#define clrsetbits_32(addr, clear, set) clrsetbits_le32(addr, clear, set)
#ifdef CONFIG_64BIT
#define wr_reg64(reg, data) __raw_writeq(data, reg)
#define rd_reg64(reg) __raw_readq(reg)
--
2.1.4
This patch series adds i.MX6 support to the Freescale CAAM driver.
Modifications include:
- explicit cache coherency support in the driver
- register I/O primitive support
- scatter/gather entry modifications
- clocking support
- i.MX6 device tree support for CAAM
- DMA fixes
- algorithm registration based on hardware capabilities
These patches have been tested on the i.MX6 and regression tested
on QorIQ platforms.
Changes in v2:
- Clocking support:
- Minimized architecture differences
- Balanced clk_get and clk_put calls
- Removed display of clock values
- Renamed clock definitions to explicitly show "CLK"
- Removed unnecessary "caam_" prefixes to clock-names property in DTS files
- Added clocks and clock-names property descriptions to SEC 4.0
device tree bindings document
- Added check of hardware capabilities before algorithm registration
- Modified patches based on AEAD changes in caamalg.c
.../devicetree/bindings/crypto/fsl-sec4.txt | 17 ++++
arch/arm/boot/dts/imx6qdl.dtsi | 29 ++++++-
arch/arm/boot/dts/imx6sx.dtsi | 28 +++++++
arch/arm/configs/imx_v6_v7_defconfig | 3 +-
drivers/clk/imx/clk-imx6q.c | 3 +
drivers/crypto/caam/Kconfig | 2 +-
drivers/crypto/caam/caamalg.c | 80 +++++++++++++++---
drivers/crypto/caam/caamhash.c | 67 +++++++++------
drivers/crypto/caam/caamrng.c | 10 ++-
drivers/crypto/caam/compat.h | 1 +
drivers/crypto/caam/ctrl.c | 94 +++++++++++++++++++++-
drivers/crypto/caam/desc.h | 25 +++++-
drivers/crypto/caam/intern.h | 5 ++
drivers/crypto/caam/jr.c | 18 +++++
drivers/crypto/caam/regs.h | 39 ++++++++-
drivers/crypto/caam/sg_sw_sec4.h | 25 ++++--
include/dt-bindings/clock/imx6qdl-clock.h | 5 +-
17 files changed, 389 insertions(+), 62 deletions(-)
--
2.1.4
Add CAAM device node to the i.MX6SX device tree.
Signed-off-by: Victoria Milhoan <[email protected]>
---
arch/arm/boot/dts/imx6sx.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 708175d..20851cb 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -738,6 +738,34 @@
reg = <0x02100000 0x100000>;
ranges;
+ crypto: caam@2100000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2100000 0x10000>;
+ ranges = <0 0x2100000 0x10000>;
+ interrupt-parent = <&intc>;
+ clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
+ <&clks IMX6SX_CLK_CAAM_ACLK>,
+ <&clks IMX6SX_CLK_CAAM_IPG>,
+ <&clks IMX6SX_CLK_EIM_SLOW>;
+ clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <0 106 0x4>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usbotg1: usb@02184000 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
--
2.1.4
Select CAAM for i.MX6 devices.
Signed-off-by: Victoria Milhoan <[email protected]>
---
arch/arm/configs/imx_v6_v7_defconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index b47863d..7569b39 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -354,8 +354,7 @@ CONFIG_PROVE_LOCKING=y
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_SECURITYFS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
CONFIG_CRC_CCITT=m
CONFIG_CRC_T10DIF=y
CONFIG_CRC7=m
--
2.1.4
Register only algorithms supported by CAAM hardware, using the CHA
version and instantiation registers to identify hardware capabilities.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/caamalg.c | 68 ++++++++++++++++++++++++++++++++++++++----
drivers/crypto/caam/caamhash.c | 38 ++++++++++++++++++-----
drivers/crypto/caam/caamrng.c | 6 +++-
drivers/crypto/caam/regs.h | 16 ++++++++--
4 files changed, 110 insertions(+), 18 deletions(-)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 3d1ca08..3361259 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -4371,8 +4371,10 @@ static int __init caam_algapi_init(void)
struct device_node *dev_node;
struct platform_device *pdev;
struct device *ctrldev;
- void *priv;
+ struct caam_drv_private *priv;
int i = 0, err = 0;
+ u32 cha_vid, cha_inst, des_inst, aes_inst, md_inst;
+ unsigned int md_limit = SHA512_DIGEST_SIZE;
bool registered = false;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
@@ -4402,16 +4404,39 @@ static int __init caam_algapi_init(void)
INIT_LIST_HEAD(&alg_list);
- /* register crypto algorithms the device supports */
+ /*
+ * Register crypto algorithms the device supports.
+ * First, detect presence and attributes of DES, AES, and MD blocks.
+ */
+ cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
+ cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
+ des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;
+ aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;
+ md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
+
+ /* If MD is present, limit digest size based on LP256 */
+ if (md_inst && ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256))
+ md_limit = SHA256_DIGEST_SIZE;
+
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
- /* TODO: check if h/w supports alg */
struct caam_crypto_alg *t_alg;
+ struct caam_alg_template *alg = driver_algs + i;
+ u32 alg_sel = alg->class1_alg_type & OP_ALG_ALGSEL_MASK;
+
+ /* Skip DES algorithms if not supported by device */
+ if (!des_inst &&
+ ((alg_sel == OP_ALG_ALGSEL_3DES) ||
+ (alg_sel == OP_ALG_ALGSEL_DES)))
+ continue;
+
+ /* Skip AES algorithms if not supported by device */
+ if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES))
+ continue;
- t_alg = caam_alg_alloc(&driver_algs[i]);
+ t_alg = caam_alg_alloc(alg);
if (IS_ERR(t_alg)) {
err = PTR_ERR(t_alg);
- pr_warn("%s alg allocation failed\n",
- driver_algs[i].driver_name);
+ pr_warn("%s alg allocation failed\n", alg->driver_name);
continue;
}
@@ -4429,6 +4454,37 @@ static int __init caam_algapi_init(void)
for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
struct caam_aead_alg *t_alg = driver_aeads + i;
+ u32 c1_alg_sel = t_alg->caam.class1_alg_type &
+ OP_ALG_ALGSEL_MASK;
+ u32 c2_alg_sel = t_alg->caam.class2_alg_type &
+ OP_ALG_ALGSEL_MASK;
+ u32 alg_aai = t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
+
+ /* Skip DES algorithms if not supported by device */
+ if (!des_inst &&
+ ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
+ (c1_alg_sel == OP_ALG_ALGSEL_DES)))
+ continue;
+
+ /* Skip AES algorithms if not supported by device */
+ if (!aes_inst && (c1_alg_sel == OP_ALG_ALGSEL_AES))
+ continue;
+
+ /*
+ * Check support for AES algorithms not available
+ * on LP devices.
+ */
+ if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)
+ if (alg_aai == OP_ALG_AAI_GCM)
+ continue;
+
+ /*
+ * Skip algorithms requiring message digests
+ * if MD or MD size is not supported by device.
+ */
+ if (c2_alg_sel &&
+ (!md_inst || (t_alg->aead.maxauthsize > md_limit)))
+ continue;
caam_aead_alg_init(t_alg);
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 16c03f8..bb0935a 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -1883,8 +1883,10 @@ static int __init caam_algapi_hash_init(void)
struct device_node *dev_node;
struct platform_device *pdev;
struct device *ctrldev;
- void *priv;
int i = 0, err = 0;
+ struct caam_drv_private *priv;
+ unsigned int md_limit = SHA512_DIGEST_SIZE;
+ u32 cha_inst, cha_vid;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
if (!dev_node) {
@@ -1910,19 +1912,40 @@ static int __init caam_algapi_hash_init(void)
if (!priv)
return -ENODEV;
+ /*
+ * Register crypto algorithms the device supports. First, identify
+ * presence and attributes of MD block.
+ */
+ cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
+ cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
+
+ /*
+ * Skip registration of any hashing algorithms if MD block
+ * is not present.
+ */
+ if (!((cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT))
+ return -ENODEV;
+
+ /* Limit digest size based on LP256 */
+ if ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256)
+ md_limit = SHA256_DIGEST_SIZE;
+
INIT_LIST_HEAD(&hash_list);
/* register crypto algorithms the device supports */
for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
- /* TODO: check if h/w supports alg */
struct caam_hash_alg *t_alg;
+ struct caam_hash_template *alg = driver_hash + i;
+
+ /* If MD size is not supported by device, skip registration */
+ if (alg->template_ahash.halg.digestsize > md_limit)
+ continue;
/* register hmac version */
- t_alg = caam_hash_alloc(&driver_hash[i], true);
+ t_alg = caam_hash_alloc(alg, true);
if (IS_ERR(t_alg)) {
err = PTR_ERR(t_alg);
- pr_warn("%s alg allocation failed\n",
- driver_hash[i].driver_name);
+ pr_warn("%s alg allocation failed\n", alg->driver_name);
continue;
}
@@ -1935,11 +1958,10 @@ static int __init caam_algapi_hash_init(void)
list_add_tail(&t_alg->entry, &hash_list);
/* register unkeyed version */
- t_alg = caam_hash_alloc(&driver_hash[i], false);
+ t_alg = caam_hash_alloc(alg, false);
if (IS_ERR(t_alg)) {
err = PTR_ERR(t_alg);
- pr_warn("%s alg allocation failed\n",
- driver_hash[i].driver_name);
+ pr_warn("%s alg allocation failed\n", alg->driver_name);
continue;
}
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index a1d21d5..345024c 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -315,7 +315,7 @@ static int __init caam_rng_init(void)
struct device_node *dev_node;
struct platform_device *pdev;
struct device *ctrldev;
- void *priv;
+ struct caam_drv_private *priv;
int err;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
@@ -342,6 +342,10 @@ static int __init caam_rng_init(void)
if (!priv)
return -ENODEV;
+ /* Check for an instantiated RNG before registration */
+ if (!(rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & CHA_ID_LS_RNG_MASK))
+ return -ENODEV;
+
dev = caam_jr_alloc();
if (IS_ERR(dev)) {
pr_err("Job Ring Device allocation for transform failed\n");
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 3a2a788..d7c3579 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -156,18 +156,28 @@ struct jr_outentry {
#define CHA_NUM_MS_DECONUM_SHIFT 24
#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
-/* CHA Version IDs */
+/*
+ * CHA version IDs / instantiation bitfields
+ * Defined for use with the cha_id fields in perfmon, but the same shift/mask
+ * selectors can be used to pull out the number of instantiated blocks within
+ * cha_num fields in perfmon because the locations are the same.
+ */
#define CHA_ID_LS_AES_SHIFT 0
-#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
+#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
+#define CHA_ID_LS_AES_LP (0x3ull << CHA_ID_LS_AES_SHIFT)
+#define CHA_ID_LS_AES_HP (0x4ull << CHA_ID_LS_AES_SHIFT)
#define CHA_ID_LS_DES_SHIFT 4
-#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
+#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
#define CHA_ID_LS_ARC4_SHIFT 8
#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
#define CHA_ID_LS_MD_SHIFT 12
#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
+#define CHA_ID_LS_MD_LP256 (0x0ull << CHA_ID_LS_MD_SHIFT)
+#define CHA_ID_LS_MD_LP512 (0x1ull << CHA_ID_LS_MD_SHIFT)
+#define CHA_ID_LS_MD_HP (0x2ull << CHA_ID_LS_MD_SHIFT)
#define CHA_ID_LS_RNG_SHIFT 16
#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
--
2.1.4
The clocks and clock-names properties describe input clocks that may be
required for enablement of CAAM.
Signed-off-by: Victoria Milhoan <[email protected]>
---
Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index e402277..1003073 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -106,6 +106,18 @@ PROPERTIES
to the interrupt parent to which the child domain
is being mapped.
+ - clocks
+ Usage: required if SEC 4.0 requires explicit enablement of clocks
+ Value type: <prop_encoded-array>
+ Definition: A list of phandle and clock specifier pairs describing
+ the clocks required for enabling and disabling SEC 4.0.
+
+ - clock-names
+ Usage: required if SEC 4.0 requires explicit enablement of clocks
+ Value type: <string>
+ Definition: A list of clock name strings in the same order as the
+ clocks property.
+
Note: All other standard properties (see the ePAPR) are allowed
but are optional.
@@ -120,6 +132,11 @@ EXAMPLE
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
+ clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
+ <&clks IMX6QDL_CLK_CAAM_ACLK>,
+ <&clks IMX6QDL_CLK_CAAM_IPG>,
+ <&clks IMX6QDL_CLK_EIM_SLOW>;
+ clock-names = "mem", "aclk", "ipg", "emi_slow";
};
=====================================================================
--
2.1.4
Add CAAM clock support to the i.MX6 clocking infrastructure.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/clk/imx/clk-imx6q.c | 3 +++
include/dt-bindings/clock/imx6qdl-clock.h | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index d046f8e..15e8557 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -381,6 +381,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
+ clk[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
+ clk[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
+ clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 8780868..8de173f 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -251,6 +251,9 @@
#define IMX6QDL_CLK_VIDEO_27M 238
#define IMX6QDL_CLK_MIPI_CORE_CFG 239
#define IMX6QDL_CLK_MIPI_IPG 240
-#define IMX6QDL_CLK_END 241
+#define IMX6QDL_CLK_CAAM_MEM 241
+#define IMX6QDL_CLK_CAAM_ACLK 242
+#define IMX6QDL_CLK_CAAM_IPG 243
+#define IMX6QDL_CLK_END 244
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--
2.1.4
Add CAAM device node to the i.MX6 device tree.
Signed-off-by: Victoria Milhoan <[email protected]>
---
arch/arm/boot/dts/imx6qdl.dtsi | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e6d1359..b5c89cd 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -836,10 +836,31 @@
reg = <0x02100000 0x100000>;
ranges;
- caam@02100000 {
- reg = <0x02100000 0x40000>;
- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
- <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ crypto: caam@2100000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2100000 0x10000>;
+ ranges = <0 0x2100000 0x10000>;
+ interrupt-parent = <&intc>;
+ clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
+ <&clks IMX6QDL_CLK_CAAM_ACLK>,
+ <&clks IMX6QDL_CLK_CAAM_IPG>,
+ <&clks IMX6QDL_CLK_EIM_SLOW>;
+ clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
aipstz@0217c000 { /* AIPSTZ2 */
--
2.1.4
From: Steve Cornelius <[email protected]>
Allow CAAM to be selected in the kernel for Freescale i.MX devices if
ARCH_MXC is enabled.
Signed-off-by: Steve Cornelius <[email protected]>
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig
index e286e28..66ef0c0 100644
--- a/drivers/crypto/caam/Kconfig
+++ b/drivers/crypto/caam/Kconfig
@@ -1,6 +1,6 @@
config CRYPTO_DEV_FSL_CAAM
tristate "Freescale CAAM-Multicore driver backend"
- depends on FSL_SOC
+ depends on FSL_SOC || ARCH_MXC
help
Enables the driver module for Freescale's Cryptographic Accelerator
and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
--
2.1.4
Freescale i.MX6 ARM platforms do not support hardware cache coherency.
This patch adds cache coherency support to the CAAM driver.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/caamhash.c | 2 +-
drivers/crypto/caam/caamrng.c | 4 ++++
drivers/crypto/caam/jr.c | 18 ++++++++++++++++++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index dae1e80..9622a81 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -127,7 +127,7 @@ struct caam_hash_state {
int buflen_0;
u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
int buflen_1;
- u8 caam_ctx[MAX_CTX_LEN];
+ u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
int (*update)(struct ahash_request *req);
int (*final)(struct ahash_request *req);
int (*finup)(struct ahash_request *req);
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 5095337..a1d21d5 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -108,6 +108,10 @@ static void rng_done(struct device *jrdev, u32 *desc, u32 err, void *context)
atomic_set(&bd->empty, BUF_NOT_EMPTY);
complete(&bd->filled);
+
+ /* Buffer refilled, invalidate cache */
+ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE);
+
#ifdef DEBUG
print_hex_dump(KERN_ERR, "rng refreshed buf@: ",
DUMP_PREFIX_ADDRESS, 16, 4, bd->buf, RN_BUF_SIZE, 1);
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index b8b5d47..b7ec1ad 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -202,6 +202,13 @@ static void caam_jr_dequeue(unsigned long devarg)
userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
userstatus = jrp->outring[hw_idx].jrstatus;
+ /*
+ * Make sure all information from the job has been obtained
+ * before telling CAAM that the job has been removed from the
+ * output ring.
+ */
+ mb();
+
/* set done */
wr_reg32(&jrp->rregs->outring_rmvd, 1);
@@ -351,12 +358,23 @@ int caam_jr_enqueue(struct device *dev, u32 *desc,
jrp->inpring[jrp->inp_ring_write_index] = desc_dma;
+ /*
+ * Guarantee that the descriptor's DMA address has been written to
+ * the next slot in the ring before the write index is updated, since
+ * other cores may update this index independently.
+ */
smp_wmb();
jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) &
(JOBR_DEPTH - 1);
jrp->head = (head + 1) & (JOBR_DEPTH - 1);
+ /*
+ * Ensure that all job information has been written before
+ * notifying CAAM that a new job was added to the input ring.
+ */
+ wmb();
+
wr_reg32(&jrp->rregs->inpring_jobadd, 1);
spin_unlock_bh(&jrp->inplock);
--
2.1.4
Avoid moving the head of the scatterlist entry by using temporary
pointers to walk the scatterlist.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/sg_sw_sec4.h | 24 +++++++++++++++++-------
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h
index 711bb39..18cd6d1 100644
--- a/drivers/crypto/caam/sg_sw_sec4.h
+++ b/drivers/crypto/caam/sg_sw_sec4.h
@@ -105,9 +105,15 @@ static inline void dma_unmap_sg_chained(
{
if (unlikely(chained)) {
int i;
+ struct scatterlist *tsg = sg;
+
+ /*
+ * Use a local copy of the sg pointer to avoid moving the
+ * head of the list pointed to by sg as we walk the list.
+ */
for (i = 0; i < nents; i++) {
- dma_unmap_sg(dev, sg, 1, dir);
- sg = sg_next(sg);
+ dma_unmap_sg(dev, tsg, 1, dir);
+ tsg = sg_next(tsg);
}
} else if (nents) {
dma_unmap_sg(dev, sg, nents, dir);
@@ -118,19 +124,23 @@ static inline int dma_map_sg_chained(
struct device *dev, struct scatterlist *sg, unsigned int nents,
enum dma_data_direction dir, bool chained)
{
- struct scatterlist *first = sg;
-
if (unlikely(chained)) {
int i;
+ struct scatterlist *tsg = sg;
+
+ /*
+ * Use a local copy of the sg pointer to avoid moving the
+ * head of the list pointed to by sg as we walk the list.
+ */
for (i = 0; i < nents; i++) {
- if (!dma_map_sg(dev, sg, 1, dir)) {
- dma_unmap_sg_chained(dev, first, i, dir,
+ if (!dma_map_sg(dev, tsg, 1, dir)) {
+ dma_unmap_sg_chained(dev, sg, i, dir,
chained);
nents = 0;
break;
}
- sg = sg_next(sg);
+ tsg = sg_next(tsg);
}
} else
nents = dma_map_sg(dev, sg, nents, dir);
--
2.1.4
This change fixes:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 456 at lib/dma-debug.c:1103 check_unmap+0x438/0x958()
caam_jr 2101000.jr0: DMA-API: device driver frees DMA memory with different size [device address=0x000000003a241080] [map ]
Modules linked in: tcrypt(+)
CPU: 0 PID: 456 Comm: insmod Not tainted 4.1.0-248766-gf823586-dirty #82
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[<80015e0c>] (unwind_backtrace) from [<80012764>] (show_stack+0x10/0x14)
[<80012764>] (show_stack) from [<806df8e8>] (dump_stack+0x84/0xc4)
[<806df8e8>] (dump_stack) from [<800266fc>] (warn_slowpath_common+0x84/0xb4)
[<800266fc>] (warn_slowpath_common) from [<8002675c>] (warn_slowpath_fmt+0x30/0x40)
[<8002675c>] (warn_slowpath_fmt) from [<802c7db8>] (check_unmap+0x438/0x958)
[<802c7db8>] (check_unmap) from [<802c835c>] (debug_dma_unmap_page+0x84/0x8c)
[<802c835c>] (debug_dma_unmap_page) from [<804d3b94>] (ahash_update_ctx+0xb08/0xec4)
[<804d3b94>] (ahash_update_ctx) from [<7f002984>] (test_ahash_pnum.isra.9.constprop.19+0x2b8/0x514 [tcrypt])
[<7f002984>] (test_ahash_pnum.isra.9.constprop.19 [tcrypt]) from [<7f005998>] (do_test+0x2db8/0x37cc [tcrypt])
[<7f005998>] (do_test [tcrypt]) from [<7f00b050>] (tcrypt_mod_init+0x50/0x9c [tcrypt])
[<7f00b050>] (tcrypt_mod_init [tcrypt]) from [<80009730>] (do_one_initcall+0x8c/0x1d4)
[<80009730>] (do_one_initcall) from [<806dda4c>] (do_init_module+0x5c/0x1a8)
[<806dda4c>] (do_init_module) from [<80085308>] (load_module+0x17e0/0x1da0)
[<80085308>] (load_module) from [<80085998>] (SyS_init_module+0xd0/0x120)
[<80085998>] (SyS_init_module) from [<8000f4c0>] (ret_fast_syscall+0x0/0x3c)
---[ end trace 60807cfb6521c79f ]---
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/caamhash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 2361beb..16c03f8 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -829,7 +829,7 @@ static int ahash_update_ctx(struct ahash_request *req)
state->buf_dma = try_buf_map_to_sec4_sg(jrdev,
edesc->sec4_sg + 1,
buf, state->buf_dma,
- *buflen, last_buflen);
+ *next_buflen, *buflen);
if (src_nents) {
src_map_to_sec4_sg(jrdev, req->src, src_nents,
--
2.1.4
ARM-based systems may disable clocking to the CAAM device on the
Freescale i.MX platform for power management purposes. This patch
enables the required clocks when the CAAM module is initialized and
disables the required clocks when the CAAM module is shut down.
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/compat.h | 1 +
drivers/crypto/caam/ctrl.c | 88 ++++++++++++++++++++++++++++++++++++++++++++
drivers/crypto/caam/intern.h | 5 +++
3 files changed, 94 insertions(+)
diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h
index f57f395..b6955ec 100644
--- a/drivers/crypto/caam/compat.h
+++ b/drivers/crypto/caam/compat.h
@@ -23,6 +23,7 @@
#include <linux/types.h>
#include <linux/debugfs.h>
#include <linux/circ_buf.h>
+#include <linux/clk.h>
#include <net/xfrm.h>
#include <crypto/algapi.h>
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 660cc3e..37c2d8d 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -16,6 +16,24 @@
#include "error.h"
/*
+ * ARM targets tend to have clock control subsystems that can
+ * enable/disable clocking to our device.
+ */
+#ifdef CONFIG_ARM
+static inline struct clk *caam_drv_identify_clk(struct device *dev,
+ char *clk_name)
+{
+ return devm_clk_get(dev, clk_name);
+}
+#else
+static inline struct clk *caam_drv_identify_clk(struct device *dev,
+ char *clk_name)
+{
+ return NULL;
+}
+#endif
+
+/*
* Descriptor to instantiate RNG State Handle 0 in normal mode and
* load the JDKEK, TDKEK and TDSK registers
*/
@@ -304,6 +322,12 @@ static int caam_remove(struct platform_device *pdev)
/* Unmap controller region */
iounmap(ctrl);
+ /* shut clocks off before finalizing shutdown */
+ clk_disable_unprepare(ctrlpriv->caam_ipg);
+ clk_disable_unprepare(ctrlpriv->caam_mem);
+ clk_disable_unprepare(ctrlpriv->caam_aclk);
+ clk_disable_unprepare(ctrlpriv->caam_emi_slow);
+
return ret;
}
@@ -391,6 +415,7 @@ static int caam_probe(struct platform_device *pdev)
struct device_node *nprop, *np;
struct caam_ctrl __iomem *ctrl;
struct caam_drv_private *ctrlpriv;
+ struct clk *clk;
#ifdef CONFIG_DEBUG_FS
struct caam_perfmon *perfmon;
#endif
@@ -409,6 +434,69 @@ static int caam_probe(struct platform_device *pdev)
ctrlpriv->pdev = pdev;
nprop = pdev->dev.of_node;
+ /* Enable clocking */
+ clk = caam_drv_identify_clk(&pdev->dev, "ipg");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM ipg clk: %d\n", ret);
+ return -ENODEV;
+ }
+ ctrlpriv->caam_ipg = clk;
+
+ clk = caam_drv_identify_clk(&pdev->dev, "mem");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM mem clk: %d\n", ret);
+ return -ENODEV;
+ }
+ ctrlpriv->caam_mem = clk;
+
+ clk = caam_drv_identify_clk(&pdev->dev, "aclk");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM aclk clk: %d\n", ret);
+ return -ENODEV;
+ }
+ ctrlpriv->caam_aclk = clk;
+
+ clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
+ if (IS_ERR(clk)) {
+ ret = PTR_ERR(clk);
+ dev_err(&pdev->dev,
+ "can't identify CAAM emi_slow clk: %d\n", ret);
+ return -ENODEV;
+ }
+ ctrlpriv->caam_emi_slow = clk;
+
+ ret = clk_prepare_enable(ctrlpriv->caam_ipg);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
+ return -ENODEV;
+ }
+
+ ret = clk_prepare_enable(ctrlpriv->caam_mem);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
+ ret);
+ return -ENODEV;
+ }
+
+ ret = clk_prepare_enable(ctrlpriv->caam_aclk);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
+ return -ENODEV;
+ }
+
+ ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
+ ret);
+ return -ENODEV;
+ }
+
/* Get configuration properties from device tree */
/* First, get register page */
ctrl = of_iomap(nprop, 0);
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 89b94cc..e2bcacc 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -91,6 +91,11 @@ struct caam_drv_private {
Handles of the RNG4 block are initialized
by this driver */
+ struct clk *caam_ipg;
+ struct clk *caam_mem;
+ struct clk *caam_aclk;
+ struct clk *caam_emi_slow;
+
/*
* debugfs entries for developer view into driver/device
* variables at runtime.
--
2.1.4
Since fields must be ORed in to operate correctly using any order of
operations, changed allocations of the combination of extended
descriptor structs + hardware scatterlists to use kzalloc() instead
of kmalloc(), so as to ensure that residue data would not be ORed in
with the correct data.
Signed-off-by: Steve Cornelius <[email protected]>
Signed-off-by: Victoria Milhoan <[email protected]>
---
drivers/crypto/caam/caamalg.c | 12 ++++++------
drivers/crypto/caam/caamhash.c | 25 ++++++++++++-------------
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index b09c171..3d1ca08 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2199,8 +2199,8 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
@@ -2503,8 +2503,8 @@ static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
@@ -2682,8 +2682,8 @@ static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc(
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(*edesc) + desc_bytes +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return ERR_PTR(-ENOMEM);
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index 9622a81..2361beb 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -807,7 +807,7 @@ static int ahash_update_ctx(struct ahash_request *req)
* allocate space for base edesc and hw desc commands,
* link tables
*/
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
sec4_sg_bytes, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev,
@@ -918,8 +918,8 @@ static int ahash_final_ctx(struct ahash_request *req)
sec4_sg_bytes = (1 + (buflen ? 1 : 0)) * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1005,8 +1005,8 @@ static int ahash_finup_ctx(struct ahash_request *req)
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1091,8 +1091,8 @@ static int ahash_digest(struct ahash_request *req)
sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
- DESC_JOB_IO_LEN, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + sec4_sg_bytes + DESC_JOB_IO_LEN,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1165,8 +1165,7 @@ static int ahash_final_no_ctx(struct ahash_request *req)
int sh_len;
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
- GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1245,7 +1244,7 @@ static int ahash_update_no_ctx(struct ahash_request *req)
* allocate space for base edesc and hw desc commands,
* link tables
*/
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
sec4_sg_bytes, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev,
@@ -1353,8 +1352,8 @@ static int ahash_finup_no_ctx(struct ahash_request *req)
sizeof(struct sec4_sg_entry);
/* allocate space for base edesc and hw desc commands, link tables */
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
- sec4_sg_bytes, GFP_DMA | flags);
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
+ GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev, "could not allocate extended descriptor\n");
return -ENOMEM;
@@ -1448,7 +1447,7 @@ static int ahash_update_first(struct ahash_request *req)
* allocate space for base edesc and hw desc commands,
* link tables
*/
- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
sec4_sg_bytes, GFP_DMA | flags);
if (!edesc) {
dev_err(jrdev,
--
2.1.4
On 8/5/2015 9:28 PM, Victoria Milhoan wrote:
> Add CAAM device node to the i.MX6SX device tree.
>
> Signed-off-by: Victoria Milhoan <[email protected]>
> ---
> arch/arm/boot/dts/imx6sx.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> index 708175d..20851cb 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -738,6 +738,34 @@
> reg = <0x02100000 0x100000>;
> ranges;
>
> + crypto: caam@2100000 {
> + compatible = "fsl,sec-v4.0";
> + fsl,sec-era = <4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x2100000 0x10000>;
> + ranges = <0 0x2100000 0x10000>;
> + interrupt-parent = <&intc>;
> + clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
> + <&clks IMX6SX_CLK_CAAM_ACLK>,
> + <&clks IMX6SX_CLK_CAAM_IPG>,
> + <&clks IMX6SX_CLK_EIM_SLOW>;
> + clock-names = "mem", "aclk", "ipg", "emi_slow";
> +
> + sec_jr0: jr0@1000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x1000 0x1000>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr1: jr1@2000 {
> + compatible = "fsl,sec-v4.0-job-ring";
> + reg = <0x2000 0x1000>;
> + interrupts = <0 106 0x4>;
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
Typo - duplicate property. Remove the first one.
Horia
On Thu, 6 Aug 2015 11:59:34 +0300
Horia Geantă <[email protected]> wrote:
> On 8/5/2015 9:28 PM, Victoria Milhoan wrote:
> > Add CAAM device node to the i.MX6SX device tree.
> >
> > Signed-off-by: Victoria Milhoan <[email protected]>
> > ---
> > arch/arm/boot/dts/imx6sx.dtsi | 28 ++++++++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> > index 708175d..20851cb 100644
> > --- a/arch/arm/boot/dts/imx6sx.dtsi
> > +++ b/arch/arm/boot/dts/imx6sx.dtsi
> > @@ -738,6 +738,34 @@
> > reg = <0x02100000 0x100000>;
> > ranges;
> >
> > + crypto: caam@2100000 {
> > + compatible = "fsl,sec-v4.0";
> > + fsl,sec-era = <4>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + reg = <0x2100000 0x10000>;
> > + ranges = <0 0x2100000 0x10000>;
> > + interrupt-parent = <&intc>;
> > + clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
> > + <&clks IMX6SX_CLK_CAAM_ACLK>,
> > + <&clks IMX6SX_CLK_CAAM_IPG>,
> > + <&clks IMX6SX_CLK_EIM_SLOW>;
> > + clock-names = "mem", "aclk", "ipg", "emi_slow";
> > +
> > + sec_jr0: jr0@1000 {
> > + compatible = "fsl,sec-v4.0-job-ring";
> > + reg = <0x1000 0x1000>;
> > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sec_jr1: jr1@2000 {
> > + compatible = "fsl,sec-v4.0-job-ring";
> > + reg = <0x2000 0x1000>;
> > + interrupts = <0 106 0x4>;
> > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
>
> Typo - duplicate property. Remove the first one.
I will send out a replacement patch shortly.
>
> Horia
>
>
--
Victoria Milhoan <[email protected]>
Add CAAM device node to the i.MX6SX device tree.
Signed-off-by: Victoria Milhoan <[email protected]>
---
arch/arm/boot/dts/imx6sx.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 708175d..e6223d8 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -738,6 +738,33 @@
reg = <0x02100000 0x100000>;
ranges;
+ crypto: caam@2100000 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2100000 0x10000>;
+ ranges = <0 0x2100000 0x10000>;
+ interrupt-parent = <&intc>;
+ clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
+ <&clks IMX6SX_CLK_CAAM_ACLK>,
+ <&clks IMX6SX_CLK_CAAM_IPG>,
+ <&clks IMX6SX_CLK_EIM_SLOW>;
+ clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usbotg1: usb@02184000 {
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
--
2.1.4
On 8/6/2015 9:42 PM, Victoria Milhoan wrote:
> Add CAAM device node to the i.MX6SX device tree.
>
> Signed-off-by: Victoria Milhoan <[email protected]>
Vicki, thanks for your work!
For the series:
Tested-by: Horia Geantă <[email protected]>
on imx6q-sabresd.
Note that patch 14/14
crypto: caam - Detect hardware features during algorithm registration
should be applied before 13/14
ARM: imx_v6_v7_defconfig: Select CAAM
(in case the patches won't go through different trees).
Horia
On Wed, Aug 05, 2015 at 11:28:39AM -0700, Victoria Milhoan wrote:
> Since fields must be ORed in to operate correctly using any order of
> operations, changed allocations of the combination of extended
> descriptor structs + hardware scatterlists to use kzalloc() instead
> of kmalloc(), so as to ensure that residue data would not be ORed in
> with the correct data.
>
> Signed-off-by: Steve Cornelius <[email protected]>
> Signed-off-by: Victoria Milhoan <[email protected]>
Please rebase this on the current cryptodev tree.
Thanks,
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Wed, Aug 05, 2015 at 11:28:34AM -0700, Victoria Milhoan wrote:
> This patch series adds i.MX6 support to the Freescale CAAM driver.
>
> Modifications include:
>
> - explicit cache coherency support in the driver
> - register I/O primitive support
> - scatter/gather entry modifications
> - clocking support
> - i.MX6 device tree support for CAAM
> - DMA fixes
> - algorithm registration based on hardware capabilities
>
> These patches have been tested on the i.MX6 and regression tested
> on QorIQ platforms.
>
> Changes in v2:
> - Clocking support:
> - Minimized architecture differences
> - Balanced clk_get and clk_put calls
> - Removed display of clock values
> - Renamed clock definitions to explicitly show "CLK"
> - Removed unnecessary "caam_" prefixes to clock-names property in DTS files
> - Added clocks and clock-names property descriptions to SEC 4.0
> device tree bindings document
> - Added check of hardware capabilities before algorithm registration
> - Modified patches based on AEAD changes in caamalg.c
All applied with v3 for patch 11 and the order of patches 13 and
14 reversed.
Thanks!
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt