Changes since v1:
=================
- v1 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- v1 did not work well as reported earlier by Dmitry, so v2 contains the following
changes/fixes:
~ Enable the interconnect path b/w BAM DMA and main memory first
before trying to access the BAM DMA registers.
~ Enable the interconnect path b/w qce crytpo and main memory first
before trying to access the qce crypto registers.
~ Make sure to document the required and optional properties for both
BAM DMA and qce crypto drivers.
~ Add a few debug related print messages in case the qce crypto driver
passes or fails to probe.
~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
or the interconnect driver(s) (needed on specific Qualcomm parts) are not
yet probed.
Qualcomm crypto engine is also available on sm8250 SoC.
It supports hardware accelerated algorithms for encryption
and authentication. It also provides support for aes, des, 3des
encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
authentication algorithms.
Tested the enabled crypto algorithms with cryptsetup test utilities
on sm8250-mtp and RB5 board (see [1]).
While at it, also make a minor fix in 'sdm845.dtsi', to make
sure it confirms with the other .dtsi files which expose
crypto nodes on qcom SoCs.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Bhupesh Sharma (14):
dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to
optional properties
dt-bindings: qcom-bam: Add 'iommus' to required properties
dt-bindings: qcom-qce: Add 'iommus' to required properties
dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to
optional properties
arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
dt-bindings: crypto : Add new compatible strings for qcom-qce
arm64/dts: qcom: Use new compatibles for crypto nodes
crypto: qce: Add new compatibles for qce crypto driver
crypto: qce: Print a failure msg in case probe() fails
crypto: qce: Convert the device found dev_dbg() to dev_info()
dma: qcom: bam_dma: Create a new header file for BAM DMA driver
crypto: qce: Defer probing if BAM dma is not yet initialized
crypto: qce: Defer probe in case interconnect is not yet initialized
arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
Thara Gopinath (3):
dma: qcom: bam_dma: Add support to initialize interconnect path
crypto: qce: core: Add support to initialize interconnect path
crypto: qce: core: Make clocks optional
.../devicetree/bindings/crypto/qcom-qce.txt | 22 +-
.../devicetree/bindings/dma/qcom_bam_dma.txt | 5 +
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++
drivers/crypto/qce/core.c | 112 +++++--
drivers/crypto/qce/core.h | 3 +
drivers/dma/qcom/bam_dma.c | 306 ++----------------
include/soc/qcom/bam_dma.h | 290 +++++++++++++++++
9 files changed, 457 insertions(+), 317 deletions(-)
create mode 100644 include/soc/qcom/bam_dma.h
--
2.30.2
Add the missing required property - 'iommus' to the
device-tree binding documentation for qcom-bam DMA IP.
This property describes the phandle(s) to apps_smmu node with sid mask.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
Documentation/devicetree/bindings/dma/qcom_bam_dma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
index 077242956ff2..60a76c0fb118 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
@@ -13,6 +13,7 @@ Required properties:
- clock-names: must contain "bam_clk" entry
- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
the secure world.
+- iommus : phandle to apps_smmu node with sid mask
Optional properties:
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
--
2.30.2
Add the missing required property - 'iommus' to the
device-tree binding documentation for qcom-qce crypto IP.
This property describes the phandle(s) to apps_smmu node with sid mask.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
index fdd53b184ba8..07ee1b12000b 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
@@ -11,6 +11,7 @@ Required properties:
- dmas : DMA specifiers for tx and rx dma channels. For more see
Documentation/devicetree/bindings/dma/dma.txt
- dma-names : DMA request names should be "rx" and "tx"
+- iommus : phandle to apps_smmu node with sid mask
Example:
crypto@fd45a000 {
--
2.30.2
In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries
to support crypto engine."), we decided to use the value indicated
by constant RPMH_CE_CLK rather than using it directly.
Now that the same RPMH clock value might be used for other
SoCs (in addition to sdm845), let's use the constant
RPMH_CE_CLK to make sure that this dtsi is compatible with the
other qcom ones.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0a86fe71a66d..2ec4be930fd6 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2316,7 +2316,7 @@ cryptobam: dma@1dc4000 {
compatible = "qcom,bam-v1.7.0";
reg = <0 0x01dc4000 0 0x24000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rpmhcc 15>;
+ clocks = <&rpmhcc RPMH_CE_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
@@ -2332,7 +2332,7 @@ crypto: crypto@1dfa000 {
reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AHB_CLK>,
- <&rpmhcc 15>;
+ <&rpmhcc RPMH_CE_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 6>, <&cryptobam 7>;
dma-names = "rx", "tx";
--
2.30.2
Add 'interconnects' and 'interconnect-names' to the device-tree binding
documentation for qcom crypto IP.
These properties describe the interconnect path between crypto and main
memory and the interconnect type respectively.
While at it also move 'clocks' to the optional properties sections,
as crypto IPs on SoCs like sm8150, sm8250, sm8350 (and so on), don't
require linux to setup the clocks (this is already done by the secure
firmware running before linux).
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.txt | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
index 07ee1b12000b..3f70cee1a491 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
@@ -4,15 +4,19 @@ Required properties:
- compatible : should be "qcom,crypto-v5.1"
- reg : specifies base physical address and size of the registers map
-- clocks : phandle to clock-controller plus clock-specifier pair
-- clock-names : "iface" clocks register interface
- "bus" clocks data transfer interface
- "core" clocks rest of the crypto block
- dmas : DMA specifiers for tx and rx dma channels. For more see
Documentation/devicetree/bindings/dma/dma.txt
- dma-names : DMA request names should be "rx" and "tx"
- iommus : phandle to apps_smmu node with sid mask
+Optional properties:
+- clocks : phandle to clock-controller plus clock-specifier pair
+- clock-names : "iface" clocks register interface
+ "bus" clocks data transfer interface
+ "core" clocks rest of the crypto block
+- interconnects : Interconnect path between qce crypto and main memory
+- interconnect-names: should be "memory"
+
Example:
crypto@fd45a000 {
compatible = "qcom,crypto-v5.1";
@@ -23,4 +27,6 @@ Example:
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
};
--
2.30.2
Newer qcom chips support newer versions of the qce crypto IP, so add
soc specific compatible strings for qcom-qce instead of using crypto
IP version specific ones.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
index 3f70cee1a491..814fe3c577fb 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
@@ -2,7 +2,12 @@ Qualcomm crypto engine driver
Required properties:
-- compatible : should be "qcom,crypto-v5.1"
+- compatible : Supported versions are:
+ - "qcom,ipq6018-qce", for ipq6018
+ - "qcom,sdm845-qce", for sdm845
+ - "qcom,sm8150-qce", for sm8150
+ - "qcom,sm8250-qce", for sm8250
+ - "qcom,sm8350-qce", for sm8350
- reg : specifies base physical address and size of the registers map
- dmas : DMA specifiers for tx and rx dma channels. For more see
Documentation/devicetree/bindings/dma/dma.txt
--
2.30.2
Since we are using soc specific qce crypto IP compatibles
in the bindings now, use the same in the device tree files
which include the crypto nodes.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 9fa5b028e4f3..978c34f176de 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -205,7 +205,7 @@ cryptobam: dma-controller@704000 {
};
crypto: crypto@73a000 {
- compatible = "qcom,crypto-v5.1";
+ compatible = "qcom,ipq6018-qce";
reg = <0x0 0x0073a000 0x0 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2ec4be930fd6..6423991fa303 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2328,7 +2328,7 @@ cryptobam: dma@1dc4000 {
};
crypto: crypto@1dfa000 {
- compatible = "qcom,crypto-v5.4";
+ compatible = "qcom,sdm845-qce";
reg = <0 0x01dfa000 0 0x6000>;
clocks = <&gcc GCC_CE1_AHB_CLK>,
<&gcc GCC_CE1_AHB_CLK>,
--
2.30.2
From: Thara Gopinath <[email protected]>
BAM dma engine associated with certain hardware blocks could require
relevant interconnect pieces be initialized prior to the dma engine
initialization. For e.g. crypto bam dma engine on sm8250. Such requirement
is passed on to the bam dma driver from dt via the "interconnects"
property. Add support in bam_dma driver to check whether the interconnect
path is accessible/enabled prior to attempting driver intializations.
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
[Make header file inclusion alphabetical]
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/dma/qcom/bam_dma.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index c8a77b428b52..fc84ef42507d 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -26,6 +26,7 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/init.h>
+#include <linux/interconnect.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/interrupt.h>
@@ -392,6 +393,7 @@ struct bam_device {
const struct reg_offset_data *layout;
struct clk *bamclk;
+ struct icc_path *mem_path;
int irq;
/* dma start transaction tasklet */
@@ -1284,9 +1286,18 @@ static int bam_dma_probe(struct platform_device *pdev)
return ret;
}
+ /* Ensure that interconnects are initialized */
+ bdev->mem_path = of_icc_get(bdev->dev, "memory");
+
+ if (IS_ERR(bdev->mem_path)) {
+ ret = PTR_ERR(bdev->mem_path);
+ dev_err(bdev->dev, "failed to acquire icc path %d\n", ret);
+ goto err_disable_clk;
+ }
+
ret = bam_init(bdev);
if (ret)
- goto err_disable_clk;
+ goto err_icc_path_put;
tasklet_setup(&bdev->task, dma_tasklet);
@@ -1371,6 +1382,8 @@ static int bam_dma_probe(struct platform_device *pdev)
tasklet_kill(&bdev->channels[i].vc.task);
err_tasklet_kill:
tasklet_kill(&bdev->task);
+err_icc_path_put:
+ icc_put(bdev->mem_path);
err_disable_clk:
clk_disable_unprepare(bdev->bamclk);
@@ -1406,6 +1419,7 @@ static int bam_dma_remove(struct platform_device *pdev)
tasklet_kill(&bdev->task);
+ icc_put(bdev->mem_path);
clk_disable_unprepare(bdev->bamclk);
return 0;
--
2.30.2
Since we decided to use soc specific compatibles for describing
the qce crypto IP nodes in the device-trees, adapt the driver
now to handle the same.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
drivers/crypto/qce/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 92a0ff1d357e..f6032c303c8c 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -294,8 +294,8 @@ static int qce_crypto_remove(struct platform_device *pdev)
}
static const struct of_device_id qce_crypto_of_match[] = {
- { .compatible = "qcom,crypto-v5.1", },
- { .compatible = "qcom,crypto-v5.4", },
+ { .compatible = "qcom,ipq6018-qce", },
+ { .compatible = "qcom,sdm845-qce", },
{}
};
MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
--
2.30.2
Print a failure message (dev_err) in case the qcom qce crypto
driver probe() fails.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
drivers/crypto/qce/core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 293d0bfe3aab..bae08fdfc44f 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -301,6 +301,8 @@ static int qce_crypto_probe(struct platform_device *pdev)
icc_set_bw(qce->mem_path, 0, 0);
err_mem_path_put:
icc_put(qce->mem_path);
+
+ dev_err(dev, "%s failed : %d\n", __func__, ret);
return ret;
}
--
2.30.2
QCE crypto driver is right now too silent even if the probe() is ok
and a valid crypto IP version is found.
Convert the dev_dbg() message to a dev_info() instead.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
drivers/crypto/qce/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index bae08fdfc44f..9a7d7ef94687 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -179,7 +179,7 @@ static int qce_check_version(struct qce_device *qce)
*/
qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1;
- dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
+ dev_info(qce->dev, "Crypto device found, version %d.%d.%d\n",
major, minor, step);
return 0;
--
2.30.2
From: Thara Gopinath <[email protected]>
On certain Snapdragon processors, the crypto engine clocks are enabled by
default by security firmware and the driver need not handle the
clocks. Make acquiring of all the clocks optional in crypto enginer driver
so that the driver intializes properly even if no clocks are specified in
the dt.
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
[Make clock enablement optional only for qcom parts where
firmware has already initialized them, using a bool variable]
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/crypto/qce/core.c | 85 +++++++++++++++++++++++----------------
drivers/crypto/qce/core.h | 2 +
2 files changed, 53 insertions(+), 34 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index f6032c303c8c..293d0bfe3aab 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -9,6 +9,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/types.h>
@@ -184,12 +185,23 @@ static int qce_check_version(struct qce_device *qce)
return 0;
}
+static const struct of_device_id qce_crypto_of_match[] = {
+ { .compatible = "qcom,ipq6018-qce", },
+ { .compatible = "qcom,sdm845-qce", },
+ { .compatible = "qcom,sm8250-qce", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
+
static int qce_crypto_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct qce_device *qce;
+ const struct of_device_id *of_id =
+ of_match_device(qce_crypto_of_match, &pdev->dev);
int ret;
+
qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
if (!qce)
return -ENOMEM;
@@ -209,39 +221,51 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (IS_ERR(qce->mem_path))
return PTR_ERR(qce->mem_path);
- qce->core = devm_clk_get(qce->dev, "core");
- if (IS_ERR(qce->core)) {
- ret = PTR_ERR(qce->core);
- goto err_mem_path_put;
- }
-
- qce->iface = devm_clk_get(qce->dev, "iface");
- if (IS_ERR(qce->iface)) {
- ret = PTR_ERR(qce->iface);
- goto err_mem_path_put;
- }
-
- qce->bus = devm_clk_get(qce->dev, "bus");
- if (IS_ERR(qce->bus)) {
- ret = PTR_ERR(qce->bus);
- goto err_mem_path_put;
- }
-
ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
if (ret)
goto err_mem_path_put;
- ret = clk_prepare_enable(qce->core);
- if (ret)
- goto err_mem_path_disable;
+ /* On some qcom parts the crypto clocks are already configured by
+ * the firmware running before linux. In such cases we don't need to
+ * enable/configure them again. Check here for the same.
+ */
+ if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") ||
+ !strcmp(of_id->compatible, "qcom,sdm845-qce"))
+ qce->clks_configured_by_fw = false;
+ else
+ qce->clks_configured_by_fw = true;
+
+ if (!qce->clks_configured_by_fw) {
+ qce->core = devm_clk_get(qce->dev, "core");
+ if (IS_ERR(qce->core)) {
+ ret = PTR_ERR(qce->core);
+ goto err_mem_path_put;
+ }
+
+ qce->iface = devm_clk_get(qce->dev, "iface");
+ if (IS_ERR(qce->iface)) {
+ ret = PTR_ERR(qce->iface);
+ goto err_mem_path_put;
+ }
+
+ qce->bus = devm_clk_get(qce->dev, "bus");
+ if (IS_ERR(qce->bus)) {
+ ret = PTR_ERR(qce->bus);
+ goto err_mem_path_put;
+ }
+
+ ret = clk_prepare_enable(qce->core);
+ if (ret)
+ goto err_mem_path_disable;
- ret = clk_prepare_enable(qce->iface);
- if (ret)
- goto err_clks_core;
+ ret = clk_prepare_enable(qce->iface);
+ if (ret)
+ goto err_clks_core;
- ret = clk_prepare_enable(qce->bus);
- if (ret)
- goto err_clks_iface;
+ ret = clk_prepare_enable(qce->bus);
+ if (ret)
+ goto err_clks_iface;
+ }
ret = qce_dma_request(qce->dev, &qce->dma);
if (ret)
@@ -293,13 +317,6 @@ static int qce_crypto_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id qce_crypto_of_match[] = {
- { .compatible = "qcom,ipq6018-qce", },
- { .compatible = "qcom,sdm845-qce", },
- {}
-};
-MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
-
static struct platform_driver qce_crypto_driver = {
.probe = qce_crypto_probe,
.remove = qce_crypto_remove,
diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
index 228fcd69ec51..d9bf05babecc 100644
--- a/drivers/crypto/qce/core.h
+++ b/drivers/crypto/qce/core.h
@@ -23,6 +23,7 @@
* @dma: pointer to dma data
* @burst_size: the crypto burst size
* @pipe_pair_id: which pipe pair id the device using
+ * @clks_configured_by_fw: clocks are already configured by fw
* @async_req_enqueue: invoked by every algorithm to enqueue a request
* @async_req_done: invoked by every algorithm to finish its request
*/
@@ -39,6 +40,7 @@ struct qce_device {
struct qce_dma_data dma;
int burst_size;
unsigned int pipe_pair_id;
+ bool clks_configured_by_fw;
int (*async_req_enqueue)(struct qce_device *qce,
struct crypto_async_request *req);
void (*async_req_done)(struct qce_device *qce, int ret);
--
2.30.2
Add crypto engine (CE) and CE BAM related nodes and definitions to
"sm8250.dtsi".
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 4c0de12aaba6..6700d609a7b8 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3796,6 +3796,34 @@ cpufreq_hw: cpufreq@18591000 {
#freq-domain-cells = <1>;
};
+
+ cryptobam: dma@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely = <1>;
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8250-qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>;
+ interconnect-names = "memory";
+ };
};
timer {
--
2.30.2
Since the Qualcomm qce crypto driver needs the BAM dma driver to be
setup first (to allow crypto operations), it makes sense to defer
the qce crypto driver probing in case the BAM dma driver is not yet
probed.
This fixes the qce probe failure issues when both qce and BMA dma
are compiled as static part of the kernel.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
drivers/crypto/qce/core.c | 4 ++++
drivers/dma/qcom/bam_dma.c | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 9a7d7ef94687..3e742e9911fa 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -15,6 +15,7 @@
#include <linux/types.h>
#include <crypto/algapi.h>
#include <crypto/internal/hash.h>
+#include <soc/qcom/bam_dma.h>
#include "core.h"
#include "cipher.h"
@@ -201,6 +202,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
of_match_device(qce_crypto_of_match, &pdev->dev);
int ret;
+ /* qce driver requires BAM dma driver to be setup first */
+ if (!bam_is_probed())
+ return -EPROBE_DEFER;
qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
if (!qce)
diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index 2bc3b7c7ee5a..c854fcc82dbf 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.c
@@ -935,6 +935,12 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
INIT_LIST_HEAD(&bchan->desc_list);
}
+bool bam_is_probed(void)
+{
+ return bam_probed;
+}
+EXPORT_SYMBOL_GPL(bam_is_probed);
+
static const struct of_device_id bam_of_match[] = {
{ .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
{ .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
@@ -1084,6 +1090,7 @@ static int bam_dma_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_dma;
+ bam_probed = true;
if (!bdev->bamclk) {
pm_runtime_disable(&pdev->dev);
return 0;
--
2.30.2
On some Qualcomm parts the qce crypto driver needs the interconnect between
the crypto block and main memory to be initialized first before the crypto
registers can be accessed. So it makes sense to defer the qce crypto driver
probing in case the interconnect driver is not yet probed.
This fixes the qce probe failure issues when both qce and
interconnect drivers are compiled as static part of the kernel.
Cc: Thara Gopinath <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Bhupesh Sharma <[email protected]>
---
drivers/crypto/qce/core.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 3e742e9911fa..9915b184f780 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -222,6 +222,20 @@ static int qce_crypto_probe(struct platform_device *pdev)
return ret;
qce->mem_path = of_icc_get(qce->dev, "memory");
+
+ /* Check for NULL return path, which indicates
+ * interconnect API is disabled or the "interconnects"
+ * DT property is missing.
+ */
+ if (!qce->mem_path)
+ /* On some qcom parts, the qce crypto block needs interconnect
+ * paths to be configured before the registers can be accessed.
+ * Check here for the same.
+ */
+ if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") ||
+ !strcmp(of_id->compatible, "qcom,sdm845-qce"))
+ return -EPROBE_DEFER;
+
if (IS_ERR(qce->mem_path))
return PTR_ERR(qce->mem_path);
--
2.30.2
On Thu, May 06, 2021 at 03:07:14AM +0530, Bhupesh Sharma wrote:
>
> Tested the enabled crypto algorithms with cryptsetup test utilities
> on sm8250-mtp and RB5 board (see [1]).
>
Does this driver also pass the crypto self-tests, including the fuzz tests
(CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y)?
- Eric
Hello Eric,
On Thu, 6 May 2021 at 03:39, Eric Biggers <[email protected]> wrote:
>
> On Thu, May 06, 2021 at 03:07:14AM +0530, Bhupesh Sharma wrote:
> >
> > Tested the enabled crypto algorithms with cryptsetup test utilities
> > on sm8250-mtp and RB5 board (see [1]).
> >
>
> Does this driver also pass the crypto self-tests, including the fuzz tests
> (CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y)?
I did try running these self-tests and they pass with
'CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y' as well. Do note that we need
the AEAD fixes from Thara (see[1]) for all of the fuzz tests to work
(so my patches are actually rebased on this series).
[1]. https://lore.kernel.org/linux-crypto/[email protected]/T/
Thanks,
Bhupesh
On Thu, May 06, 2021 at 03:07:14AM +0530, Bhupesh Sharma wrote:
> Changes since v1:
> =================
> - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - v1 did not work well as reported earlier by Dmitry, so v2 contains the following
> changes/fixes:
> ~ Enable the interconnect path b/w BAM DMA and main memory first
> before trying to access the BAM DMA registers.
> ~ Enable the interconnect path b/w qce crytpo and main memory first
> before trying to access the qce crypto registers.
> ~ Make sure to document the required and optional properties for both
> BAM DMA and qce crypto drivers.
> ~ Add a few debug related print messages in case the qce crypto driver
> passes or fails to probe.
> ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
> or the interconnect driver(s) (needed on specific Qualcomm parts) are not
> yet probed.
>
> Qualcomm crypto engine is also available on sm8250 SoC.
> It supports hardware accelerated algorithms for encryption
> and authentication. It also provides support for aes, des, 3des
> encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
> authentication algorithms.
>
> Tested the enabled crypto algorithms with cryptsetup test utilities
> on sm8250-mtp and RB5 board (see [1]).
>
> While at it, also make a minor fix in 'sdm845.dtsi', to make
> sure it confirms with the other .dtsi files which expose
> crypto nodes on qcom SoCs.
>
> Cc: Thara Gopinath <[email protected]>
> Cc: Bjorn Andersson <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Andy Gross <[email protected]>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: Michael Turquette <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
>
> Bhupesh Sharma (14):
> dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to
> optional properties
> dt-bindings: qcom-bam: Add 'iommus' to required properties
> dt-bindings: qcom-qce: Add 'iommus' to required properties
> dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to
> optional properties
> arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
> dt-bindings: crypto : Add new compatible strings for qcom-qce
Please convert these bindings to schemas.
> arm64/dts: qcom: Use new compatibles for crypto nodes
> crypto: qce: Add new compatibles for qce crypto driver
> crypto: qce: Print a failure msg in case probe() fails
> crypto: qce: Convert the device found dev_dbg() to dev_info()
> dma: qcom: bam_dma: Create a new header file for BAM DMA driver
> crypto: qce: Defer probing if BAM dma is not yet initialized
> crypto: qce: Defer probe in case interconnect is not yet initialized
> arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
>
> Thara Gopinath (3):
> dma: qcom: bam_dma: Add support to initialize interconnect path
> crypto: qce: core: Add support to initialize interconnect path
> crypto: qce: core: Make clocks optional
>
> .../devicetree/bindings/crypto/qcom-qce.txt | 22 +-
> .../devicetree/bindings/dma/qcom_bam_dma.txt | 5 +
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +-
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++
> drivers/crypto/qce/core.c | 112 +++++--
> drivers/crypto/qce/core.h | 3 +
> drivers/dma/qcom/bam_dma.c | 306 ++----------------
> include/soc/qcom/bam_dma.h | 290 +++++++++++++++++
> 9 files changed, 457 insertions(+), 317 deletions(-)
> create mode 100644 include/soc/qcom/bam_dma.h
>
> --
> 2.30.2
>
Hi Rob,
On Sat, 8 May 2021 at 02:44, Rob Herring <[email protected]> wrote:
>
> On Thu, May 06, 2021 at 03:07:14AM +0530, Bhupesh Sharma wrote:
> > Changes since v1:
> > =================
> > - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> > - v1 did not work well as reported earlier by Dmitry, so v2 contains the following
> > changes/fixes:
> > ~ Enable the interconnect path b/w BAM DMA and main memory first
> > before trying to access the BAM DMA registers.
> > ~ Enable the interconnect path b/w qce crytpo and main memory first
> > before trying to access the qce crypto registers.
> > ~ Make sure to document the required and optional properties for both
> > BAM DMA and qce crypto drivers.
> > ~ Add a few debug related print messages in case the qce crypto driver
> > passes or fails to probe.
> > ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
> > or the interconnect driver(s) (needed on specific Qualcomm parts) are not
> > yet probed.
> >
> > Qualcomm crypto engine is also available on sm8250 SoC.
> > It supports hardware accelerated algorithms for encryption
> > and authentication. It also provides support for aes, des, 3des
> > encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
> > authentication algorithms.
> >
> > Tested the enabled crypto algorithms with cryptsetup test utilities
> > on sm8250-mtp and RB5 board (see [1]).
> >
> > While at it, also make a minor fix in 'sdm845.dtsi', to make
> > sure it confirms with the other .dtsi files which expose
> > crypto nodes on qcom SoCs.
> >
> > Cc: Thara Gopinath <[email protected]>
> > Cc: Bjorn Andersson <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Cc: Andy Gross <[email protected]>
> > Cc: Herbert Xu <[email protected]>
> > Cc: David S. Miller <[email protected]>
> > Cc: Stephen Boyd <[email protected]>
> > Cc: Michael Turquette <[email protected]>
> > Cc: Vinod Koul <[email protected]>
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> >
> > Bhupesh Sharma (14):
> > dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to
> > optional properties
> > dt-bindings: qcom-bam: Add 'iommus' to required properties
> > dt-bindings: qcom-qce: Add 'iommus' to required properties
> > dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to
> > optional properties
> > arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly
> > dt-bindings: crypto : Add new compatible strings for qcom-qce
>
> Please convert these bindings to schemas.
Ok, will fix it in v3.
Thanks,
Bhupesh
>
> > arm64/dts: qcom: Use new compatibles for crypto nodes
> > crypto: qce: Add new compatibles for qce crypto driver
> > crypto: qce: Print a failure msg in case probe() fails
> > crypto: qce: Convert the device found dev_dbg() to dev_info()
> > dma: qcom: bam_dma: Create a new header file for BAM DMA driver
> > crypto: qce: Defer probing if BAM dma is not yet initialized
> > crypto: qce: Defer probe in case interconnect is not yet initialized
> > arm64/dts: qcom: sm8250: Add dt entries to support crypto engine.
> >
> > Thara Gopinath (3):
> > dma: qcom: bam_dma: Add support to initialize interconnect path
> > crypto: qce: core: Add support to initialize interconnect path
> > crypto: qce: core: Make clocks optional
> >
> > .../devicetree/bindings/crypto/qcom-qce.txt | 22 +-
> > .../devicetree/bindings/dma/qcom_bam_dma.txt | 5 +
> > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
> > arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +-
> > arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++
> > drivers/crypto/qce/core.c | 112 +++++--
> > drivers/crypto/qce/core.h | 3 +
> > drivers/dma/qcom/bam_dma.c | 306 ++----------------
> > include/soc/qcom/bam_dma.h | 290 +++++++++++++++++
> > 9 files changed, 457 insertions(+), 317 deletions(-)
> > create mode 100644 include/soc/qcom/bam_dma.h
> >
> > --
> > 2.30.2
> >
On 5/5/21 5:37 PM, Bhupesh Sharma wrote:
> Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> setup first (to allow crypto operations), it makes sense to defer
> the qce crypto driver probing in case the BAM dma driver is not yet
> probed.
>
> This fixes the qce probe failure issues when both qce and BMA dma
> are compiled as static part of the kernel.
>
> Cc: Thara Gopinath <[email protected]>
> Cc: Bjorn Andersson <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Andy Gross <[email protected]>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: Michael Turquette <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Bhupesh Sharma <[email protected]>
> ---
> drivers/crypto/qce/core.c | 4 ++++
> drivers/dma/qcom/bam_dma.c | 7 +++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 9a7d7ef94687..3e742e9911fa 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -15,6 +15,7 @@
> #include <linux/types.h>
> #include <crypto/algapi.h>
> #include <crypto/internal/hash.h>
> +#include <soc/qcom/bam_dma.h>
>
> #include "core.h"
> #include "cipher.h"
> @@ -201,6 +202,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
> of_match_device(qce_crypto_of_match, &pdev->dev);
> int ret;
>
> + /* qce driver requires BAM dma driver to be setup first */
> + if (!bam_is_probed())
> + return -EPROBE_DEFER;
Hi Bhupesh,
You don't need this here. qce_dma_request returns -EPROBE_DEFER if the
dma controller is not probed yet.
--
Warm Regards
Thara
>
> qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
> if (!qce)
> diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
> index 2bc3b7c7ee5a..c854fcc82dbf 100644
> --- a/drivers/dma/qcom/bam_dma.c
> +++ b/drivers/dma/qcom/bam_dma.c
> @@ -935,6 +935,12 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
> INIT_LIST_HEAD(&bchan->desc_list);
> }
>
> +bool bam_is_probed(void)
> +{
> + return bam_probed;
> +}
> +EXPORT_SYMBOL_GPL(bam_is_probed);
> +
> static const struct of_device_id bam_of_match[] = {
> { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
> { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
> @@ -1084,6 +1090,7 @@ static int bam_dma_probe(struct platform_device *pdev)
> if (ret)
> goto err_unregister_dma;
>
> + bam_probed = true;
> if (!bdev->bamclk) {
> pm_runtime_disable(&pdev->dev);
> return 0;
>
Hi Thara,
On Mon, 10 May 2021 at 18:53, Thara Gopinath <[email protected]> wrote:
>
>
>
> On 5/5/21 5:37 PM, Bhupesh Sharma wrote:
> > On some Qualcomm parts the qce crypto driver needs the interconnect between
> > the crypto block and main memory to be initialized first before the crypto
> > registers can be accessed. So it makes sense to defer the qce crypto driver
> > probing in case the interconnect driver is not yet probed.
> >
> > This fixes the qce probe failure issues when both qce and
> > interconnect drivers are compiled as static part of the kernel.
> >
> > Cc: Thara Gopinath <[email protected]>
> > Cc: Bjorn Andersson <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Cc: Andy Gross <[email protected]>
> > Cc: Herbert Xu <[email protected]>
> > Cc: David S. Miller <[email protected]>
> > Cc: Stephen Boyd <[email protected]>
> > Cc: Michael Turquette <[email protected]>
> > Cc: Vinod Koul <[email protected]>
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Signed-off-by: Bhupesh Sharma <[email protected]>
> > ---
> > drivers/crypto/qce/core.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index 3e742e9911fa..9915b184f780 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -222,6 +222,20 @@ static int qce_crypto_probe(struct platform_device *pdev)
> > return ret;
> >
> > qce->mem_path = of_icc_get(qce->dev, "memory");
> > +
> > + /* Check for NULL return path, which indicates
> > + * interconnect API is disabled or the "interconnects"
> > + * DT property is missing.
> > + */
> > + if (!qce->mem_path)
> > + /* On some qcom parts, the qce crypto block needs interconnect
> > + * paths to be configured before the registers can be accessed.
> > + * Check here for the same.
> > + */
> > + if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") ||
> > + !strcmp(of_id->compatible, "qcom,sdm845-qce"))
> > + return -EPROBE_DEFER;
> > +
>
> Hi Bhupesh,
>
> You don't need this here. of_icc_get returns -EPROBE_DEFER if the
> interconnect provider is not initialized yet.
Thanks for the review.
Yes, I finished testing all the possible combinations with qce, bam
dma and interconnect drivers compiled as modules v/s as static parts
of the kernel and we don't need this extra check for the interconnect
here. We should be fine with checking just the qce_dma_request()
return value and returning early in the qce probe() flow if no dma
channels are yet available from the bam dma driver.
I have made the changes in v3 and will post it for review shortly.
Regards,
Bhupesh
HI Thara,
On Mon, 10 May 2021 at 18:52, Thara Gopinath <[email protected]> wrote:
>
>
>
> On 5/5/21 5:37 PM, Bhupesh Sharma wrote:
> > Since the Qualcomm qce crypto driver needs the BAM dma driver to be
> > setup first (to allow crypto operations), it makes sense to defer
> > the qce crypto driver probing in case the BAM dma driver is not yet
> > probed.
> >
> > This fixes the qce probe failure issues when both qce and BMA dma
> > are compiled as static part of the kernel.
> >
> > Cc: Thara Gopinath <[email protected]>
> > Cc: Bjorn Andersson <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Cc: Andy Gross <[email protected]>
> > Cc: Herbert Xu <[email protected]>
> > Cc: David S. Miller <[email protected]>
> > Cc: Stephen Boyd <[email protected]>
> > Cc: Michael Turquette <[email protected]>
> > Cc: Vinod Koul <[email protected]>
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Signed-off-by: Bhupesh Sharma <[email protected]>
> > ---
> > drivers/crypto/qce/core.c | 4 ++++
> > drivers/dma/qcom/bam_dma.c | 7 +++++++
> > 2 files changed, 11 insertions(+)
> >
> > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> > index 9a7d7ef94687..3e742e9911fa 100644
> > --- a/drivers/crypto/qce/core.c
> > +++ b/drivers/crypto/qce/core.c
> > @@ -15,6 +15,7 @@
> > #include <linux/types.h>
> > #include <crypto/algapi.h>
> > #include <crypto/internal/hash.h>
> > +#include <soc/qcom/bam_dma.h>
> >
> > #include "core.h"
> > #include "cipher.h"
> > @@ -201,6 +202,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
> > of_match_device(qce_crypto_of_match, &pdev->dev);
> > int ret;
> >
> > + /* qce driver requires BAM dma driver to be setup first */
> > + if (!bam_is_probed())
> > + return -EPROBE_DEFER;
>
> Hi Bhupesh,
>
> You don't need this here. qce_dma_request returns -EPROBE_DEFER if the
> dma controller is not probed yet.
Thanks for the review.
Yes, we can just use qce_dma_request() return value to return from the
qce probe() function early, in case the bam dma channels are not
available yet.
I have made the changes in v3 and will post it for review shortly.
Regards,
Bhupesh
> >
> > qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
> > if (!qce)
> > diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
> > index 2bc3b7c7ee5a..c854fcc82dbf 100644
> > --- a/drivers/dma/qcom/bam_dma.c
> > +++ b/drivers/dma/qcom/bam_dma.c
> > @@ -935,6 +935,12 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
> > INIT_LIST_HEAD(&bchan->desc_list);
> > }
> >
> > +bool bam_is_probed(void)
> > +{
> > + return bam_probed;
> > +}
> > +EXPORT_SYMBOL_GPL(bam_is_probed);
> > +
> > static const struct of_device_id bam_of_match[] = {
> > { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
> > { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
> > @@ -1084,6 +1090,7 @@ static int bam_dma_probe(struct platform_device *pdev)
> > if (ret)
> > goto err_unregister_dma;
> >
> > + bam_probed = true;
> > if (!bdev->bamclk) {
> > pm_runtime_disable(&pdev->dev);
> > return 0;
> >
>